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CO2005: Electronics I

The Field-Effect Transistor The Field Effect Transistor

(FET)

Electronics I, Neamen 3th Ed. 1

(2)

 The metal-oxide-semiconductor field-effect transistor (MOSFET) becomes a practical

MOSFET

reality in the 1970s.

 The MOSFET, compared to BJTs, can be made very small, that is, it occupies a very small area in IC chip.

 In the MOSFET, the current is controlled by an electric field applied perpendicular to both the semiconductor surface and to the direction of current.

 The phenomenon applying an electric field perpendicular to the surface is called the field effect

effect.

 Basic MOS capacitor structure

(3)

The Physics of the MOS Capacitor

Gate

Electronics I, Neamen 3th Ed. 3

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The Physics of the MOS Capacitor for N-type Semiconductor Substrate

 Enhancement mode: a voltage must be applied to the gate to create an inversion layer

 Enhancement mode: a voltage must be applied to the gate to create an inversion layer.

 P-type: a positive gate voltage must be applied to create the electron inversion layer

 N-type: a negative gate voltage must be applied to create the hole inversion layer

(5)

 Transistor Structure

NMOS

Large enough positive

 Transistor Operation

g g p

voltage induces an electron inversion layer.

Connection between D and S is created so that a

current can be generated

Electronics I, Neamen 3th Ed. 5

current can be generated.

(6)

 The threshold voltage of the n-channel MOSFET is denoted as and is defined as the

MOSFET Current-Voltage Characteristics

VTN

applied gate voltage needed to create an inversion charge.

 We can think of the threshold voltage as the gate voltage required to “turn on” the transistor.

(7)

 The versus characteristics for small values of

MOSFET Current-Voltage Characteristics

i

D

v

DS

v

DS

Electronics I, Neamen 3th Ed. 7

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MOSFET Current-Voltage Characteristics

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 Nonsaturation (triode) Region

Ideal MOSFET Current-Voltage Characteristics

TN GS

sat DS

DS

v v V

v

( )

 

) 2

( ]

) (

2

[ v V v v

2

K v

( )

v v

2

K

i     

 Saturation Region

) 2

( ]

) (

2

[

GS TN DS DS n DS(sat) DS DS

n

D

K v V v v K v v v

i  

) also

( v V

v

v

DS

v

DS(sat)

( also v

GS

V

TN

)

v  

)

2

(

GS TN

n

D

K v V

i  

Note: In the saturation region

D DS

o

v r 1 i /

Note: In the saturation region,

Electronics I, Neamen 3th Ed. 9

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 Conduction Parameter

Conduction Parameter

2

ox n n

C L

K W

(conduction parameter)

1 C

ox

n

W

: oxide capacitance per unit area : electron mobility

: channel width

thickness oxide

: 1 ,

ox ox

ox

t

Ct

 The conduction parameter is a function of both electrical and geometric parameters.

W L

: channel width : channel length

 The conduction parameter is a function of both electrical and geometric parameters.

 Electrical Parameters: The oxide capacitance and carrier mobility are essentially constants for a given technology.

k W

 Geometrical Parameters: The width-to-length ratio (W/L) is a variable in the design of

constant :

2

n

n

n

k k

L

K W  

g ( ) g

MOSFETs that is used to produce specific current-voltage characteritics in MOSFET

(11)

Electronics I, Neamen 3th Ed. 11

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 In the p-channel enhancement-mode device, a negative gate-to-source voltage must be

PMOS

applied to create the inversion layer of holes that connects the source and drain regions.

 The threshold voltage, denoted an for the PMOS is negative for an enhancement- mode devices. The threshold voltage is positive for a depletion-mode device.TP

V

 Holes flow from the source to the drain, the conventional current enters the source and leaves the drain.

(13)

 Nonsaturation (triode) Region

Ideal PMOS Current-Voltage Relationship

:

when v

SD

v

SD(sat)

v

SG

V

TP

) 2

( ]

) (

2

[ v V v v

2

K v

( )

v v

2

K

i     

 Saturation Region

) 2

( ]

) (

2

[

SG TP SD SD p SD(sat) SD SD

p

D

K v V v v K v v v

i   

: ) 0 also

(

when vv ( also vV  0 ) : i K ( V )

2

when v

SD

v

SD(sat)

v

SG

V

TP

i

D

K

p

( v

SG

V

TP

)

2

Electronics I, Neamen 3th Ed. 13

(14)

Circuit Symbols

N channel enhancement N-channel enhancement- mode MOSFET

P-channel enhancement- P channel enhancement mode MOSFET

(15)

 Complement MOS (CMOS) technology uses both NMOS and PMOS in the same circuit.

CMOS

 To design electrically equivalent NMOS and PMOS devices, adjusting the W/L ratios of the transistors is required.

Electronics I, Neamen 3th Ed. 15

(16)

Summary of MOS Transistor Operation

(17)

NMOS Common-Source Circuit

Electronics I, Neamen 3th Ed. 17

(18)

PMOS Common-Source Circuit

(19)

Electronics I, Neamen 3th Ed. 19

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(21)

Electronics I, Neamen 3th Ed. 21

(22)
(23)

 Load Line

Load Line

5

) 20 ( 5

D

D D DD

DS

V

I R

I V

V    

) mA 20 (

20

5

DS

D

I   V

Electronics I, Neamen 3th Ed. 23

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(25)

Electronics I, Neamen 3th Ed. 25

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(27)

中央大學通訊系 張大中 Electronics I, Neamen 3th Ed. 27

(28)

 An enhancement-mode MOSFET is used as a nonlinear resistor.

Nonlinear Resistor

 The transistor is always biased in the saturation region and called a load device.

)

(Sat GS TN

,

TN

0

DS GS

DS

v v v V V

v     

2 2

) (

) (

)

(

GS TN n DS TN

n

D

K v V K v V

i    

(29)

Electronics I, Neamen 3th Ed. 29

(30)
(31)

Electronics I, Neamen 3th Ed. 31

(32)

CMOS Inverter

(33)

 If , the transistor is in cut-off.

NMOS Inverter

TN

I V

v

DD O

D

V

v

i  0 

 If (and make ), the transistor is biased in the non-saturation region. vIVTN

2

DS TN

I

V v

v  

D D DD

O

O O

TN I

n D

R i v

v

v v

V v

K i

 [ 2 ( )

2

]

Electronics I, Neamen 3th Ed. 33

(34)
(35)

Digital Logic Gate

Electronics I, Neamen 3th Ed. 35

(36)

 We can establish a particular Q-point on the load line by designing the ratio of the bias

MOS Small-Signal Amplifier

resistors and .

R

1

R

2

(37)

Constant-Current Biasing

Electronics I, Neamen 3th Ed. 37

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(39)

中央大學通訊系 張大中 Electronics I, Neamen 3th Ed. 39

(40)
(41)

Constant-Current Biasing

2 4 4

4 2

3 3

3

(

GS TN

)

n

(

GS TN

)

n

V V K V V

K   

V V

V

GS4 GS3

4 3

3 4

3

/

n

n TN

TN GS

K K

V V

VV  

4 3

3

1

n

/

n

GS

K K

2 2 3

2

(

GS TN

)

n

Q

K V V

I  

Electronics I, Neamen 3th Ed. 41

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(43)

Multitransistor Circuit: Cascade Configuration

中央大學通訊系 張大中 Electronics I, Neamen 3th Ed. 43

(44)
(45)

Multitransistor Circuit: Cascode Configuration

中央大學通訊系 張大中 Electronics I, Neamen 3th Ed. 45

(46)

References

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