Questa
SIM User’s Manual
Including Support for Questa SV/AFV
Software Version 10.0d
© 1991-2011 Mentor Graphics Corporation All rights reserved.
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Table of Contents
Chapter 1
Introduction. . . . 57
Operational Structure and Flow . . . 57
Simulation Task Overview . . . 58
Basic Steps for Simulation. . . 60
Step 1 — Collect Files and Map Libraries . . . 60
Step 2 — Compile the Design . . . 62
Step 3 — Load the Design for Simulation . . . 63
Step 4 — Simulate the Design . . . 63
Step 5 — Debug the Design . . . 63
Modes of Operation . . . . 64
Command Line Mode . . . 65
Batch Mode. . . 66
Definition of an Object . . . . 66
Graphic Interface Overview. . . 67
Standards Supported . . . . 67
Assumptions. . . 68
Text Conventions . . . 69
Installation Directory Pathnames. . . 69
Where to Find Questa SIM Documentation. . . 69
Mentor Graphics Support. . . 70
Deprecated Features, Commands, and Variables . . . 71
Chapter 2 Graphical User Interface . . . . 73
Design Object Icons and Their Meaning . . . 76
Setting Fonts . . . 77
Using the Find and Filter Functions . . . 78
Using the Find Options Popup Menu . . . 81
User-Defined Radices . . . 81
Using the radix define Command . . . 82
Saving and Reloading Formats and Content . . . 86
Active Time Label . . . 86
Main Window . . . 87
Elements of the Main Window . . . 87
Selecting the Active Window . . . 94
Rearranging the Main Window. . . 94
Navigating in the Main Window . . . 96
Main Window Menu Bar . . . 96
Main Window Toolbar . . . 105
Assertions Window . . . 129
GUI Elements of the Assertions Window. . . 130
ATV Window. . . 134
ATV Window Tasks . . . 135
GUI Elements of the ATV Window . . . 135
Call Stack Window . . . 137
Call Stack Window Tasks. . . 138
Related Commands of the Call Stack Window. . . 139
GUI Elements of the Call Stack Window . . . 139
Capacity Window. . . 139
GUI Elements of the Capacity Window . . . 140
Class Graph Window . . . 142
Class Graph Window Tasks . . . 142
GUI Elements of the Class Graph Window . . . 143
Class Tree Window . . . 144
GUI Elements of the Class Tree Window. . . 144
Code Coverage Analysis Window . . . 146
Viewing Code Coverage Data and Current Exclusions . . . 148
Coverage Details Window . . . 150
Cover Directives Window . . . 154
GUI Elements of the Cover Directives Window . . . 155
Cover Directives Window Tasks . . . 156
Covergroups Window . . . 157
GUI Elements of the Covergroups Window. . . 158
Covergroups Window Tasks. . . 159
Dataflow Window . . . 160
Dataflow Window Tasks. . . 161
Files Window . . . 164
GUI Elements of the Files Window . . . 165
FSM List Window . . . 167
GUI Elements of the FSM List Window . . . 168
FSM Viewer Window . . . 169
FSM Viewer Window Tasks. . . 170
GUI Elements of the FSM Viewer Window. . . 174
Instance Coverage Window . . . 176
Instance Coverage Window Tasks . . . 177
GUI Elements of the Instance Coverage Window . . . 178
Library Window. . . 179
GUI Elements of the Library Window . . . 179
List Window. . . 181
List Window Tasks . . . 182
GUI Elements of the List Window . . . 183
Locals Window . . . 185
Locals Window Tasks. . . 186
GUI Elements of the Locals Window. . . 186
Memory List Window . . . 188
Memory List Window Tasks . . . 190
GUI Elements of the Memory List Window. . . 191
Memory Data Window . . . 192
GUI Elements of the Memory Data Window . . . 194
Message Viewer Window . . . 195
Message Viewer Window Tasks. . . 197
GUI Elements of the Message Viewer Window. . . 198
Objects Window. . . 202
Objects Window Tasks . . . 203
GUI Elements of the Objects Window . . . 206
Processes Window . . . 207
Processes Window Tasks . . . 208
GUI Elements of the Processes Window . . . 210
Profiling Windows . . . 212
GUI Elements of the Profile Windows . . . 215
Schematic Window . . . 216
Schematic Window Tasks. . . 218
GUI Elements of the Schematic Window. . . 223
Source Window . . . 226
Opening Source Files . . . 228
Displaying Multiple Source Files . . . 228
Dragging and Dropping Objects into the Wave and List Windows . . . 229
Setting your Context by Navigating Source Files. . . 229
Coverage Data in the Source Window . . . 231
Debugging with Source Annotation . . . 234
Accessing Textual Connectivity Information . . . 236
Using Language Templates. . . 237
Setting File-Line Breakpoints with the GUI. . . 240
Adding File-Line Breakpoints with the bp Command . . . 241
Editing File-Line Breakpoints. . . 242
Setting Conditional Breakpoints . . . 244
Checking Object Values and Descriptions . . . 246
Marking Lines with Bookmarks . . . 247
Performing Incremental Search for Specific Code . . . 247
Customizing the Source Window . . . 248
Structure Window . . . 249
Viewing the Structure Window . . . 250
Structure Window Tasks. . . 250
GUI Elements of the Structure Window. . . 253
Code Coverage in the Structure Window . . . 257
Verification Management Browser Window . . . 258
Controlling the Verification Browser Columns . . . 259
Saving Verification Browser Column and Filter Settings . . . 259
GUI Elements of the Verification Browser Window . . . 259
Verification Results Analysis Window . . . 262
Verification Test Analysis Window. . . 262
Verification Tracker Window . . . 262
Verification Trender Window . . . 262
Transaction View Window . . . 262
Transcript Window . . . 262
Displaying the Transcript Window. . . 263
Transcript Window Tasks . . . 263
GUI Elements of the Transcript Window . . . 264
Watch Window . . . 265
Adding Objects to the Watch Window . . . 267
Expanding Objects to Show Individual Bits. . . 267
Grouping and Ungrouping Objects. . . 268
Saving and Reloading Format Files . . . 269
Wave Window . . . 269
Add Objects to the Wave Window . . . 270
Wave Window Panes . . . 271
Objects You Can View in the Wave Window . . . 278
Wave Window Toolbar. . . 280
Chapter 3 Protecting Your Source Code . . . 281
Creating Encryption Envelopes . . . 281
Configuring the Encryption Envelope . . . 282
Protection Expressions . . . 284
Using the `include Compiler Directive (Verilog only) . . . 286
Compiling with +protect . . . 289
The Runtime Encryption Model . . . 290
Language-Specific Usage Models . . . 291
Usage Models for Protecting Verilog Source Code . . . 291
Usage Models for Protecting VHDL Source Code. . . 296
Proprietary Source Code Encryption Tools . . . 303
Using Proprietary Compiler Directives . . . 304
Protecting Source Code Using -nodebug . . . 305
Encryption Reference. . . 306
Encryption and Encoding Methods. . . 307
How Encryption Envelopes Work . . . 308
Using Public Encryption Keys . . . 309
Using the Mentor Graphics Public Encryption Key . . . 309
. . . 311
Chapter 4 Optimizing Designs with vopt . . . 313
Optimization Flows . . . 313
Three-Step Flow . . . 313
Two-Step Flow . . . 316
Using vopt and the -O Optimization Control Switches . . . 317
Inlining and the Implications of Coverage Settings . . . 318
Optimizing Parameters and Generics. . . 318
Optimizing Portions of your Design . . . 319
Simulating Designs with Several Different Test Benches . . . 320
Using Configurations with Blackboxed Designs . . . 321
Resolving Blackboxed Design Loading Errors. . . 324
Alternate Optimization Flows . . . 325
Optimizing Liberty Cell Libraries for Debugging . . . 326
Creating an Environment for Optimized and Unoptimized Flows . . . 326
Preserving Design Visibility with the Learn Flow . . . 327
Description of Learn Flow Control Files . . . 329
Controlling Optimization from the GUI . . . 329
Optimization Considerations for Verilog Designs. . . 329
Design Object Visibility for Designs with PLI. . . 330
Performing Optimization on Designs Containing SDF . . . 331
Reporting on Gate-Level Optimizations. . . 332
Using Pre-Compiled Libraries . . . 332
Event Order and Optimized Designs . . . 332
Timing Checks in Optimized Designs . . . 332
Chapter 5 Projects. . . 335
What are Projects? . . . 335
What are the Benefits of Projects? . . . 335
Project Conversion Between Versions . . . 336
Getting Started with Projects . . . 336
Step 1 — Creating a New Project . . . 337
Step 2 — Adding Items to the Project . . . 338
Step 3 — Compiling the Files. . . 339
Step 4 — Simulating a Design . . . 342
Other Basic Project Operations. . . 344
The Project Window . . . 344
Sorting the List . . . 345
Creating a Simulation Configuration . . . 345
Optimization Configurations . . . 347
Organizing Projects with Folders. . . 347
Adding a Folder . . . 347
Specifying File Properties and Project Settings. . . 349
File Compilation Properties . . . 349
Project Settings . . . 351
Accessing Projects from the Command Line. . . 352
Chapter 6 Design Libraries . . . 353
Design Library Overview . . . 353
Design Unit Information . . . 353
Working Library Versus Resource Libraries . . . 353
Archives . . . 354
Working with Design Libraries . . . 354
Creating a Library . . . 355
Managing Library Contents . . . 355
Assigning a Logical Name to a Design Library . . . 357
Moving a Library . . . 358
Setting Up Libraries for Group Use . . . 359
Verilog Resource Libraries . . . 359
VHDL Resource Libraries . . . 359
Predefined Libraries . . . 360
Alternate IEEE Libraries Supplied . . . 360
Regenerating Your Design Libraries . . . 361
Maintaining 32- and 64-bit Versions in the Same Library . . . 361
Importing FPGA Libraries. . . 362
Protecting Source Code . . . 363
Chapter 7 VHDL Simulation . . . 365
Basic VHDL Usage . . . 365
Compilation and Simulation of VHDL . . . 365
Creating a Design Library for VHDL. . . 365
Compiling a VHDL Design—the vcom Command . . . 366
Simulating a VHDL Design . . . 370
Naming Behavior of VHDL For Generate Blocks . . . 371
Differences Between Versions of VHDL . . . 372
Foreign Language Interface . . . 375
Simulator Resolution Limit for VHDL. . . 375
Default Binding. . . 376
Delta Delays . . . 377
Using the TextIO Package . . . 379
Syntax for File Declaration. . . 380
Using STD_INPUT and STD_OUTPUT Within Questa SIM . . . 380
TextIO Implementation Issues . . . 381
Writing Strings and Aggregates . . . 381
Reading and Writing Hexadecimal Numbers . . . 382
Dangling Pointers . . . 382
The ENDLINE Function. . . 382
The ENDFILE Function . . . 383
Using Alternative Input/Output Files . . . 383
Flushing the TEXTIO Buffer . . . 383
Providing Stimulus . . . 383
VITAL Usage and Compliance . . . 384
VITAL Source Code . . . 384
VITAL 1995 and 2000 Packages . . . 384
VITAL Compliance . . . 385
Compiling and Simulating with Accelerated VITAL Packages . . . 386
Compiler Options for VITAL Optimization . . . 386
VHDL Utilities Package (util) . . . 387
get_resolution . . . 387 init_signal_driver() . . . 388 init_signal_spy() . . . 388 signal_force() . . . 388 signal_release() . . . 388 to_real(). . . 388 to_time() . . . 389
Modeling Memory . . . 390
Examples of Different Memory Models . . . 391
Affecting Performance by Cancelling Scheduled Events. . . 400
Chapter 8 Verilog and SystemVerilog Simulation. . . 401
Standards, Nomenclature, and Conventions . . . 401
Alternative One-Step Flow . . . 403
Basic Verilog Usage . . . 403
Verilog Compilation . . . 404
Creating a Working Library . . . 404
Invoking the Verilog Compiler. . . 404
Initializing enum Variables. . . 407
Incremental Compilation . . . 407
Library Usage . . . 410
SystemVerilog Multi-File Compilation . . . 411
Verilog-XL Compatible Compiler Arguments . . . 413
Verilog-XL uselib Compiler Directive . . . 413
Verilog Configurations . . . 416
Verilog Generate Statements . . . 417
Initializing Registers and Memories . . . 418
Verilog Simulation. . . 420
Simulator Resolution Limit (Verilog). . . 421
Event Ordering in Verilog Designs. . . 423
Debugging Event Order Issues . . . 426
Debugging Signal Segmentation Violations. . . 427
Negative Timing Checks. . . 429
Force and Release Statements in Verilog . . . 438
Verilog-XL Compatible Simulator Arguments . . . 438
Using Escaped Identifiers . . . 439
Cell Libraries . . . 440
SDF Timing Annotation . . . 440
Delay Modes . . . 441
Approximating Metastability . . . 442
System Tasks and Functions . . . 443
IEEE Std 1364 System Tasks and Functions . . . 443
SystemVerilog System Tasks and Functions . . . 446
Simulator-Specific System Tasks and Functions . . . 447
Verilog-XL Compatible System Tasks and Functions . . . 453
Compiler Directives . . . 455
IEEE Std 1364 Compiler Directives . . . 456
Compiler Directives for vlog . . . 456
Verilog-XL Compatible Compiler Directives . . . 458
Sparse Memory Modeling . . . 459
Manually Marking Sparse Memories . . . 459
Automatically Enabling Sparse Memories . . . 460
Combining Automatic and Manual Modes. . . 460
Determining Which Memories Were Implemented as Sparse . . . 461
Verilog PLI/VPI and SystemVerilog DPI . . . 462
Standards, Nomenclature, and Conventions . . . 462
Extensions to SystemVerilog DPI . . . 462
OVM-Aware Debug. . . 463
Preparing Your Simulation for OVM-Aware Debug . . . 463
OVM-Aware Debugging Tasks . . . 464
OVM-Aware Debug Windows . . . 465
Chapter 9 SystemC Simulation . . . 467
Supported Platforms and Compiler Versions . . . 467
Building gcc with Custom Configuration Options . . . 468
Usage Flow for SystemC-Only Designs . . . 469
Recommendations for using sc_main at the Top Level . . . 470
Creating Shared Object Files for SystemC Code. . . 473
Binding to Verilog or SystemVerilog Designs . . . 474
Limitations of Bind Support for SystemC . . . 474
Compiling SystemC Files . . . 474
Creating a Design Library for SystemC . . . 475
Invoking the SystemC Compiler. . . 475
Compiling Optimized and/or Debug Code . . . 476
Specifying an Alternate g++ Installation . . . 476
Maintaining Portability Between OSCI and the Simulator. . . 476
Using sccom in Addition to the Raw C++ Compiler . . . 477
Compiling Changed Files Only (Incremental Compilation). . . 478
Issues with C++ Templates. . . 480
Linking the Compiled Source . . . 488
Simulating SystemC Designs. . . 489
Loading the Design . . . 489
Running Simulation . . . 489
SystemC Time Unit and Simulator Resolution. . . 490
Initialization and Cleanup of SystemC State-Based Code . . . 491
Debugging the Design . . . 492
Viewable SystemC Types . . . 492
Viewable SystemC Objects. . . 493
Waveform Compare with SystemC . . . 494
Debugging Source-Level Code. . . 494
SystemC Object and Type Display . . . 498
Support for Globals and Statics . . . 498
Support for Aggregates . . . 499
SystemC Dynamic Module Array. . . 500
Viewing FIFOs . . . 500
Viewing SystemC Memories . . . 501
Properly Recognizing Derived Module Class Pointers . . . 502
Custom Debugging of SystemC Channels and Variables. . . 503
Modifying SystemC Source Code . . . 508
Differences Between the Simulator and OSCI . . . 511
Fixed-Point Types. . . 512
Algorithmic C Datatype Support . . . 513
Support for cin . . . 513
OSCI 2.2 Feature Implementation Details. . . 514
Support for OSCI TLM Library . . . 514
Phase Callback . . . 514
Accessing Command-Line Arguments . . . 514
sc_stop Behavior. . . 515
Construction Parameters for SystemC Types . . . 515
Troubleshooting SystemC Errors. . . 517
Unexplained Behaviors During Loading or Runtime . . . 517
Errors During Loading . . . 517
Chapter 10 Mixed-Language Simulation . . . 523
Basic Mixed-Language Flow. . . 523
Separate Compilers with Common Design Libraries . . . 524
Using Hierarchical References . . . 524
Using SystemVerilog bind Construct in Mixed-Language Designs . . . 526
Syntax of bind Statement . . . 527
What Can Be Bound . . . 527
Hierarchical References to a VHDL Object from a Verilog/SystemVerilog Scope. . . 528
Mapping of Types . . . 529
Using SV Bind With or Without vopt . . . 529
Binding to VHDL Enumerated Types . . . 530
Binding to a VHDL Instance . . . 532
Limitations to Bind Support for SystemC . . . 536
Optimizing Mixed Designs . . . 536
Simulator Resolution Limit . . . 536
Runtime Modeling Semantics . . . 537
Hierarchical References to SystemVerilog. . . 537
Hierarchical References In Mixed HDL and SystemC Designs. . . 537
Signal Connections Between Mixed HDL and SystemC Designs . . . 539
Mapping Data Types . . . 540
Verilog and SystemVerilog to VHDL Mappings . . . 540
VHDL To Verilog and SystemVerilog Mappings . . . 545
Verilog or SystemVerilog and SystemC Signal Interaction And Mappings . . . 552
VHDL and SystemC Signal Interaction And Mappings. . . 560
VHDL Instantiating Verilog or SystemVerilog. . . 566
Verilog/SystemVerilog Instantiation Criteria Within VHDL. . . 566
Component Declaration for VHDL Instantiating Verilog . . . 567
vgencomp Component Declaration when VHDL Instantiates Verilog . . . 568
Modules with Bidirectional Pass Switches . . . 569
Modules with Unnamed Ports. . . 569
Verilog or SystemVerilog Instantiating VHDL. . . 570
VHDL Instantiation Criteria Within Verilog . . . 570
Named Port Associations . . . 572
Generic Associations . . . 572
SDF Annotation . . . 572
Sharing User-Defined Types . . . 573
SystemC Instantiating Verilog or SystemVerilog . . . 578
Verilog Instantiation Criteria Within SystemC. . . 578
SystemC Foreign Module (Verilog) Declaration . . . 579
Parameter Support for SystemC Instantiating Verilog . . . 580
Verilog or SystemVerilog Instantiating SystemC . . . 585
SystemC Instantiation Criteria for Verilog . . . 585
Exporting SystemC Modules for Verilog . . . 585
Parameter Support for Verilog Instantiating SystemC . . . 586
SystemC Instantiating VHDL . . . 588
VHDL Instantiation Criteria Within SystemC . . . 588
SystemC Foreign Module (VHDL) Declaration. . . 589
Generic Support for SystemC Instantiating VHDL . . . 590
VHDL Instantiating SystemC . . . 595
SystemC Instantiation Criteria for VHDL . . . 595
Component Declaration for VHDL Instantiating SystemC . . . 595
vgencomp Component Declaration when VHDL Instantiates SystemC . . . 596
Exporting SystemC Modules for VHDL . . . 596
SystemC Procedural Interface to SystemVerilog . . . 597
Definition of Terms. . . 597
SystemC DPI Usage Flow . . . 598
SystemC Import Functions . . . 598
Calling SystemVerilog Export Tasks / Functions from SystemC . . . 602
SystemC Data Type Support in SystemVerilog DPI . . . 603
SystemC Function Prototype Header File (sc_dpiheader.h). . . 605
Support for Multiple SystemVerilog Libraries . . . 606
SystemC DPI Usage Example . . . 606
Chapter 11 Advanced Simulation Techniques . . . 609
Checkpointing and Restoring Simulations . . . 609
Checkpoint File Contents . . . 609
Controlling Checkpoint File Compression . . . 610
The Difference Between Checkpoint/Restore and Restart . . . 610
Using Macros with Restart and Checkpoint/Restore . . . 610
Checkpointing Foreign C Code That Works with Heap Memory . . . 611
Checkpointing a Running Simulation. . . 611
Simulating with an Elaboration File . . . 613
Why an Elaboration File? . . . 613
Elaboration File Flow . . . 613
Creating an Elaboration File . . . 614
Loading an Elaboration File . . . 614
Modifying Stimulus . . . 615
Chapter 12
Recording and Viewing Transactions . . . 617
Transaction Background . . . 617
What is a Transaction? . . . 618
About the Source Code for Transactions . . . 618
About Transaction Streams. . . 619
Viewing Transactions in the GUI . . . 621
Transaction Viewing Commonalities . . . 621
Viewing Transaction Objects in the Structure Window . . . 623
Viewing Transactions in the Wave Window . . . 623
Viewing a Transaction in the List Window . . . 630
Viewing a Transaction in the Objects Window . . . 631
Debugging with Tcl . . . 632
Transactions in Designs with Questa Verification IP . . . 633
Transaction Recording Flow . . . 633
Transaction Recording Guidelines. . . 636
Names of Streams and Substreams . . . 637
Stream Logging. . . 637
Transaction UIDs . . . 638
Attribute Type. . . 638
Multiple Uses of the Same Attribute . . . 638
Anonymous Attributes . . . 639
Definition of Relationship in Transactions . . . 639
The Life-cycle of a Transaction . . . 640
Transaction Handles and Memory Leaks . . . 641
Transaction Recording Procedures . . . 641
Recording Transactions in Verilog and VHDL . . . 641
Recording Transactions in SystemC. . . 645
SCV Limitations . . . 652
CLI Debugging Command Reference . . . 652
Verilog and VHDL API System Task Reference . . . 653
add_attribute . . . 653 add_relation. . . 654 begin_transaction . . . 655 create_transaction_stream. . . 656 delete_transaction . . . 657 end_transaction . . . 658 free_transaction. . . 659 Chapter 13 Verifying Designs with Questa Verification IP Library Components . . . 661
What is Questa Verification IP? . . . 661
What is a Questa Verification IP Transaction? . . . 662
Questa Verification IP Transaction Relationships . . . 662
Questa Verification IP Transaction Viewing in the GUI. . . 663
Questa Verification IP Objects in the GUI . . . 663
Viewing Questa Verification IP Transactions in the Wave Window . . . 666
Viewing Questa Verification IP Transactions in Objects Window . . . 672
Viewing Questa Verification IP Transactions in List Window . . . 672
Questa Verification IP Transaction Debug . . . 673
Debugging Using Relationships . . . 674
Questa Verification IP Transaction Details in Transaction View Window . . . 675
Chapter 14 Recording Simulation Results With Datasets. . . 679
Saving a Simulation to a WLF File . . . 680
WLF File Parameter Overview. . . 681
Limiting the WLF File Size . . . 682
Multithreading on Linux and Solaris Platforms . . . 683
Opening Datasets . . . 684
Viewing Dataset Structure . . . 684
Structure Tab Columns . . . 685
Managing Multiple Datasets . . . 686
Managing Multiple Datasets in the GUI. . . 686
Command Line . . . 686
Restricting the Dataset Prefix Display . . . 687
Saving at Intervals with Dataset Snapshot. . . 688
Collapsing Time and Delta Steps. . . 689
Virtual Objects . . . 690 Virtual Signals . . . 691 Virtual Functions . . . 692 Virtual Regions . . . 693 Virtual Types . . . 693 Chapter 15 Waveform Analysis. . . 695
Objects You Can View . . . 695
Wave Window Overview. . . 696
Wave Window Panes . . . 696
List Window Overview . . . 698
Adding Objects to the Wave or List Window . . . 698
Adding Objects with Mouse Actions . . . 699
Adding Objects with Menu Selections . . . 699
Adding Objects with a Command. . . 699
Adding Objects with a Window Format File . . . 700
Working with Cursors . . . 700
Cursor and Timeline Toolbox. . . 700
Jumping to a Signal Transition . . . 702
Measuring Time with Cursors in the Wave Window . . . 703
Syncing All Active Cursors . . . 703
Linking Cursors . . . 704
Understanding Cursor Behavior . . . 705
Shortcuts for Working with Cursors . . . 705
Working with Markers . . . 706
Expanded Time in the Wave and List Windows . . . 707
Expanded Time Terminology . . . 707
Recording Expanded Time Information . . . 708
Viewing Expanded Time Information in the Wave Window . . . 708
Selecting the Expanded Time Display Mode . . . 712
Switching Between Time Modes . . . 713
Expanding and Collapsing Simulation Time . . . 713
Expanded Time Viewing in the List Window . . . 714
Zooming the Wave Window Display . . . 716
Zooming with the Menu, Toolbar and Mouse . . . 717
Saving Zoom Range and Scroll Position with Bookmarks. . . 718
Searching in the Wave and List Windows. . . 719
Searching for Values or Transitions . . . 720
Using the Expression Builder for Expression Searches . . . 721
Filtering the Wave Window Display . . . 723
Formatting the Wave Window. . . 723
Setting Wave Window Display Preferences . . . 723
Formatting Objects in the Wave Window . . . 727
Dividing the Wave Window . . . 729
Splitting Wave Window Panes . . . 731
Wave Groups . . . 732
Creating a Wave Group . . . 732
Deleting or Ungrouping a Wave Group . . . 734
Adding Items to an Existing Wave Group . . . 734
Removing Items from an Existing Wave Group. . . 734
Miscellaneous Wave Group Features . . . 735
Composite Signals or Buses . . . 735
Formatting the List Window . . . 736
Setting List Window Display Properties. . . 736
Formatting Objects in the List Window . . . 737
Saving the Window Format . . . 739
Exporting Waveforms from the Wave window . . . 740
Exporting the Wave Window as a Bitmap Image. . . 740
Printing the Wave Window to a Postscript File . . . 741
Printing the Wave Window on the Windows Platform . . . 741
Saving Waveforms Between Two Cursors . . . 741
Saving List Window Data to a File . . . 743
Viewing SystemVerilog Class Objects . . . 744
Combining Objects into Buses . . . 746
Creating a Virtual Signal . . . 747
Configuring New Line Triggering in the List Window . . . 748
Using Gating Expressions to Control Triggering . . . 751
Sampling Signals at a Clock Change . . . 752
Miscellaneous Tasks . . . 753
Examining Waveform Values. . . 753
Displaying Drivers of the Selected Waveform . . . 753
Sorting a Group of Objects in the Wave Window . . . 753
Signal Breakpoints . . . 754
File-Line Breakpoints . . . 756
Saving and Restoring Breakpoints . . . 758
Waveform Compare. . . 758
Mixed-Language Waveform Compare Support . . . 759
Three Options for Setting up a Comparison . . . 759
Setting Up a Comparison with the GUI . . . 761
Starting a Waveform Comparison . . . 761
Adding Signals, Regions, and Clocks. . . 762
Specifying the Comparison Method . . . 764
Setting Compare Options . . . 765
Viewing Differences in the Wave Window . . . 766
Viewing Differences in the List Window . . . 768
Viewing Differences in Textual Format . . . 769
Saving and Reloading Comparison Results . . . 769
Comparing Hierarchical and Flattened Designs . . . 770
Chapter 16 Schematic Window . . . 771
Schematic Window Usage Flow . . . 772
Post Simulation Schematic Debug Flow . . . 773
Two Schematic Views . . . 773
Common Tasks for Schematic Debugging . . . 774
Adding Objects to the Incremental View . . . 774
Display a Structural Overview in the Full View. . . 775
Exploring the Connectivity of the Design . . . 776
Folding and Unfolding Instances in the Incremental View . . . 783
Exploring Designs with the Embedded Wave Viewer . . . 784
Tracing Events in the Incremental View . . . 785
Tracing the Source of an Unknown State (StX) . . . 790
Finding Objects by Name in the Schematic Window. . . 792
Schematic Concepts . . . 792
Symbol Mapping. . . 793
Schematic Window Graphic Interface Reference . . . 795
What Can I View in the Schematic Window? . . . 796
How is the Schematic Window Linked to Other Windows? . . . 796
How Can I Print and Save the Display? . . . 797
How do I Configure Window Options? . . . 798
How do I Zoom and Pan the Display? . . . 800
How do I Use Keyboard Shortcuts? . . . 802
Chapter 17 Debugging with the Dataflow Window . . . 805
Dataflow Window Overview . . . 805
Dataflow Usage Flow . . . 805
Post-Simulation Debug Flow Details . . . 806
Common Tasks for Dataflow Debugging . . . 807
Exploring the Connectivity of the Design . . . 809
Exploring Designs with the Embedded Wave Viewer . . . 812
Tracing Events . . . 813
Tracing the Source of an Unknown State (StX) . . . 814
Finding Objects by Name in the Dataflow Window. . . 816
Automatically Tracing All Paths Between Two Nets. . . 816
Dataflow Concepts. . . 818
Symbol Mapping. . . 818
Current vs. Post-Simulation Command Output . . . 820
Dataflow Window Graphic Interface Reference . . . 821
What Can I View in the Dataflow Window? . . . 821
How is the Dataflow Window Linked to Other Windows? . . . 821
How Can I Print and Save the Display? . . . 822
How Do I Configure Window Options? . . . 824
Chapter 18 Source Window . . . 825
Creating and Editing Source Files . . . 825
Creating New Files . . . 825
Opening Existing Files . . . 826
Editing Files . . . 827
Saving Files. . . 830
Searching for Code in the Source Window. . . 830
Navigating Through Your Design . . . 831
Data and Objects in the Source Window . . . 832
Determining Object Values and Descriptions. . . 833
Displaying Object Values with Source Annotation . . . 833
Source Window Debugging and Textual Connectivity . . . 835
Dragging Source Window Objects Into Other Windows . . . 837
Highlighted Text in the Source Window . . . 838
Hyperlinked Text in the Source Window . . . 839
Code Coverage Data in the Source Window . . . 839
Breakpoints . . . 841
Setting Individual Breakpoints in a Source File . . . 842
Setting Breakpoints with the bp Command . . . 842
Setting SystemC Breakpoints . . . 843
Editing Breakpoints . . . 843
Saving and Restoring Breakpoints . . . 845
Setting Conditional Breakpoints . . . 846
Bookmarks . . . 848
Setting and Removing Bookmarks . . . 848
Setting Source Window Preferences.. . . 849
Chapter 19 Using Causality Traceback . . . 851
Usage Flow for Causality Traceback. . . 851
Post-sim Debug. . . 853
Tracing to the First Sequential Process. . . 854
Tracing to the Immediate Driving Process . . . 859
Tracing to the Root Cause. . . 861
Tracing to the Root Cause of an ‘X’. . . 863
Finding All Possible Drivers. . . 863
Tracing from a Specific Time . . . 864
Handling Multiple Drivers . . . 865
Viewing Causality Path Details . . . 866
Initiating Causality Traceback from the Command Line . . . 869
Setting the Report Destination with Command Line Options . . . 870
Setting Causality Traceback Preferences. . . 871
Chapter 20 Code Coverage . . . 875
Overview of Code Coverage Types. . . 876
Language and Datatype Support. . . 876
Usage Flow for Code Coverage Collection . . . 877
Specifying Coverage Types for Collection. . . 878
Enabling Simulation for Code Coverage Collection . . . 879
Saving Code Coverage in the UCDB . . . 879
Code Coverage in the UCDB. . . 881
Code Coverage in the Graphic Interface . . . 882
Understanding Unexpected Coverage Results . . . 884
Code Coverage Types . . . 884
Statement Coverage . . . 884
Branch Coverage . . . 885
Case and Branches . . . 886
AllFalse Branches . . . 886
Missing Branches in VHDL and Clock Optimizations. . . 887
Condition and Expression Coverage . . . 887
Effect of Short-circuiting on Expression and Condition Coverage . . . 888
Reporting Condition and Expression Coverage . . . 889
FEC Coverage Detailed Examples . . . 890
UDP Coverage Details and Examples . . . 896
VHDL Condition and Expression Type Support . . . 898
Verilog/SV Condition and Expression Type Support. . . 899
Toggle Coverage . . . 899
Toggle Coverage and Performance Considerations . . . 900
VHDL Toggle Coverage Type Support . . . 900
Verilog/SV Toggle Coverage Type Support. . . 900
Toggle Ports Only Flow . . . 902
Viewing Toggle Coverage Data in the Objects Window . . . 902
Understanding Toggle Counts . . . 903
Limiting Toggle Coverage . . . 907
Finite State Machine Coverage . . . 908
Coverage Exclusions . . . 908
What Objects can be Excluded? . . . 908
Methods for Excluding Objects . . . 909
Toggle Exclusion Management . . . 917
Exclude Nodes from Toggle Coverage. . . 918
FSM Coverage Exclusions . . . 920
Saving and Recalling Exclusions . . . 922
Coverage Reports. . . 924
Using the coverage report Command . . . 925
Using the toggle report Command . . . 926
Using the Coverage Report Dialog . . . 928
Setting a Default Coverage Reporting Mode . . . 928
XML Output . . . 928
HTML Output . . . 929
Coverage Reporting on a Specific Test . . . 929
Notes on Coverage and Optimization . . . 929
Customizing Optimization Level for Coverage Runs. . . 929
Interaction of Optimization and Coverage Arguments. . . 930
Chapter 21 Finite State Machines . . . 931
FSM Recognition . . . 931
Unsupported FSM Design Styles . . . 932
FSM Design Style Examples . . . 932
FSM Coverage . . . 935
FSM Multi-State Transitions . . . 935
Collecting FSM Coverage Metrics . . . 936
Reporting Coverage Metrics for FSMs . . . 938
Viewing FSM Information in the GUI. . . 939
FSM Coverage Metrics Available in the GUI . . . 940
Advanced Command Arguments for FSMs. . . 942
Consolidated FSM Recognition Arguments . . . 942
Recognized FSM Note. . . 943
FSM Recognition Info Note. . . 943
FSM Coverage Text Report . . . 945
Chapter 22 Verification with Assertions and Cover Directives . . . 947
Overview of Assertions and Cover Directives. . . 947
Processing Assume Directives . . . 948
General Assertion Writing Guidelines . . . 948
Configuring Assertions . . . 950
Simulating Assertions . . . 960
Analyzing Assertions and Cover Directives . . . 965
Saving Metrics to the UCDB . . . 975
Excluding Assertions and Cover Directives . . . 975
Creating Assertion Reports . . . 975
PSL Assertions and Cover Directives . . . 977
Using PSL Directives in Procedural Blocks . . . 978
Common PSL Assertions Coding Tasks. . . 978
Compiling and Simulating PSL Assertions . . . 987
PSL Limitations . . . 988
Using SVA Assertions and Cover Directives . . . 989
Assertions and Action Blocks in SVA . . . 989
Deferred Assertions and Cover Directives . . . 989
SystemVerilog Cover Directives . . . 989
SVA Usage Flow for Assertions and Cover Directives . . . 990
Using -assertdebug to Debug with Assertions and Cover Directives . . . 991
Viewing Debugging Information . . . 991
Enabling ATV Recording . . . 992
Saving Assertion and Cover Directive Metrics . . . 994
Viewing Assertion Threads in the ATV Window. . . 998
Navigating Inside an ATV Window . . . 1001
Actions in the ATV Window . . . 1005
Chapter 23 Verification with Functional Coverage. . . 1011
Functional Coverage Flow. . . 1011
Configuring Covergroups, Coverpoints, and Crosses . . . 1012
Functional Coverage Computation . . . 1013
Predefined Coverage Methods . . . 1013
Predefined Coverage System Function. . . 1013
SystemVerilog Functional Coverage Terminology . . . 1013
IEEE Std 1800-2009 Option Behavior . . . 1013
Type-Based Coverage With Constructor Parameters . . . 1018
Viewing Functional Coverage Statistics in the GUI . . . 1021
Functional Coverage Statistics in the Covergroups Window . . . 1022
Functional Coverage Aggregation in Structure Window . . . 1022
Reporting on Functional Coverage . . . 1023
Creating Text Reports Via the GUI . . . 1023
Creating HTML Reports Via the GUI . . . 1025
Covergroup Bin Reporting and Timestamps . . . 1025
Filtering Functional Coverage Data . . . 1026
Reporting Via the Command Line . . . 1028
Assertion/Cover Directive Naming Conventions . . . 1029
Covergroup Naming Conventions . . . 1030
Covergroup in a Class. . . 1030
Saving Functional Coverage Data . . . 1031
Loading a Functional Coverage Database into Simulation. . . 1032
Excluding Functional Coverage . . . 1034
Merging Databases . . . 1035
Chapter 24 Verification with Constrained Random Stimulus . . . 1037
Building Constrained Random Test Benches on SystemVerilog Classes . . . 1038
Using Attributes . . . 1040
Inheriting Constraints . . . 1044
Examining Solver Failures . . . 1045
Setting Compatibility with a Previous Release. . . 1046
Seeding the Random Number Generator (RNG) . . . 1046
Using Program Blocks . . . 1047
Chapter 25 Coverage and Verification Management in the UCDB . . . 1049
Coverage and Verification Overview . . . 1050
What is the Unified Coverage Database? . . . 1051
Calculation of Total Coverage . . . 1052
Coverage and Simulator Use Modes. . . 1057
Coverage View Mode and the UCDB . . . 1057
Running Tests and Collecting Data . . . 1058
Collecting and Saving Coverage Data . . . 1058
Understanding Stored Test Data in the UCDB . . . 1060
Rerunning Tests and Executing Commands . . . 1063
Managing Test Data in UCDBs . . . 1066
Merging Coverage Test Data . . . 1067
Warnings During Merge . . . 1069
Ranking Coverage Test Data . . . 1070
Modifying UCDBs . . . 1072
About the Merge Algorithm . . . 1074
Merge Usage Scenarios. . . 1079
Viewing and Analyzing Verification Data . . . 1080
Storing User Attributes in the UCDB . . . 1081
Viewing Test Data in the GUI . . . 1081
Viewing Test Data in the Browser Window . . . 1081
Generating Coverage Reports . . . 1083
Filtering Data in the UCDB . . . 1090
Filtering Results by User Attributes . . . 1092
Retrieving Test Attribute Record Content . . . 1094
Analysis for Late-stage ECO Changes . . . 1094
Chapter 26 C Debug . . . 1095
Supported Platforms and gdb Versions . . . 1095
Running C Debug on Windows Platforms . . . 1096
Setting Up C Debug . . . 1096
Running C Debug from a DO File . . . 1097
Setting Breakpoints . . . 1097
Stepping in C Debug . . . 1099
Debugging Active or Suspended Threads. . . 1100
Known Problems With Stepping in C Debug . . . 1100
Quitting C Debug. . . 1101
Finding Function Entry Points with Auto Find bp . . . 1101
Enabling Auto Step Mode. . . 1102 Auto Find bp Versus Auto Step Mode . . . 1103 Debugging Functions During Elaboration . . . 1104 FLI Functions in Initialization Mode . . . 1105 PLI Functions in Initialization Mode . . . 1105 VPI Functions in Initialization Mode . . . 1107 Completing Design Load . . . 1107 Debugging Functions when Quitting Simulation . . . 1107 C Debug Command Reference . . . 1108
Chapter 27
Profiling Performance and Memory Use . . . 1111
Introducing Performance and Memory Profiling. . . 1111 Statistical Sampling Profiler . . . 1112 Memory Allocation Profiler . . . 1112 Getting Started with the Profiler . . . 1112 Enabling the Memory Allocation Profiler . . . 1112 Enabling the Statistical Sampling Profiler . . . 1114 Collecting Memory Allocation and Performance Data . . . 1114 Running the Profiler on Windows with PLI/VPI Code . . . 1115 Interpreting Profiler Data. . . 1115 Viewing Profiler Results . . . 1115 Ranked Window . . . 1116 Design Units Window. . . 1117 Calltree Window . . . 1117 Structural Window . . . 1119 Viewing Profile Details . . . 1120 Integration with Source Windows . . . 1121 Analyzing C Code Performance . . . 1122 Searching Profiler Results . . . 1123 Reporting Profiler Results . . . 1123 Capacity Analysis . . . 1125 Enabling or Disabling Capacity Analysis . . . 1126 Levels of Capacity Analysis . . . 1128 Obtaining a Graphical Interface (GUI) Display . . . 1129 Writing a Text-Based Report . . . 1130
Chapter 28
Signal Spy . . . 1135
Signal Spy Formatting Syntax . . . 1136 Signal Spy Supported Types . . . 1136 disable_signal_spy . . . 1137 enable_signal_spy . . . 1139 init_signal_driver . . . 1141 init_signal_spy . . . 1145 signal_force. . . 1149 signal_release . . . 1153
Chapter 29
Monitoring Simulations with JobSpy . . . 1155
Basic JobSpy Flow. . . 1155 Starting the JobSpy Daemon. . . 1156 Running JobSpy from the Command Line . . . 1157 Simulation Commands Available to JobSpy . . . 1157 Example Session . . . 1158 Running the JobSpy GUI . . . 1159 Starting Job Manager . . . 1159 Invoking Simulation Commands in Job Manager . . . 1159 View Commands and Pathnames . . . 1160 Viewing Results During Active Simulation . . . 1161 Viewing Waveforms from the Command Line . . . 1161 Licensing and Job Suspension . . . 1162 Checkpointing Jobs . . . 1162 Connecting to Load-Sharing Software. . . 1163 Checkpointing with Load-Sharing Software . . . 1163
Chapter 30
Generating Stimulus with Waveform Editor . . . 1165
Getting Started with the Waveform Editor . . . 1165 Using Waveform Editor Prior to Loading a Design . . . 1165 Using Waveform Editor After Loading a Design . . . 1166 Creating Waveforms from Patterns . . . 1167 Creating Waveforms with Wave Create Command. . . 1168 Editing Waveforms . . . 1169 Selecting Parts of the Waveform . . . 1170 Stretching and Moving Edges. . . 1172 Simulating Directly from Waveform Editor . . . 1172 Exporting Waveforms to a Stimulus File. . . 1172 Driving Simulation with the Saved Stimulus File . . . 1173 Signal Mapping and Importing EVCD Files . . . 1174 Using Waveform Compare with Created Waveforms . . . 1174 Saving the Waveform Editor Commands . . . 1175
Chapter 31
Standard Delay Format (SDF) Timing Annotation. . . 1177
Specifying SDF Files for Simulation. . . 1177 Instance Specification . . . 1178 SDF Specification with the GUI . . . 1178 Errors and Warnings . . . 1179 Compiling SDF Files . . . 1179 Simulating with Compiled SDF Files . . . 1179 Using $sdf_annotate() with Compiled SDF . . . 1180 VHDL VITAL SDF . . . 1180 SDF to VHDL Generic Matching . . . 1180 Resolving Errors . . . 1181 Verilog SDF . . . 1181
$sdf_annotate . . . 1183 SDF to Verilog Construct Matching . . . 1184 Retain Delay Behavior . . . 1187 Optional Edge Specifications . . . 1189 Optional Conditions . . . 1190 Rounded Timing Values . . . 1190 SDF for Mixed VHDL and Verilog Designs . . . 1191 Interconnect Delays . . . 1191 Disabling Timing Checks . . . 1191 Troubleshooting . . . 1192 Specifying the Wrong Instance. . . 1192 Matching a Single Timing Check . . . 1193 Mistaking a Component or Module Name for an Instance Label. . . 1193 Forgetting to Specify the Instance . . . 1194
Chapter 32
Value Change Dump (VCD) Files . . . 1195
Creating a VCD File . . . 1195 Four-State VCD File . . . 1195 Extended VCD File. . . 1196 VCD Case Sensitivity . . . 1196 Checkpoint/Restore and Writing VCD Files . . . 1196 Using Extended VCD as Stimulus. . . 1197 Simulating with Input Values from a VCD File . . . 1197 Replacing Instances with Output Values from a VCD File . . . 1198 VCD Commands and VCD Tasks . . . 1200 Using VCD Commands with SystemC. . . 1201 Compressing Files with VCD Tasks. . . 1202 VCD File from Source to Output. . . 1202 VHDL Source Code . . . 1202 VCD Simulator Commands . . . 1203 VCD Output . . . 1204 VCD to WLF . . . 1205 Capturing Port Driver Data . . . 1205 Driver States . . . 1205 Driver Strength . . . 1206 Identifier Code . . . 1206 Resolving Values . . . 1207
Chapter 33
Tcl and Macros (DO Files) . . . 1211
Tcl Features . . . 1211 Tcl References . . . 1211 Tcl Commands . . . 1212 Tcl Command Syntax . . . 1212 If Command Syntax . . . 1215 set Command Syntax . . . 1215 Command Substitution . . . 1216
Command Separator . . . 1217 Multiple-Line Commands. . . 1217 Evaluation Order. . . 1217 Tcl Relational Expression Evaluation. . . 1217 Variable Substitution . . . 1218 System Commands . . . 1218 Simulator State Variables . . . 1219 Referencing Simulator State Variables. . . 1220 Special Considerations for the now Variable . . . 1220 List Processing . . . 1221 Reading Variable Values From the INI File . . . 1221 Simulator Tcl Commands . . . 1222 Simulator Tcl Time Commands. . . 1222 Conversions. . . 1223 Relations . . . 1223 Arithmetic . . . 1224 Tcl Examples . . . 1224 Macros (DO Files) . . . 1226 Creating DO Files . . . 1226 Using Parameters with DO Files. . . 1227 Deleting a File from a .do Script. . . 1227 Making Macro Parameters Optional. . . 1228 Useful Commands for Handling Breakpoints and Errors . . . 1229 Error Action in DO Files. . . 1230 The Tcl Debugger . . . 1231 Starting the Debugger . . . 1231 How the debugger Works . . . 1231 The Chooser . . . 1231 The Debugger . . . 1232 Breakpoints . . . 1234 Configuration . . . 1235 TclPro Debugger . . . 1235 Appendix A modelsim.ini Variables . . . 1237
Organization of the modelsim.ini File . . . 1237 Making Changes to the modelsim.ini File . . . 1238 Changing the modelsim.ini Read-Only Attribute . . . 1238 The Runtime Options Dialog . . . 1238 Editing modelsim.ini Variables . . . 1242 Overriding the Default Initialization File . . . 1242 Variables . . . 1243 AcceptLowerCasePragmaOnly. . . 1244 AmsStandard. . . 1244 AssertFile . . . 1244 AssertionActiveThreadMonitor . . . 1245 AssertionActiveThreadMonitorLimit . . . 1245 AssertionCover . . . 1245
AssertionDebug. . . 1246 AssertionEnable . . . 1246 AssertionEnableVacuousPassActionBlock. . . 1246 AssertionFailAction . . . 1247 AssertionFailLocalVarLog . . . 1247 AssertionFailLog. . . 1247 AssertionLimit . . . 1248 AssertionPassLog . . . 1248 AssertionThreadLimit . . . 1248 AssertionThreadLimitAction . . . 1248 ATVStartTimeKeepCount . . . 1249 AutoExclusionsDisable. . . 1249 BindAtCompile . . . 1250 BreakOnAssertion. . . 1250 CheckPlusargs. . . 1251 CheckpointCompressMode. . . 1251 CheckSynthesis . . . 1252 CodeCoverage. . . 1252 CodeLinkAutoLoad . . . 1252 CommandHistory . . . 1253 CompilerTempDir. . . 1253 ConcurrentFileLimit . . . 1253 Coverage . . . 1253 CoverAtLeast . . . 1254 CoverCells. . . 1254 CoverClkOptBuiltins . . . 1254 CoverCountAll . . . 1255 CoverEnable . . . 1255 CoverExcludeDefault . . . 1255 CoverFEC . . . 1256 CoverLimit . . . 1256 CoverLog . . . 1256 CoverMaxFECRows . . . 1257 CoverMaxUDPRows . . . 1257 CoverOpt. . . 1257 CoverRespectHandL . . . 1258 CoverReportCancelled . . . 1258 CoverShortCircuit . . . 1259 CoverSub. . . 1259 CoverThreadLimit. . . 1259 CoverThreadLimitAction . . . 1260 CoverUDP. . . 1260 CoverWeight . . . 1260 CppOptions . . . 1261 CppPath. . . 1261 DatasetSeparator . . . 1261 DefaultForceKind . . . 1262 DefaultRadix . . . 1262 DefaultRestartOptions. . . 1263
DelayFileOpen . . . 1263 displaymsgmode . . . 1264 DpiCppPath. . . 1264 DpiOutOfTheBlue. . . 1265 DumpportsCollapse. . . 1265 EmbeddedPsl. . . 1265 EnableSVCoverpointExprVariable. . . 1266 EnableTypeOf . . . 1266 EnumBaseInit . . . 1266 error. . . 1267 ErrorFile . . . 1267 Explicit . . . 1268 ExtendedToggleMode. . . 1268 fatal . . . 1268 floatfixlib. . . 1269 ForceSigNextIter. . . 1269 ForceUnsignedIntegerToVHDLInteger . . . 1269 FsmImplicitTrans . . . 1270 FsmResetTrans . . . 1270 FsmSingle . . . 1270 FsmXAssign . . . 1271 GenerateFormat. . . 1271 GenerateLoopIterationMax. . . 1272 GenerateRecursionDepthMax. . . 1272 GenerousIdentifierParsing . . . 1272 GlobalSharedObjectsList . . . 1273 Hazard . . . 1273 ieee . . . 1273 IgnoreError . . . 1273 IgnoreFailure. . . 1274 IgnoreNote . . . 1274 ignoreStandardRealVector . . . 1275 IgnoreSVAError . . . 1275 IgnoreSVAFatal . . . 1275 IgnoreSVAInfo . . . 1276 IgnoreSVAWarning . . . 1276 IgnoreVitalErrors . . . 1276 IgnoreWarning . . . 1277 ImmediateContinuousAssign . . . 1277 InitOutCompositeParam . . . 1277 IncludeRecursionDepthMax . . . 1278 IterationLimit . . . 1278 LibrarySearchPath. . . 1278 License . . . 1279 MaxReportRhsCrossProducts . . . 1280 MaxReportRhsSVCrossProducts . . . 1280 MaxSVCoverpointBinsDesign . . . 1280 MaxSVCoverpointBinsInst. . . 1280 MaxSVCrossBinsDesign . . . 1281
MaxSVCrossBinsInst . . . 1281 MessageFormat . . . 1281 MessageFormatBreak . . . 1282 MessageFormatBreakLine . . . 1282 MessageFormatError. . . 1283 MessageFormatFail. . . 1283 MessageFormatFatal . . . 1283 MessageFormatNote . . . 1284 MessageFormatWarning . . . 1284 MixedAnsiPorts . . . 1284 modelsim_lib . . . 1285 msgmode . . . 1285 mtiAvm . . . 1285 mtiOvm . . . 1285 mtiPA . . . 1286 mtiUPF . . . 1286 mtiUvm . . . 1286 MultiFileCompilationUnit . . . 1287 MvcHome . . . 1287 NoCaseStaticError . . . 1287 NoDebug . . . 1288 NoDeferSubpgmCheck . . . 1288 NoIndexCheck . . . 1288 NoOthersStaticError . . . 1289 NoRangeCheck . . . 1289 note . . . 1289 NoVital . . . 1290 NoVitalCheck . . . 1290 NumericStdNoWarnings. . . 1290 OldVHDLConfigurationVisibility . . . 1291 OldVhdlForGenNames . . . 1291 OnFinish . . . 1292 OnFinishPendingAssert . . . 1292 Optimize_1164 . . . 1292 PathSeparator . . . 1293 PedanticErrors. . . 1293 PliCompatDefault . . . 1294 PreserveCase . . . 1295 PrintSimStats . . . 1295 PrintSVPackageLoadingAttribute. . . 1296 Protect . . . 1296 PslOneAttempt . . . 1296 PslInfinityThreshold . . . 1297 Quiet . . . 1297 RequireConfigForAllDefaultBinding . . . 1297 Resolution . . . 1298 RunLength. . . 1298 ScalarOpts . . . 1299 SccomLogfile . . . 1299
SccomVerbose . . . 1299 ScEnableScSignalWriteCheck . . . 1300 ScMainFinishOnQuit . . . 1300 ScMainStackSize . . . 1300 ScShowIeeeDeprecationWarnings . . . 1301 ScTimeUnit . . . 1301 ScvPhaseRelationName . . . 1301 SeparateConfigLibrary . . . 1301 Show_BadOptionWarning . . . 1302 Show_Lint. . . 1302 Show_PslChecksWarnings . . . 1302 Show_source . . . 1303 Show_VitalChecksWarnings . . . 1303 Show_Warning1 . . . 1303 Show_Warning2 . . . 1303 Show_Warning3 . . . 1304 Show_Warning4 . . . 1304 Show_Warning5 . . . 1304 ShowConstantImmediateAsserts . . . 1304 ShowFunctions . . . 1305 ShowUnassociatedScNameWarning. . . 1305 ShowUndebuggableScTypeWarning . . . 1305 ShutdownFile . . . 1306 SignalSpyPathSeparator . . . 1306 SimulateAssumeDirectives . . . 1306 SimulatePSL . . . 1307 SimulateSVA . . . 1307 SolveACTbeforeSpeculate . . . 1307 SolveACTMaxOps . . . 1308 SolveACTMaxTests . . . 1308 SolveACTRetryCount. . . 1308 SolveArrayResizeMax . . . 1309 SolveEngine . . . 1309 SolveFailDebug. . . 1309 SolveFailDebugMaxSet . . . 1310 SolveFailSeverity . . . 1310 SolveFlags. . . 1310 SolveGraphMaxEval. . . 1311 SolveGraphMaxSize . . . 1311 SolveIgnoreOverflow . . . 1311 SolveRev . . . 1312 SolveSpeculateDistFirst . . . 1312 SolveSpeculateFirst. . . 1313 SolveSpeculateLevel. . . 1313 SolveSpeculateMaxCondWidth . . . 1314 SolveSpeculateMaxIterations . . . 1314 SparseMemThreshold . . . 1314 Startup . . . 1315 std . . . 1315
std_developerskit . . . 1315 StdArithNoWarnings . . . 1316 suppress. . . 1316 Sv_Seed. . . 1316 sv_std . . . 1317 SVAPrintOnlyUserMessage . . . 1317 SVCovergroupGetInstCoverageDefault . . . 1317 SVCovergroupGoal. . . 1318 SVCovergroupGoalDefault. . . 1318 SVCovergroupMergeInstancesDefault . . . 1319 SVCovergroupPerInstanceDefault . . . 1320 SVCovergroupSampleInfo . . . 1320 SVCovergroupStrobe . . . 1321 SVCovergroupStrobeDefault . . . 1321 SVCovergroupTypeGoal . . . 1321 SVCovergroupTypeGoalDefault . . . 1322 SVCoverpointAutoBinMax . . . 1322 SVCoverpointExprVariablePrefix . . . 1323 SVCoverpointWildCardBinValueSizeWarn. . . 1323 SVCrossNumPrintMissing . . . 1323 SVCrossNumPrintMissingDefault . . . 1324 SVFileExtensions . . . 1324 Svlog . . . 1325 synopsys . . . 1325 SyncCompilerFiles . . . 1325 SynthPrefix . . . 1325 ToggleCountLimit . . . 1326 ToggleFixedSizeArray . . . 1326 ToggleMaxFixedSizeArray. . . 1327 ToggleMaxIntValues . . . 1327 ToggleMaxRealValues . . . 1328 ToggleNoIntegers . . . 1328 TogglePackedAsVec. . . 1328 TogglePortsOnly . . . 1329 ToggleVlogEnumBits . . . 1329 ToggleVlogIntegers . . . 1329 ToggleVlogReal . . . 1330 ToggleWidthLimit . . . 1330 TranscriptFile . . . 1330 UCDBFilename. . . 1331 UCDBTestStatusMessageFilter . . . 1331 UnattemptedImmediateAssertions . . . 1331 UnbufferedOutput . . . 1332 UpCase . . . 1332 UserTimeUnit . . . 1332 UseScv . . . 1333 UseSVCrossNumPrintMissing . . . 1333 verilog . . . 1333 Veriuser. . . 1334
VHDL93 . . . 1334 VhdlVariableLogging . . . 1334 vital2000 . . . 1335 vlog95compat . . . 1335 VoptFlow . . . 1336 WarnConstantChange . . . 1336 warning . . . 1336 WaveSignalNameWidth . . . 1337 WLFCacheSize . . . 1337 WLFCollapseMode. . . 1337 WLFCompress . . . 1338 WLFDeleteOnQuit . . . 1338 WLFFileLock . . . 1339 WLFFilename . . . 1339 WLFOptimize . . . 1339 WLFSaveAllRegions . . . 1340 WLFSimCacheSize. . . 1340 WLFSizeLimit . . . 1341 WLFTimeLimit. . . 1341 WLFUseThreads . . . 1342 Commonly Used modelsim.ini Variables . . . 1342 Common Environment Variables . . . 1342 Hierarchical Library Mapping . . . 1343 Creating a Transcript File . . . 1343 Using a Startup File . . . 1344 Turning Off Assertion Messages . . . 1344 Turning off Warnings from Arithmetic Packages . . . 1344 Force Command Defaults . . . 1345 Restart Command Defaults . . . 1345 VHDL Standard . . . 1345 Opening VHDL Files . . . 1346
Appendix B
Location Mapping. . . 1347
Referencing Source Files with Location Maps . . . 1347 Using Location Mapping . . . 1347 Pathname Syntax. . . 1348 How Location Mapping Works . . . 1348 Mapping with TCL Variables . . . 1348
Appendix C
Error and Warning Messages . . . 1349
Message System. . . 1349 Message Format . . . 1349 Getting More Information. . . 1350 Changing Message Severity Level . . . 1350 Suppressing Warning Messages . . . 1350 Suppressing VCOM Warning Messages . . . 1350
Suppressing VLOG Warning Messages . . . 1351 Suppressing VOPT Warning Messages . . . 1351 Suppressing VSIM Warning Messages . . . 1352 Exit Codes . . . 1352 Miscellaneous Messages . . . 1354 sccom Error Messages . . . 1358 Enforcing Strict 1076 Compliance. . . 1359
Appendix D
Verilog Interfaces to C . . . 1363
Implementation Information . . . 1363 GCC Compiler Support for use with C Interfaces . . . 1365 Registering PLI Applications. . . 1365 Registering VPI Applications . . . 1367 Registering DPI Applications . . . 1368 DPI Use Flow. . . 1369 DPI and the vlog Command . . . 1370 When Your DPI Export Function is Not Getting Called . . . 1371 Troubleshooting a Missing DPI Import Function. . . 1371 Simplified Import of Library Functions . . . 1372 Optimizing DPI Import Call Performance . . . 1373 DPI Arguments of Parameterized Datatypes . . . 1373 Making Verilog Function Calls from non-DPI C Models . . . 1374 Calling C/C++ Functions Defined in PLI Shared Objects from DPI Code . . . 1374 Compiling and Linking C Applications for Interfaces . . . 1375 For all UNIX Platforms . . . 1375 Windows Platforms — C . . . 1376 32-bit Linux Platform — C. . . 1377 64-bit Linux Platform — C. . . 1377 Compiling and Linking C++ Applications for Interfaces . . . 1378 Windows Platforms — C++ . . . 1379 32-bit Linux Platform — C++ . . . 1380 64-bit Linux Platform — C++ . . . 1380 Specifying Application Files to Load . . . 1380 PLI and VPI File Loading. . . 1380 DPI File Loading. . . 1381 Loading Shared Objects with Global Symbol Visibility . . . 1382 PLI Example . . . 1382 VPI Example . . . 1382 DPI Example . . . 1383 The PLI Callback reason Argument . . . 1384 The sizetf Callback Function . . . 1386 PLI Object Handles . . . 1386 Third Party PLI Applications. . . 1386 Support for VHDL Objects . . . 1387 IEEE Std 1364 ACC Routines . . . 1389 IEEE Std 1364 TF Routines. . . 1391 SystemVerilog DPI Access Routines. . . 1391
Verilog-XL Compatible Routines . . . 1392 64-bit Support for PLI . . . 1392 Using 64-bit Questa SIM with 32-bit Applications . . . 1392 PLI/VPI Tracing. . . 1392 The Purpose of Tracing Files . . . 1393 Invoking a Trace . . . 1393 Checkpointing and Interface Code. . . 1394 Checkpointing Code that Works with Heap Memory. . . 1394 Debugging Interface Application Code . . . 1394
Appendix E
Command and Keyboard Shortcuts . . . 1397
Command Shortcuts. . . 1397 Command History Shortcuts. . . 1397 Main and Source Window Mouse and Keyboard Shortcuts . . . 1398 List Window Keyboard Shortcuts . . . 1401 Wave Window Mouse and Keyboard Shortcuts . . . 1402
Appendix F
Setting GUI Preferences . . . 1405
Customizing the Simulator GUI Layout . . . 1405 Layout Mode Loading Priority . . . 1406 Configure Window Layouts Dialog Box . . . 1406 Creating a Custom Layout Mode . . . 1406 Changing Layout Mode Behavior. . . 1407 Resetting a Layout Mode to its Default . . . 1407 Deleting a Custom Layout Mode . . . 1407 Configuring Default Windows for Restored Layouts. . . 1407 Configuring the Column Layout. . . 1408 Simulator GUI Preferences . . . 1409 Setting Preference Variables from the GUI . . . 1410 Setting Preference Variables from the Command Line . . . 1412 Saving GUI Preferences . . . 1412 The modelsim.tcl File . . . 1413
Appendix G
System Initialization . . . 1415
Files Accessed During Startup. . . 1415 Initialization Sequence. . . 1415 Environment Variables . . . 1418 Environment Variable Expansion . . . 1418 Setting Environment Variables . . . 1418 Creating Environment Variables in Windows . . . 1424 Referencing Environment Variables. . . 1425 Removing Temp Files (VSOUT) . . . 1425
Third-Party Model Support. . . 1427
Synopsys SmartModels . . . 1427 VHDL SmartModel Interface . . . 1427 Verilog SmartModel Interface . . . 1434 Synopsys Hardware Models . . . 1434 VHDL Hardware Model Interface . . . 1434 Creating Foreign Architectures with hm_entity . . . 1435
Index
Third-Party Information End-User License Agreement
List of Examples
Example 2-1. Using the radix define Command . . . 82 Example 2-2. Using radix define to Specify Color . . . 83 Example 2-3. Covergroups Window . . . 158 Example 3-1. Encryption Envelope Contains Verilog IP Code to be Protected . . . 283 Example 3-2. Encryption Envelope Contains `include Compiler Directives . . . 284 Example 3-3. Results After Compiling with vlog +protect . . . 289 Example 3-4. Using the Mentor Graphics Public Encryption Key in Verilog/SystemVerilog 310 Example 7-1. Memory Model Using VHDL87 and VHDL93 Architectures . . . 392 Example 7-2. Conversions Package. . . 394 Example 7-3. Memory Model Using VHDL02 Architecture . . . 396 Example 8-1. Invocation of the Verilog Compiler . . . 404 Example 8-2. Incremental Compilation Example . . . 408 Example 8-3. Sub-Modules with Common Names . . . 411 Example 9-1. Simple SystemC-only sc_main(). . . 470 Example 9-2. Generating SCV Extensions for a Structure . . . 484 Example 9-3. Generating SCV Extensions for a Class without Friend
(Private Data Not Generated). . . 484 Example 9-4. Generating SCV Extensions for a Class with Friend
(Private Data Generated) . . . 484 Example 9-5. Generating SCV Extensions for an Enumerated Type . . . 485 Example 9-6. User-Defined Constraint . . . 486 Example 9-7. Use of mti_set_typename . . . 502 Example 9-8. Using the Custom Interface on Different Objects . . . 505 Example 9-9. Converting sc_main to a Module . . . 509 Example 9-10. Using sc_main and Signal Assignments . . . 510 Example 9-11. Using an SCV Transaction Database . . . 511 Example 10-1. Binding with -cuname and -mfcu Arguments . . . 534 Example 10-2. SystemC Instantiating Verilog - 1 . . . 579 Example 10-3. SystemC Instantiating Verilog - 2 . . . 580 Example 10-4. Sample Foreign Module Declaration, with Constructor Arguments for Parameters 581
Example 10-5. Passing Parameters as Constructor Arguments - 1 . . . 581 Example 10-6. SystemC Instantiating Verilog, Passing Integer Parameters as Template
Arguments . . . 583 Example 10-7. Passing Integer Parameters as Template Arguments and Non-integer Parameters as Constructor Arguments . . . 584 Example 10-8. Verilog/SystemVerilog Instantiating SystemC, Parameter Information. . . . 586 Example 10-9. SystemC Design Instantiating a VHDL Design Unit . . . 590 Example 10-10. SystemC Instantiating VHDL, Generic Information. . . 591 Example 10-11. Passing Parameters as Constructor Arguments - 2 . . . 591
Example 10-12. SystemC Instantiating VHDL, Passing Integer Generics as Template Arguments 592
Example 10-13. Passing Integer Generics as Template Arguments and Non-integer Generics as Constructor Arguments . . . 593 Example 10-14. Global Import Function Registration . . . 598 Example 10-15. SystemVerilog Global Import Declaration . . . 599 Example 10-16. Registering a Global Function. . . 599 Example 10-17. Usage of scSetScopeByName and scGetScopeName . . . 601 Example 12-1. Transactions in List Window . . . 630 Example 12-2. Verilog API Code Example. . . 645 Example 12-3. SCV Initialization and WLF Database Creation . . . 646 Example 12-4. SCV API Code Example . . . 651 Example 20-1. Branch Coverage . . . 885 Example 20-2. Coverage Report for Branch . . . 885 Example 20-3. FEC Coverage - Simple Expression . . . 890 Example 20-4. FEC Coverage - Bimodal Expression . . . 893 Example 20-5. UDP Condition Truth Table . . . 896 Example 20-6. Vectors in UDP Condition Truth Table . . . 897 Example 20-7. Expression UDP Truth Table . . . 898 Example 20-8. Creating Coverage Exclusions with a .do File . . . 911 Example 20-9. Excluding, Merging and Reporting on Several Runs . . . 923 Example 20-10. Reporting Coverage Data from the Command Line . . . 925 Example 21-1. Verilog Single-State Variable FSM . . . 932 Example 21-2. VHDL Single-State Variable FSM . . . 933 Example 21-3. Verilog Current-State Variable with a Single Next-State Variable FSM . . . 934 Example 21-4. VHDL Current-State Variable and Single Next-State Variable FSM. . . 934 Example 22-1. Embedding Assertions in Your Code . . . 980 Example 22-2. Writing Assertions in an External File . . . 982 Example 22-3. Using PSL ended() in Verilog . . . 985 Example 22-4. Using ended() in VHDL . . . 986 Example 22-5. Enable and Disable Assertion During Simulation. . . 994 Example 23-1. With option.per_instance=1 or vsim -cvgperinstance. . . 1015 Example 23-2. Different Results with get_inst_coverage and get_coverage . . . 1017 Example 23-3. Type-based Coverage . . . 1019 Example 23-4. Bin Unions. . . 1020 Example 23-5. Sample Output From vcover report Command . . . 1029 Example 23-6. Functional Coverage in Code . . . 1034 Example 24-1. The rand Variable . . . 1039 Example 24-2. Generating New Random Values With randomize() . . . 1039 Example 24-3. Using the solveflags attribute. . . 1042 Example 25-1. Dividing a UCDB by Module/DU. . . 1073 Example 25-2. Coverage Threshold Difference . . . 1077 Example 25-3. Coverage Object Differences with Parameters . . . 1077 Example 32-1. Verilog Counter. . . 1197 Example 32-2. VHDL Adder. . . 1197
Example 32-3. Mixed-HDL Design. . . 1198 Example 32-4. Replacing Instances. . . 1199 Example 32-5. VCD Output from vcd dumpports. . . 1210 Example 33-1. Tcl while Loop . . . 1224 Example 33-2. Tcl for Command . . . 1224 Example 33-3. Tcl foreach Command . . . 1224 Example 33-4. Tcl break Command . . . 1225 Example 33-5. Tcl continue Command . . . 1225 Example 33-6. Access and Transfer System Information . . . 1225 Example 33-7. Tcl Used to Specify Compiler Arguments . . . 1226 Example 33-8. Tcl Used to Specify Compiler Arguments—Enhanced . . . 1226 Example 33-9. Specifying Files to Compile With argc Macro . . . 1228 Example 33-10. Specifying Compiler Arguments With Macro . . . 1228 Example 33-11. Specifying Compiler Arguments With Macro—Enhanced. . . 1228 Example D-1. VPI Application Registration . . . 1367
List of Figures
Figure 1-1. Operational Structure and Flow of Questa SIM . . . 58 Figure 2-1. Graphical User Interface . . . 73 Figure 2-2. Find Mode . . . 78 Figure 2-3. Filter Mode . . . . 78 Figure 2-4. Find Options Popup Menu . . . 81 Figure 2-5. User-Defined Radix “States” in the Wave Window . . . 83 Figure 2-6. User-Defined Radix “States” in the List Window . . . 83 Figure 2-7. Setting the Global Signal Radix . . . 85 Figure 2-8. Fixed Point Radix Dialog . . . 85 Figure 2-9. Active Cursor Time. . . 86 Figure 2-10. Enter Active Time Value . . . 87 Figure 2-11. Main Window of the GUI . . . 88 Figure 2-12. Main Window — Menu Bar . . . 89 Figure 2-13. Main Window — Toolbar Frame . . . 89 Figure 2-14. Main Window — Toolbar. . . 90 Figure 2-15. GUI Windows . . . 91 Figure 2-16. GUI Tab Group . . . 92 Figure 2-17. Wave Window Panes . . . 93 Figure 2-18. Main Window Status Bar . . . 93 Figure 2-19. Window Header Handle . . . 95 Figure 2-20. Tab Handle . . . 95 Figure 2-21. Window Undock Button . . . 95 Figure 2-22. ATV Toolbar. . . 106 Figure 2-23. Analysis Toolbar . . . 107 Figure 2-24. Column Layout Toolbar . . . 108 Figure 2-25. Compile Toolbar . . . 109 Figure 2-26. Coverage Toolbar . . . 110 Figure 2-27. FSM Toolbar . . . 111 Figure 2-28. Help Toolbar . . . 112 Figure 2-29. Layout Toolbar . . . 112 Figure 2-30. Memory Toolbar . . . 112 Figure 2-31. Mode Toolbar . . . 113 Figure 2-32. Objectfilter Toolbar. . . 114 Figure 2-33. Precision Toolbar . . . 114 Figure 2-34. Process Toolbar. . . 115 Figure 2-35. Profile Toolbar . . . 115 Figure 2-36. Schematic Toolbar . . . 116 Figure 2-37. Simulate Toolbar. . . 118 Figure 2-38. Show Cause Dropdown Menu . . . 120 Figure 2-39. Source Toolbar . . . 121
Figure 2-40. Standard Toolbar. . . 121 Figure 2-41. Add Selected to Window Dropdown Menu . . . 123 Figure 2-42. Wave Toolbar . . . 124 Figure 2-43. Wave Bookmark Toolbar . . . 124 Figure 2-44. Wave Compare Toolbar . . . 125 Figure 2-45. Wave Cursor Toolbar . . . 126 Figure 2-46. Wave Edit Toolbar . . . 126 Figure 2-47. Wave Expand Time Toolbar . . . 127 Figure 2-48. Zoom Toolbar . . . 128 Figure 2-49. Assertions Window . . . 129 Figure 2-50. ATV Window . . . 135 Figure 2-51. Call Stack Window . . . 138 Figure 2-52. Capacity Window . . . 140 Figure 2-53. Class Graph Window . . . 142 Figure 2-54. Class Tree Window . . . 144 Figure 2-55. Code Coverage Analysis . . . 147 Figure 2-56. Missed Coverage in Code Coverage Analysis Windows . . . 149 Figure 2-57. Coverage Details Window Showing Expression Truth Table . . . 152 Figure 2-58. Coverage Details Window Showing Toggle Details . . . 153 Figure 2-59. Coverage Details Window Showing FSM Details . . . 154 Figure 2-60. Cover Directives Window. . . 155 Figure 2-61. Dataflow Window . . . 161 Figure 2-62. Dataflow Window and Panes . . . 164 Figure 2-63. Files Window . . . 165 Figure 2-64. FSM List Window. . . 168 Figure 2-65. FSM Viewer Window . . . 170 Figure 2-66. Combining Common Transition Conditions. . . 173 Figure 2-67. Instance Coverage Window . . . 177 Figure 2-68. Filter Instance List Dialog Box . . . 178 Figure 2-69. Library Window . . . 179 Figure 2-70. List Window . . . 182 Figure 2-71. Locals Window . . . 186 Figure 2-72. Change Selected Variable Dialog Box . . . 188 Figure 2-73. Memory LIst Window. . . 190 Figure 2-74. Memory Data Window . . . 193 Figure 2-75. Split Screen View of Memory Contents . . . 194 Figure 2-76. Message Viewer Window . . . 197 Figure 2-77. Message Viewer Window — Tasks . . . 197 Figure 2-78. Message Viewer Filter Dialog Box. . . 202 Figure 2-79. Objects Window . . . 203 Figure 2-80. Setting the Global Signal Radix from the Objects Window . . . 204 Figure 2-81. Objects Window - Toggle Coverage. . . 206 Figure 2-82. Processes Window . . . 208 Figure 2-83. Column Heading Changes When States are Filtered . . . 209 Figure 2-84. Next Active Process Displayed in Order Column. . . 210
