EE241B : Advanced Digital Circuits

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inst.eecs.berkeley.edu/~ee241b

Borivoje Nikolić

EE241B : Advanced Digital Circuits

Lecture 8 – Standard Cells

EECS241B L08 STANDARD CELLS 1

‘I’m Not a Cat,’ Says Lawyer

Having Zoom Difficulties

The video was immediately shared

widely and brought joy to many.

The lawyer, Rod Ponton, said he

was happy people got a much‐

needed laugh

NY Times, Feb 9, 2021.

Announcements

• Assignment 1+Lab 2 due next week

• No lecture next Tuesday

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2/11/2021

2 Outline

• Standard cell libraries

• Gate delays

3 EECS241B L08 STANDARD CELLS

2.J Standard Cells

3

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Standard Cell Inverter

• Schematic and layout

(in a planar bulk process)

Polysilicon

In

Out

VDD

GND

PMOS

_2

Metal 1

NMOS

Out

In

V

_DD

PMOS

NMOS

Contacts

N Well

EECS241B L08 STANDARD CELLS 5

• Pitches are integer multiples of 

Two Inverters

Connect in Metal

Share power and ground

Abut cells

V

_DD

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2/11/2021

4 FinFET Standard Cells

V. Vashishtha, ICCAD’17

ASAP7

ASAP7 Standard Cells

EECS241B L08 STANDARD CELLS ₈

7

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ASAP7 Standard Cells

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6 ASAP7 Standard Cells

ASAP7 Standard Cells

EECS241B L08 STANDARD CELLS ₁₂

11

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ASAP7 Standard Cells

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8 ASAP7 Standard Cells

ASAP7 Standard Cells

EECS241B L08 STANDARD CELLS ₁₆

15

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ASAP7 Standard Cells

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10 ASAP7 Standard Cells

ASAP7 Latch

EECS241B L08 STANDARD CELLS ₂₀

19

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2.K Design Kit

Design Kit Components

• Physical views

• Layout and schematic, with abstractions

• Netlist

• Logical view

• Test view

• Timing, power and noise views

• Documentation

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2/11/2021

12 EE241B Technology

• ASAP7 7nm predictive technology kit

• Also available Synopsys 32/28nm Generic Library

• Multi-vth Standard Cell Library 45 IO pads

• SRAMs

• Design rule manual

2.L Delay Revisited

23

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How to Account for Input Slope?

• t

_pHL

= 0.7 R

_eq

C

_L

0 V

_DD

V

DD

0

Out In VDD CL Out In VDD CL

V

DD

0 V

_DD

0

• t

_pHL

= 0.7 R

_eq

C

_L

different R

eq

!

t

_p

= ln2 RC = 0.7 R

_eq

C

_L

T

_r,10-90

= 2.2 R

_eq

C

_L

T

_r,20-80

= 1.4 R

_eq

C

_L

Input Slope Dependence

• One way to analyze slope effect

out

L

NMOS

PMOS

dV

I

C

I

dt





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2/11/2021

14 Slope Analysis

• For falling edge at output:

• For reasonable inputs, can ignore I

_PMOS

• Either V

DS

is very small, or V

GS

is very small

• So, output current ramp starts when V

_in

=V

_ThZ

• Could evaluate the integral

• Learn more by using an intuitive, graphical approach

Slope Dependence

• I

_out

ramps linearly for

V

_ThZ

<V

_in

<V

_DD

• Constant once V

_in

=V

_DD

• C

_L

integrates I

_out

• V

ThZ

<V

in

<V

DD

: V

out

quadratic

• V

in

= V

DD

: V

out

linear

0 V

ThZ

V

DD

/2

V

DD

V

in

0 I

DSAT

I

out

V

DD

/2

V

DD

V

out

I

DSAT

/2

t

p,ramp

EECS241B L08 STANDARD CELLS ₂₈

27

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Slope Dependence

• Compare to step input whose

output crosses V

_DD

/2 at same

time

• V

_out

set by charge removed

from C

_L

• Need to make

Q

_R

= Q

_S

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2/11/2021

16 Slope Dependence

0 V

ThZ

V

DD

/2

V

DD

V

in

0 I

DSAT

I

out

V

DD

/2

V

DD

V

out

I

DSAT

/2

tp,step

V

half

= (V

DD

+V

ThZ

)/2

t

p,ramp

t

slope

• To find Δt

slope

:

• Find V

in

= V

half

when I

out

= I

DSAT

/2

• And use input t

_r

• I

_DSAT

α (V

DD

-V

ThZ

):

V

_half

= (V

_DD

+V

_ThZ

)/2

• So Δt

_slope

= (V

_ThZ

/2)/k

_r

• k

_r

= V

_DD

/(t

_r,20-80

) = V

_DD

/(2*t

_p,in

)

• t

_p,in

– input propagation delay

𝑡

,

𝑡

,

𝑉

_𝑘

/2

𝑡

,

𝑉

_𝑉

𝑡

,

Result Summary

• For reasonable input slopes:

• For t

_p,avg

: V

_ThZ

is (V

_ThZN

+ V

_ThZP

)/2

• V

_ThZ

/V

_DD

typically ~1/3-1/2 at nominal supplies

• Propagation delay is a function of

• Drive strength (R

eq

)

• Load (C

_L

)

• Input rise/fall time (which is proportional to the propagation delay of the previous gate)

EECS241B L08 STANDARD CELLS ₃₂

𝑡

,

𝑡

,

𝑉

_𝑘

/2

𝑡

,

𝑉

_𝑉

𝑡

,

𝑡

,

_2𝑉

𝑉

𝑡

,

31

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Model vs. Spice Data

• For reasonable

input slope

• Model matches

Spice very well

• Model breaks with

very large t

_r

• Input looks “DC” –

traces out VTC

• Have other problems here anyways

• Short-circuit current

Signal Arrival Times

• NAND gate:

1

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2/11/2021

18 Signal Arrival Times

• NAND gate:

1 Simultaneous Arrival Times

• NAND gate:

EECS241B L08 STANDARD CELLS ₃₆

35

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Impact of Arrival Times

A

B

Delay

0 t

_B

- t

_A

A arrives early

B arrives early

Up to 25%

The edge can also advance in the opposite transition

Not in models; add derating during design

Key Point

• Timing of a cell is set by its load and input rise/fall time

• Enables static delay computation

• Circuits described as graphs

• Timing as a graph solving problem

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2/11/2021

20 2.M Standard Cell Library

Standard Cell

Library

• Contains for each cell:

• Functional information: cell = a b c

• Timing information: function of

• input slew

• intrinsic delay

• output capacitance

non-linear models used in tabular approach

• Physical footprint (area)

• Power characteristics

• Noise senistivity

• Wire-load models - function of

• Block size

• Fan-out

Library

K. Keutzer, EE244

EECS241B L08 STANDARD CELLS ₄₀

39

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Synopsys Delay Models

• Linear (CMOS2) delay model

• Similar to what we have studied so far

Example Cell Timing

• From Synopsys training materials

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2/11/2021

22 Cell Characterization (Linear Model)

Synopsys Nonlinear Delay Model (NLDM)

Delay is a function of:

EECS241B L08 STANDARD CELLS ₄₄

43

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ASAP7 (INVBUF)

cell_rise (delay_template_7x7_x1) { index_1 ("5, 10, 20, 40, 80, 160, 320"); index_2 ("5.76, 11.52, 23.04, 46.08, 92.16, 184.32, 368.64"); values ( \ "15.1096, 17.9627, 22.9385, 32.3432, 50.7722, 87.5491, 161.048", \ "16.5685, 19.4199, 24.4133, 33.79, 52.3068, 89.0219, 162.558", \ "19.524, 22.3608, 27.3353, 36.7508, 55.1933, 92.0112, 165.882", \ "24.7681, 27.6326, 32.6303, 42.0258, 60.5712, 97.4164, 170.874", \ "32.336, 35.3813, 40.5148, 49.9033, 68.3822, 105.175, 178.667", \ "42.3648, 45.7309, 51.1095, 60.6139, 79.0285, 115.701, 189.326", \ "55.156, 59.1939, 65.086, 74.8102, 93.0649, 129.979, 203.019" \ ); } rise_transition (delay_template_7x7_x1) { index_1 ("5, 10, 20, 40, 80, 160, 320"); index_2 ("5.76, 11.52, 23.04, 46.08, 92.16, 184.32, 368.64"); values ( \ "8.99752, 13.8369, 23.7312, 43.8335, 84.6028, 166.699, 333.184", \ "8.99926, 13.8598, 23.7484, 43.8239, 84.6112, 166.718, 332.823", \ "9.02142, 13.8578, 23.7, 43.8538, 84.556, 166.735, 330.605", \ "9.54922, 14.3096, 23.9855, 43.9203, 84.7136, 167.621, 331.058", \ "10.9996, 15.5611, 24.9797, 44.3711, 84.7556, 167.261, 330.939", \ "13.4332, 17.8353, 26.8038, 45.7193, 85.3774, 166.849, 332.805", \ "17.1196, 21.5314, 29.9817, 47.9893, 86.8572, 168.099, 330.889" \ ); }