## A Modified SEPIC Converter with Extended

## Gain for Universal Input Voltage Applications

**Ansu Alex**

**1**

**,**

**Anish Benny**

**2**

1

M. Tech Student, Power Electronics and Power Systems, Amal Jyothi College of Engineering, Kottayam

2

Electrical and Electronics Department, Amal Jyothi College of Engineering, Kottayam

**ABSTRACT **

**A high-power-factor rectifier suitable for universal line base on a modified version of the single-ended primary **
**inductance converter (SEPIC) is presented in this paper. The voltage multiplier technique is applied to the classical **
**SEPIC circuit, obtaining new operation characteristics as low-switch-voltage operation and high static gain at low line **
**voltage. The operation analysis and design procedure, obtained from a 10 W universal line power-factor-correction **
**prototype of the proposed converter are presented. The theoretical analysis and simulation results obtained with the **
**proposed structure are compared with the classical boost topology. **

**Keywords: AC–DC power conversion, switched circuits, voltage multipliers. **

**I. INTRODUCTION **

The boost converter is the usual structure utilized in high-power-factor (HPF) rectifiers in order to improve power factor (PF) and reduce the total current harmonic distortion (THDi). However, for universal input voltage application, the efficiency can be reduced mainly in the lowest input voltage, and the worst operation condition must be considered in the power converter design procedure [1]. The improvement of the efficiency at lower line voltage is important because the thermal design and heat sinks size are defined considering the worst operation point. Many works were developed in order to improve the operation characteristics of the power converter utilized in HPF universal input rectifiers.

The use of high static gain and low-switch voltage topologies can improve the efficiency operating with low input voltage, as presented in [15]–[18]. The voltage multiplier technique was presented in [18] for a boost converter in order to increase the static gain with reduced switch voltage. However, the boost voltage doubler cannot be used for a universal input voltage HPF rectifier because the output voltage must be higher than the double of the maximum input voltage (Vo = 800 V).A modification in the multiphase boost voltage doubler was proposed in [1] for a universal input HPF rectifier, in order to obtain high static gain at the lower input voltage with the same dc output voltage level of a classical boost converter (Vo = 400 V).

The integration of a voltage multiplier cell with a classical single-ended primary inductance converter (SEPIC) is proposed in order to obtain a high step-up static gain operating with low input voltage and a low step-up static gain for the high input voltage operation.

The operation characteristics obtained with this modification makes the Proposed structure an interesting alternative for the universal input HPF rectifier or wide input voltage range applications, operating with high efficiency. The proposed converter operates with a switch voltage lower than the output voltage, and with an input current ripple lower than the classical boost converter.

**II.PROPOSED CONVERTER **

The power circuit of the classical SEPIC converter is presented in Fig. 1. The step-up and step-down static gains of the SEPIC converter are an interesting operation characteristic for a wide input voltage-range application. However, as the switch voltage is equal to the sum of the input and output voltages, this topology is not used for a universal input HPF rectifier.

**Fig. 2 Proposed SEPIC Converter [1] **

An adaptation of the voltage multiplier technique with the SEPIC converter is presented in the proposed converter as shown in Fig. 2 . The modification of the SEPIC converter is accomplished with the inclusion of the diode Dm and the capacitor Cm. Many operational characteristics of the classical SEPIC converter are changed with the proposed modification.

The capacitor Cm shown in Fig. 2, is charged with the output voltage of the classical boost converter. Therefore, the voltage applied to the inductor L2 during the conduction of the power switch (S) is higher than that in the classical SEPIC, thereby increasing the static gain. The polarity of the voltage stored in the capacitor Cs is inverted in the proposed converter. The continuous conduction-mode (CCM) operation of the modified SEPIC converter presents the following two operation.

1) First stage ([t0,t1],Fig. 2) - At the instant t0 , the switch S is turned-off and the energy stored in the input inductor L1 is transferred to the output through the capacitor Cs and output diode Do , and also to the capacitor Cm through the diode Dm. Therefore, the switch voltage is equal to the capacitor Cm voltage. The energy stored in the inductor L2 is transferred to the output through the diode Do .

2) Second stage ([t1,t2]Fig. 3) -At the instant t1 , the switch S is turned-on and the diodes Dm and Do are blocked, and the inductors L1 and L2 store energy. The input voltage is applied to the input inductor L1 and the voltage Vcs − Vcm is applied to the inductor L2 . The voltage Vcm is higher than the voltage Vcs.

**Fig. 4 Second operation stage [1] **
The main theoretical waveforms are presented in Fig. 5.

The voltage in all diodes and the power switch is equal to the capacitor Cm voltage. The output voltage is equal to the sum of the Cs and Cm capacitors’ voltages. The average L1 inductor current is equal to the input current and the average L2 inductor current is equal to the output current.

**III. THEORETICAL ANALYSIS **

The main equations and the theoretical analysis of the proposed converter are presented in this section. The results of the theoretical analysis are compared with the classical boost converter in order to show the positive and negative aspects of the proposed converter.

Some comparison with the classical SEPIC converter is also presented because the proposed topology is obtained from this converter. The equations defined by the theoretical analysis are utilized for the determination of the inductances and capacitances of the proposed converter. The theoretical analysis is developed considering the operation as an HPF rectifier, and the utilization of an ac voltage source and a full-bridge diode rectifier connected to the input of the proposed converter is considered.

All analyses are accomplished for an application with an ac input voltage changing from Vi = 9 Vrms to Vi = 20 Vrms, an output voltage equal to Vo = 30 Vdc, and a nominal output power equal to Po = 10 W.

**A. Static Gain **

The static gain of the proposed converter can be obtained considering that the average inductor voltage is zero at the steady state. Therefore, the relation presented in (1) must occur at the steady state for the inductor L1

Vi tON = (VCM-Vi) tOFF (1)

Vi D = (V CM- Vi) (1-D) (2)

Therefore, the CM capacitor voltage is defined by (3), which is the same equation of the classical boost static gain given by

(3)

During the period where the power switch is turned-off (toff), the diodes Dm and Do are in conduction state, and the following relation can be defined:

V o = V CS + V CM (4)

The L2 average voltage is zero at the steady state, and the following relations can be considered:

.(V CM – V CS ) t ON = (Vo- V CM) t OFF (5)

(VCM − VCS)D = (Vo − VCM)(1 − D). (6)

Substituting (3) and (7) in (6), the static gain of the proposed converter is obtained and presented in (8)

V CS = V o – V CM (7)

(8)

operation with a higher static gain results in an improvement in the operation with the lower input voltage. The step-up and step-down characteristics of the classical SEPIC converter are not maintained in the modified SEPIC converter. The proposed structure cannot operate with an output voltage lower than the input voltage.

**Fig. 6. Comparison of Static Gain [1] **

The voltage of the series capacitor (Vcs) is defined by substituting (3) and (8) in (7), resulting the following equation:

VCS / V i = D / (1-D) (9)

**B Input current Ripple and L1-L2 Inductances **

The input inductance value is defined as a function of the maximum input current ripple. As the classical SEPIC, boost, and the modified SEPIC converters present the same input stage, the equation for the determination of the input current ripple is the same for all converters. The input current ripple (ΔiL1 ) during the conduction of the power switch is defined by the following equation:

Δ i L1 = (Vi D) / L 1 f (10)

where f is the switching frequency.

**C. Series Capacitor (Cs) and Multiplier Capacitor (Cm) **

The Cs series capacitor voltage and the Cmmultiplier capacitor voltage change with the line input voltage variation. Therefore, these capacitances cannot be large as the output filter capacitor (Co ). However, these capacitances present a high-frequency voltage ripple due to the circulating current and the capacitor charge variation (ΔQ). As the circulating current in both capacitances are equal, the high frequency voltage ripple is the same. During the power switch turn-on period, the current in the Cs and Cm capacitances is equal to the L2 inductor current. The capacitor charge variation ΔQ is calculated as

ΔQ = i L2 D T (11)

The high-frequency capacitor voltage ripple (ΔVc ) can be defined by (12), as a function of the capacitor charge variation

ΔV c = ΔQ / C (12)

C S = C M =( i L2 D) / Δ V c f (13)

where f is the switching frequency.

**D. Output Capacitor **

The output filter capacitor (Co ) is determined as in the classical boost converter. The capacitance is defined by a function of the output power (Po ), the grid frequency (fG), and the low frequency output voltage ripple (ΔVo ). Considering an output voltage ripple equal to 1% of the output voltage, the output capacitance is calculated as

C o = Po / 2 π f G 2 Vo Δ V o (14)

**IV. SIMULATION STUDIES AND RESULTS OF PROPOSED SEPIC CONVERTER **

Using MATLAB the simulation of proposed SEPIC converter is performed. The waveforms of the output voltage is shown. The value of the inductors and the capacitors, are designed as discussed in the theoretical analysis.

**Fig. 7. MATLAB/ SIMULINK model of proposed converter **

The input side consists of a bridge rectifier as shown. The power circuit consists of a voltage multiplier cell consisting of diode Dm and capacitor Cm. Output side comprises of a filter inductor and a filter capacitor.

The output voltage waveform is shown in Fig. 8

For the designed values, an output voltage of 30 V is obtained when 9 Vrms input is given to produce power of 10 W. The output voltage takes considerable time to settle down to a constant value, nearly 1sec, due to the charging and discharging of the inductors.

The output voltage ripple is shown in Fig. 9

**Fig. 9 Output voltage ripple **

It can be seen that the output voltage ripple is very much lower than classical SEPIC converter. The experimental set up of the proposed converter is shown in Fig. 10

**Fig. 10 Experimental set up of proposed converter **
The hardware set up of proposed converter consists of following parts

1. A Bridge rectifier in the input side 2. A 555 timer circuit

**CONCLUSION **

The project has presented the design and development of a modified SEPIC converter prototype with an output power of 10 W incorporating a multiplier cell consisting of a diode and a capacitor. Although the proposed structure presents a higher circuit complexity than the classical boost converter, the advantages obtained are the higher static gain for the operation with the lower input voltage range, and a lower output voltage ripple. A 555 Timer circuit is used to provide base drive to the transistor, TIP122, used as power switch.

**REFERENCES **

[1]. P. F .de Melo, R. Gules, E. F. Romaneli, and R.C Annunziato, “A modified SEPIC converter for high-power-factor rectifier and universal input voltage applications,” IEEE Trans. Power Electron., vol. 25, no. 2, pp. 310–321, Feb. 2010.

[2]. O. Garc´ıa, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, “Single phase power factor correction: A survey,” IEEE Trans.

Power Electron., vol. 18, no. 3, pp. 749–755, May 2003.

[3]. B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. P. Kothari, “A review of single-phase improved power quality AC– DC converters,” IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 962–981, Oct. 2003.

[4]. A. Sabzali, E. H. Ismail, M. Al-Saffar, and A. Fardoun, “A new bridgeless PFC Sepic and Cuk rectifiers with low conduction and switching losses, ”IEEE Trans. Ind. Appl., vol. 47, no. 2, pp. 873–881, Mar./Apr. 2011.

[5]. J. Zhang, M. M. Jovanovic, and F. C. Lee, “Comparison between CCM single-stage and two-stage boost PFC converters,”

in Proc. Appl. Power Electron. Conf. Expo. (APEC), Mar. 1999, vol. 1, pp. 335–341

[6]. J. Chen, D. Maksimovic, and R. W. Erickson, “Analysis and design of a low-stress buck-boost converter in universal-input

PFC applications,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 320–329, Mar. 2006.

[7]. E. H. Ismail, “Bridgeless SEPIC rectifier with unity power factor and reduced conduction losses, ”IEEE Trans. Ind. Electron., vol. 56, no. 4, pp. 1147–1157, Apr. 2009.

[8]. D.D.C. Lu, H. H. C. Iu, and V. Pjevalica, “A single-stage AC/DC converter with high power factor, regulated bus voltage,

and output voltage,” IEEE Trans. Power Electron., vol. 23, no. 1, pp. 218–228, Jan. 2008.

[9]. J. Qian and F. C. Lee, “A high efficient single stage single switch high power factor ac/dc converter with universal input,”

IEEE Trans. Power Electron., vol. 13, no. 4, pp. 699–705, Jul. 1998.