Reconfig'09
Cancun, Mexico
New OPBHWICAP
Interface for Real-Time
Partial Reconfiguration
of FPGA
Julien Delorme, Amor Nafkha,
SUPELEC - Campus de Rennes - France
SCEE – Signal, Communications et Electronique Embarquée
IETR – UMR CNRS 6164
Institut d'Electronique et Télécommunications de Rennes
Julien Delorme, Amor Nafkha,
Pierre Leray, Christophe Moy
SUPELEC/IETR
10 December 2009
Experiments on Partial
Reconfiguration of FPGA
•
Prototyping PR since 2003
•
Developed our own design flow
– Virtex devices
– based on Xilinx tools (beyond usual use)
•
Application domain: Software defined radio
•
Application domain: Software defined radio
– SDR domain is extremely demanding in both
processing power and real-time flexibility
– PR has been foreseen for a while as an
enabling technology for SDR
– Xilinx decided to develop this technology for
SDR market
SDR-oriented publications
on Partial Reconfiguration
1.
Dominique NUSSBAUM, Karim KALFALLAH, Raymond KNOPP, Christophe MOY, Amor NAFKHA, Pierre LERAY, Julien DELORME,
Jacques PALICOT, Jerome MARTIN, Fabien CLERMIDY, Bertrand MERCIER, Renaud PACALET
"Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques"
DSD’09, 12th Euromicro Conference on Digital System Design, 27-29 Aug. 2009, Patras, Greece
2.
Christophe MOY, Amor NAFKHA, Pierre LERAY, Julien DELORME, Jacques PALICOT, Dominique NUSSBAUM, Karim KALFALLAH,
Hervé CALLEWWAERT, Jérôme MARTIN, Fabien CLERMIDY, Bertrand MERCIER, Renaud PACALET
"IDROMel: An Open Platform Addressing Advanced SDR Challenges"
SDR Forum Technical Conference'08, 27-30 November 2008, Washington DC, USA
3.
Julien DELORME, Jérôme MARTIN, Amor NAFKHA, Christophe MOY, Fabien CLERMIDY, Pierre LERAY, Jacques PALICOT
“A FPGA partial reconfiguration design approach for cognitive radio based on NoC architecture”
NEWCAS'08, 22-25 juin 2008, Montréal Canada
4.
Amor NAFKHA, Julien DELORME, Renaud SEGUIER, Christophe MOY, Jacques PALICOT
"A heterogeneous reconfigurable platform for cognitive radio systems"
"A heterogeneous reconfigurable platform for cognitive radio systems"
5th Karlsruhe Workshop on Software Radios, WSR'08, Karlsruhe, Allemagne, Mars 2008
5.
Loïg GODARD, Hongzhi WANG, Christophe MOY, Pierre LERAY
"Common Operators Design on Dynamically Reconfigurable Hardware for SDR Systems"
SDR Forum Technical Conference’07, Denver (USA), 5-9 November 2007
6.
Jean-Philippe DELAHAYE, Pierre LERAY, Christophe MOY
"Designing a Reconfigurable Processing Datapath for SDR over Heterogeneous Reconfigurable Platforms"
SDR Forum Technical Conference’07, Denver (USA), 5-9 November 2007
7.
Jean-Philippe DELAHAYE, Jacques PALICOT, Christophe MOY, Pierre LERAY
“Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform”
IST Mobile and Wireless Communications Summit'07, 1-5 July 2007, Budapest, Hungary
8.
Jean-Philippe DELAHAYE, Pierre LERAY, Christophe MOY, Jacques PALICOT
"Managing Dynamic Partial Reconfiguration on Heterogeneous SDR Platforms"
-PR real-time
implementation demos
•
E2R-phase 2:
– European research program
– Sundance platform (DSP+FPGA+ADAC)
– RT modulation switching (DSP+FPGA PR)
– demos in 2005 and 2006
– demos in 2005 and 2006
•
IDROMel:
– French research program
– NoC context (based on CEA FAUST chip)
– integration in a NoC HW and protocol context
– real-time reconfiguration of ultra high data rate
PR is coming in Xilinx tools
but…
•
ISE v11
– OPBHWICAP ICAP controller
– far less than possible
technological capabilities
•
First step: IP_ICAP8
MicroBlaze
OPB bus
ICAP
B
R
A
M
Management
OPBHWICAP
MicroBlaze
OPB bus
ICAP
B
R
A
M
Management
OPBHWICAP
ICAP
Multiplexer and
IP_ICAP8
8
ICAP
Multiplexer and
IP_ICAP8
8
gain of 124 in
•
First step: IP_ICAP8
– 8 bits version
(for Virtex 2)
•
Second step: IP_ICAP32DMA
– 32 bits version
(for Virtex 4 & 5)
max technological capabilities
Multiplexer and
byte reverse
32
MicroBlaze
OPB bus
GPIO bus
Multiplexer and
byte reverse
32
MicroBlaze
OPB bus
GPIO bus
ICAP
Registers
IP_ICAP32DMA
32
32
SRAM
Management
32
32
32
MicroBlaze
GPIO bus
SRAM ctrl
gain of 124 in
reconfiguration
time
Proof of concept
•
Example of a bitstream of 25 kB (encod.+intrl.)
– note that minimizing bitsream size is also a work
in itself (parameterization for instance)
– 6250 32bits words
62.5 µs @ 100 MHz
– init overhead (register loading): 5 µs
– init overhead (register loading): 5 µs
– total reconfiguration time of
67.5 µs
– validated also @125 MHz (500 MB/s)
55 µs
•
Real-time 4G radio adaptation on a video
stream application
•
interfaces compatible with all ML5xx boards
See you at the poster
SCEE team
S
ignal
C
ommunication
& E
mbedded
E
lectronics
AC Group
A
utomatics &
C
ommunication
PR design
- Xilinx Virtex devices - ICAP - external RAM - microblaze - BusMacro before ISE v11New OPBHWICAP Interface for Real-Time Partial Reconfiguration of FPGA
Julien Delorme, Amor Nafkha, Pierre Leray, Christophe Moy
SUPELEC / IETR Avenue de la Boulaie CS 47601
F-35576 Cesson-Sevigné CEDEX, France
contact: [email protected]
- only a sub-part of a FPGA is reconfigured - while the rest of the component still works - opens the SW flexibility to the HW
performance
- any time custom design for (computing and space) efficiency
Partial Reconfiguration principles
PR advantages
- small size of the bitstream- fast reconfiguration (starting from a few µs) - less memory-demanding for storage - low bandwidth overhead for Over-The-Air
bitstream download in SDR context
- specific and original design flow - ISE with a modular approach - 1 project per module for static
modules
- 1 project per configuration for PR modules
- PlanAhead
- specification of PR and static modules
- physical allocation of modules with floorplanning tool - partial bitstreams generation for
PR modules
- design alternatives: trade-off between efficiency and design ease - IP design approach for minimizing
reconfigurable area and bistreams size - bitstream generation (difference-based
partial bitstream)
- basic PR introduction in current CAD tools (ISE v11) now
PR design secrets
Reconfig'09
Conference
Cancun, Mexico
8-11 December 2009
SRAM FPGA MicroBlaze OPB EMC PRM OPB HWICAP OPB RS232 GPIO LED Switchs … Bus OPB•
PR = Combining
HW processing
power with
SW flexibility
IST Mobile Summit’06 – 4-8 June 2006 – Mykonos, GREECE
ICAP Multiplexer and byte reverse IP_ICAP8 32 8 MicroBlaze OPB bus GPIO bus ICAP Multiplexer and byte reverse IP_ICAP8 32 8 MicroBlaze OPB bus GPIO bus MicroBlaze OPB bus ICAP B R A M Management OPBHWICAP MicroBlaze OPB bus ICAP B R A M Management OPBHWICAP Ethernet
Host video stream sent
Host video stream sent Host video stream receivedHost video stream received
FPGA FPGA ASIC ASIC
Proof of concept demonstrator
ICAP interfaces
Results
Reconfiguration duration
Size
- video streaming (no video interruption) - 4G real-time SDR (radio) application (100 Mbps) - baseband IPs reconfiguration in a NoC context - NoC based on FAUST chip from CEA
XILINX ISE v11 SUPELEC Virtex 2 to 5
SUPELEC Virtex 4 & 5
bitstream download in SDR context
PR Reconfiguration performance comparison
8372 2722 67,5 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
OPBHWICAP IP_ICAP8 IP_ICAP32DMA
PR IP management R e co n fi g u ra ti o n t im e (i n µ s)
gain of 124
in reconfiguration time
tools (ISE v11) now
ICAP Registers IP_ICAP32DMA 32 32 SRAM Management 32 32 32 MicroBlaze OPB bus GPIO bus SRAM ctrl 0 0 1 Nb BRAMs 71 45 210 Nb LUTs 58 43 153 Nb FlipFlops 35 28 131 Nb slices ICAP32DMA ICAP8 OPBHWICAP 0 0 1 Nb BRAMs 71 45 210 Nb LUTs 58 43 153 Nb FlipFlops 35 28 131 Nb slices ICAP32DMA ICAP8 OPBHWICAP
Max of technological capabilities: Virtex V - 400 MB/s @ 100 MHz