19nm 112.8mm 2 64Gb Multi-level Flash Memory with 400Mb/s/pin 1.8V Toggle Mode Interface

(1)

19nm 112.8mm

2

64Gb Multi-level Flash Memory

with 400Mb/s/pin 1.8V Toggle Mode Interface

Noboru Shibata

Memory Design Department Toshiba Corporation

Flash Memory Summit 2012 Santa Clara, CA

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Outline

 Introduction to 19nm 64 Gbit MLC NAND (400 Mb/s/pin interface)

 Chip Architecture for Small Die Size  MLC Programs Techniques

 New Features(Read-Latency Reduction)  Summary of Key Features

 Conclusion

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 Introduction

 Conclusion

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1 10 100 1000 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 1Gb D2 (160nm) 2Gb D2 (130nm) 4Gb D2 (90nm) 8Gb D2 (70nm) 8Gb D2 (56nm) 128GbD3(19nm) 64GbD2(19nm) 16Gb D2 (43nm) 16Gb D4 (70nm) 32Gb D3 (56nm) 32Gb D3 (32nm) 64Gb D4 (43nm) 64Gb D2 (24nm) 1000

NAND Flash Density Trend

Note: D# = # bits per cell

D en si ty(M b /m m 2 ) Year

 Since first 160nm 1Gb MLC was commercially

introduced in 2001, Memory Density has expanded by

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Comparisons of

first 1Gb MLC and latest 64Gb MLC

5/29 Technology 160nm one-ninth _19nm Density 1Gb 64 times 64Gb Die Size 137mm2 _112.8mm2 Mb/mm2 _7.5 _{80 times} ₅₈₁ Architecture Conventional Even / Odd All-Bit-Line(ABL)

SA configulation Both Sided Single Sided

Program unit 2kB (= 512B x4Plane) 8 times 16kB (=16kB x1Plane)

tProg 1.1ms 1.1ms

Prog. Perform. 1.9MB/s 8 times 15MB/s

Year 2001 10 years 2011

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100 200 300 400 500 600 700 800 2009 2010 2011 2012 2013 D e n s ity (Mb /m m 2 ) SamSung(20nmD3) Toshiba/SanDisk(19nmD3) IM(32nmD3) Toshiba/SanDisk(24nmD2) Toshiba/SanDisk(19nmD2) SamSung(32nmD2) Hynix(32nmD2) SamSung(21nmD2) 3bit /Cell 2bit /Cell

Comparisons of 3bit /cell and 2bit /cell

 Two different directions (3bit/cell and 2bit/cell)

 3bit/cell enables highest Mb/mm2

 2bit/cell offers better performance and reliability

Note: D# = # bits per cell

D en si ty(M b /m m 2 ) 6/29

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 Introduction

 Chip Architecture for Small Die Size

• Single-Array Configuration

• One Sided All-Bit-Line(ABL) Architecture • High Speed Toggle Mode Interface

 MLC Programs Techniques

 Conclusion

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Single Array Configuration

Conventional

Evne / Odd Architecture

All-Bit-Line (ABL) Architecture 16kB-cells 8kB-Page 8kB-Page 16kB-cells 64Gb Cell Array 16kB-Page 32Gb Cell Array 16kB-cells 32Gb Cell Array

2-Plane array configuration

Single array configuration ⇒ Small Die size

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Conventional

Two-sided SA  Half of SAs are placed on each

side of the array due to complexity of SA layout.

9/29

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 Same Metal pitch in SA as BL pitch Conventional Two-sided SA This work One-sided SA Same Metal pitch

 Spacer patterning process

F F F F 2 F 2 F 2 F 2 10/29

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Conventional

Two-sided SA

This work

One-sided SA

Die Size Reduction

(fit into uSD)

112.8mm2_(94%) －30% Row Decoder Cell Array 117.3mm2(100%) Peripheral Circuits －25% Sense Amplifier 11/29

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Data Output

High Speed Toggle Mode Interface

Conventional

Two-sided sense amplifier

This work

One-sided sense amplifier

SENSE AMPLIFIER SENSE AMPLIFIER Long w ir ings Data Path

Data Path _{Data Path}

Data Output

Cell Array Cell Array

SENSE AMPLIFIER

 Minimized signal delays

 Lower power consumption

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Measured Data Output Eye-Diagram

0 0.3 0.6 0.9 1.2 1.5 1.8 0.0 2.5 5.0 7.5 10.0 DQS DQ(IO2) DQ(IO3) Time(ns) Vo lta g e (V) 

400Mb/s/pin＠1.8V high-speed

toggle mode interface is achieved!

5ns (400Mb/s/pin) V o ltag e(V ) _{DQ(IO3) DQ(IO3)} DQS 13/29 Time(ns)

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 Introduction

 Chip Architecture for Small Die Size

 MLC Program Techniques

• Bit-Line Bias Acceleration (BLBA)

• BC-States-First Program Algorithm

 Conclusion

14/29

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Bit-Line (BL) RC

24nm 64Gb D2 19nm 64Gb D2

Bit-Line ~ 65,000cells



Cells connecting to one Bit-Line is doubled

Bit-Line ~ 130,000cells

 Larger Bit-Line (BL) RC

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Cell array BLS BLX XXL Acceleration Period Bit-Line BLC "VBL+Vth" "ON" "ON" "VBL+Vth"

Bit-Line Bias Acceleration (BLBA)

 Bit-Line pre-charge time is reduced by 20% "VBL" "VBL+Vth" BLC BLX XXL “ON” “VBL+Vth” Vbit-line Acceleration Period “VBL+Vth” BLX “ON” BLC XXL “OFF” Sense Period Time Time Bit-Line Bit-Line Voltage Acceleration Period 16/29 Cell array BLS BLX XXL Sense Period Bit-Line BLC "OFF" "ON" "ON" "VBL+Vth" Bit-Line Sense Period XXL XXL

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Time

Conventional-Program Algorithm

Program pulse State “a” verify State “b” verify State “c” verify

State “b” and “c” Programing voltage is “high” Completion of state “a”

# of cells

Program disturb

Cell-to-Cell Coupling Effect

････

WL

Voltage

17/29

“a”

“a” “a” “a” “b” “b” “c”

Vth Vth

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････

WL

Voltage

････

BC-States-First Program Algorithm

Program pulse State “a” verify State “b” verify state “c” verify

 “Program disturbs” and “cell-to-cell coupling effect” are suppressed

 Bigger incremental step size can be applied

18/29

Time

Completion of state “b”,”c” # of cells

Cell-to-Cell Coupling Effect “a” “b” “b” “c” _“c”

Vth Vth “b” “c”

State “a” Programing voltage is “low”

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MLC Program Improvement

Program throughput : 15MB/s(16kB) tProg : 1.1ms



All-Bit-Line architecture (ABL)



High program throughput with high reliability

tProg reduction

----

(10%)

19/29



Bit-Line Bias Acceleration (BLBA)



BC-states-first program algorithm



Air Gap technology reduces FG coupling effect and word line(WL) RC

(6%) (8%)

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 Introduction

 Conclusion

20/29

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Program-Suspend Function

True Ready/Busy

Operation

CacheReady/Busy

Prog. Command

True Busy Prog.

P.V.

Prog Prog _P.V. Prog _P.V. Prog Read Command

Cache Busy

Cache Busy

Read

 Any page within any block can be read

Read Data Prog &P.V. Time Time Internal operation (WL voltage) 21/29

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 Read data shifted out while program resumes

True Ready/Busy

Operation

CacheReady/Busy

Prog. Command

True Busy Prog.

P.V.

Prog Prog _P.V. Prog _P.V. Prog Read Command Cache Busy Cache Busy Read Read Dataout P.V. Prog P.V. Read Data Internal operation (WL voltage) Time Time Prog &P.V. 22/29

Program-Suspend Function

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 Same sequence as at Reset command.

 Program operation as well as read operation is

available without any restrictions on address input

Ready/Busy Operation Vera2 Evfy Vera 3 dVera Read /Prog. Busy Read/Prog. Vera1 Evfy dVera Erase Command _Command Suspend Internal operation (Vera) Time Time 23/29

Erase-Suspend Function

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 Read data can be shifted out upon resume of erase sequence. Read Dataout Cache Busy Cache Ready/Busy

Operation Resume Erase _Command

Busy Erase True Ready/Busy Vera4 Evfy Vera5 Evfy Vera3 Evfy ･････ dVera dVera Suspend Command(FFh) Vera2 Evfy Vera 3 dVera Time Internal operation (Vera) 24/29

Erase-Suspend Function

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 Read latency at program/erase is improved to 50us, which is comparable to normal read latency(~40us)

1ms at program

4ms at erase 50us

Conventional _{This work}



Program-suspend function



Erase-suspend function 25/29

Read-Latency Reduction

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 Introduction

 New Features(Read-Latency Reduction)

 Summary of Key Features  Conclusion

26/29

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Summary of Key Features

Sense Amplifier Pe rip h era l C irc u it s 64Gb Array  Density: 64Gb, 2-bit/cell

 One sided ABL architecture

 Organization

 16kB / Page

 2 Pages / WL

 Single-array configuration

 Program Throughput: 15MB/s

 Burst Cycle Time: 400Mb/s/pin Toggle mode @1.8V

 Power Supply: 2.7V to 3.6V

 Technology: 3-Metal 19nm CMOS

 DieSize: 112.8mm2

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 For the first time, a 112.8mm2_{64Gb Multi-level}

(2bits/cell) NAND flash memory is developed

 19nm CMOS technology

 Single Array configuration

 One sided All-Bit-Line

 15MB/s programing throughput with high reliability

 Bit-Line Bias Acceleration(BLBA)

 “BC” states-First program algorithm

 Read latency is improved by Program-Suspend and Erase-Suspend functions

 400Mb/s/pin 1.8V high speed Toggle Mode interface

28/29

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The author thank M. Momodomi1_{, S. Ohshima}1_,

S. Mori1_{, T. Hara}1_{, K. Quader}2_{, M. Mofidi}2_,

R. Shrivastava2, Y. Fong2, S. Sprouse2 , K. Kanda1,

T. Hisada1_{, K. Isobe}1_{, M. Sato}1_{, Y. Shimizu}1_,

T. Shimizu1, T. Sugimoto1, T. Kobayashi1, K. Inuzuka1,

N. Kanagawa1_{, Y. Kajitani}1_{, T. Ogawa}1_{, J. Nakai}1_,

K. Iwasa1, M. Kojima1, T. Suzuki1, Y. Suzuki1, S. Sakai1, T. Fujimura1, Y. Utsunomiya1, T. Hashimoto1,

M. Miakashi1_{, N. Kobayashi}1_{, M. Inagaki}1_,

29/29 1_{Toshiba Corp., Yokohama, Kanagawa, Japan}

2_{SanDisk Corp., Milpitas, California, USA}

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Y. Matsumoto1_{, S. Inoue}1_{, Y. Suzuki}1_{, D. He}1_{, Y. Honda}1_,

J. Musha1, M. Nakagawa1, M. Honma1, N. Abiko1, M. Koyanagi1, M. Yoshihara1, K. Ino1, M. Noguchi1,

T. Kamei2_{, Y. Kato}2_{, S. Zaitsu}2_{, H. Nasu}2_{, T. Ariki}2_,

H. Chibvongodze2, M. Watanabe2, H. Ding2, N. Ookuma2,

R. Yamashita2_{, G. Liang}2_{, G. Hemink}2_{, F. Moogat}2_,

C. Trinh2, M. Higashitani2, T. Pham2 , K. Kanazawa1 and the entire Design, Layout, Device, Evaluation,

Test, and Process teams for supporting the development of this project

30/29 1_{Toshiba Corp., Yokohama, Kanagawa, Japan}

2_{SanDisk Corp., Milpitas, California, USA}