Improved NAND Flash Memories Storage Reliablity Using Nonlinear Multi Error Correction Codes

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http://www.ripublication.com/aeee.htm

Improved NAND Flash Memories Storage Reliablity Using

Nonlinear Multi Error Correction Codes

E. Ramakrishna Naik* and L.S. Devaraj**

*M.Tech(VLSI), Dept. of ECE, Intellectual Institute Of Technology, Anantapur. Assistant professor Dept. of ECE, Intellectual Institute Of Technolog, Anantapur.

E-mail: *[email protected], **[email protected]

Abstract

Multi-level cell (MLC) NAND flash memories are popular storage media because of their power efficiency and large storage density. Conventional reliable MLC NAND flash memories based on BCH codes or Reed-Solomon (RS) codes have a large number of undetectable and miscorrected errors. Moreover, standard decoders for BCH and RS codes cannot be easily modified to correct errors beyond their error correcting capability t = [d-1/2] , where d is the Hamming distance of the code. In this paper, we propose two general constructions of nonlinear multi-error correcting codes based on concatenations or generalized from Vasil’ev codes. The proposed constructions can generate nonlinear bit-error correcting or digit-error correcting codes with very few or even no errors undetected or miscorrected for all codewords. Moreover, codes generated by the generalized Vasil’ev construction can correct some errors with multiplicities larger than t without any extra overhead in area, latency, and power consumption compared to schemes where only errors with multiplicity up to t are corrected. The design of reliable MLC NAND flash architectures can be based on the proposed nonlinear multi-error correcting codes. The reliability, area overhead and the penalty in latency and power consumption of the architectures based on the proposed codes are compared to architectures based on BCH codes and RS codes. The results show that using the proposed nonlinear error correcting codes for the protection of MLC NAND flash memories can reduce the number of errors undetected or miscorrected for all codewords to be almost 0 at the cost of less than 20% increase in

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E. Ramakrishna Naik & L.S. Devaraj

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power and area compared to architectures based on BCH codes and RS codes.

Index Terms: Multi-error correcting codes, nonlinear codes, re-liable memory.

1. Introduction

The semiconductor industry has witnessed an explosive growth of the NAND flash memory market in the past several decades. Due to its high data transfer rate, low power consumption, large storage density and long mechanical durability, the NAND flash memories are widely used as storage media for devices such as portable media players, digital cameras, cell phones, and low-end netbooks.

The increase of the storage density and the reduction of the cost per bit of flash memories were traditionally achieved by the aggressive scaling of the memory cell transistor until the multi-level cell (MLC) technology was developed and implemented in 1997. MLC technology is based on the ability to precisely control the amount of charge stored into the floating gate of the memory cell for he purpose of setting the threshold voltage to a number of different levels corresponding to different logic values, which enables the storage of multiple bits per cell.

However, the increased number of programming threshold voltage levels has a negative impact on the reliability of the device due to the reduced operational margin. The raw bit error rate of the MLC NAND flash memory is around 10 and is at least two orders of magnitude worse than that of the single level cell (SLC) NAND flash memory . Moreover, the same reliability concerns as for SLC NAND flash memories, e.g., program/read disturb, data retention, programming/erasing endurance, and soft errors [may become more significant for MLC NAND flash memories.

Hence a powerful error correcting code (ECC) that is able to correct at least 4-bit errors is required for the MLC NAND flash memories to achieve an acceptable application bit error rate, which is no larger than 10 .

Several works have investigated the use of linear block codes to improve the reliability of MLC NAND flash memories. In, the authors presented a high-throughput and low-power ECC

NAND flash memory chip incorporating a 250 MHz BCH error correcting architecture was shown. The author of demon-strated that the use of strong BCH codes (e.g., 12,15,67,102) can effectively increase the number of bits/cell thus further in-creasing the storage capacity of MLC NAND flash memories. In , an adaptive-rate ECC architecture based on BCH codes was proposed. The design had four operation modes with dif-ferent error correcting capabilities. An ECC architecture based on

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Ree equ for base base can

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MLC NA

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Construc

e error dete ctions. The n (RS) codes oposed in , The architec r and the d H codes wit mmetric lim asymmetric

AND Flash

ll is able to f the cell. In ssian distrib f the NAND ages. Each p cally the sa tions such a mber of byte pare bytes m 6 data byte of the error other types ostly determ of more po SLC flash m es include gram-ming/e memories rb and data metry . Mor more likely local data d etric error m r. The distor

ctions of N

ecting prop nonlinearity s of length 8 which can cture achiev decoder but th the same mited-magnit c errors of m

h Memor

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Nonlinear

perties of n y of a fun 828 and 820 n correct all ves higher th needs 32 m e error corr tude error c mul-tiplicitie

ies

ltiple bits b the threshol o random m mory is organ data byte in the rest wear-leveli is usually 3 quired as the o the exist g codes used ries such as he number r correcting he primary voltage dist urance, and rrors are as for MLC N perimental r uniformly w y. Thereby, be the erro

r Multi-Er

nonlinear co nction 0 informatio bit errors o hroughput, r more redund ecting capa correcting c es up to . by precisely ld voltage o manufacturin nized in blo es and spa of the page ing . The pr 3%, e.g., 64 e page size tence of sp d for NAND s SRAM an of redunda g codes for N failure mec tribution, p d single eve symmetric, NAND flash results show within a pag throughout or-free outp

rror Corr

odes are hi on digits con of multiplic requires les dant bits tha ability. In , code was p y controllin of the whole ng variation ocks. Each b are bytes. C and are typ roportion of 4 spare byte e increases, pare bytes, D flash mem nd DRAM ant bits. Th NAND flash cha-nisms fo program/rea ent upset. H e.g., errors h memories w that errors ge without t this pape put of the m

recting Co

ighly relate can be nstructed ov city less tha ss area overh an architect an architec proposed, w ng the thres e memory a s . block consis Cells in the s pi-cally used f the spare b es for 2048 e.g., 218 s the numbe mories is no where the his allows f h memories or MLC NA ad disturb, However, w s introduced s errors hav s in MLC f any observ r we assum memory and

odes

ed to nonli defined ver an or head tures cture which shold array sts of spare d for bytes data spare er of ot as area for a . AND data while d by ve no flash vable me a be inear

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112 valu non 3.1 The con T Let not cod 24 where ue of is nlinear funct Multi-Erro e first constr catenating l Table I: Out Theorem 1: on-zero erro . Proof: Let , The error m If and be satisfied Algorithm es in theore Input : C¯= Output : e= denotes s, the high tion when or Correcti ruction of n linear and n tput of the D : Let be a line or will be d b , a masking equ d , are d. The error 1: Error Co em1: =(x1¯,x2¯,x3 =(e1,e2,e3),E the probabi her the corr

. ing Codes B nonlinear mu onlinear red Decoder for ear code wi is the enco etected with be the error and uations can b e not both 0 will always orrecting A 3¯) ERR ility of occ responding Based on C ulti-error co dundant dig r Linear Cod be a no ith Hammin oding functi h a probabil r vector, wh . be written a 0, at least on s be detected Algorithm fo E. Ramakr currence of nonlinearit Concatenati orrecting co its.

des that Can

onlinear fun ng distance

ion. The cod

lity of at lea ere as ne of the eq d. or the nonlin rishna Naik event . T ty of is. ions odes is based n Correct Up nction with , where de defined b ast quations sh near multi-& L.S. Dev The smaller is a per d on the ide p to T Error nonlinearit by own above error correc varaj r the rfect ea of rs. ty . and will cting

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4.

In th non con BCH 4.1 The line stru need the is prop mul deta corr para 1. begin 2. Decode 3. If Ev =0 4. No erro 5. else if E 6. Uncorre 7. else if E 8. Uncorre 9. else 10. Ev >0; 11. If e¯1=0 12. Error in 13. ERR=0 14. Else 15. Comput 16. Comput 17. If ŝ=0 th 18. e=(e1,e 19. else 20. Uncorre 21. ERR=1

Hardwar

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his section, nlinear multi sumption of H codes and Encoder A e encoder fo ear feedback uctures for L ds clock computation the number Compared posed nonl ltiplier and ailed archit recting code allel LFSR p e V, comput 0 ,S=0 then ors are detec Ev =0 ,S≠0 t ecteble mult Ev =-1 then ecteble mult 0 then n the redund 0; te x1¯= x1¯ te ŝ=f(x1¯) hen 2,e3), ERR= ecteble mult

re Design

rror Corre

we present i-error corre f the propos d RS codes Architecture or BCH cod k shift regi LFSRs are w cycles whil n of the red r of informa to the enco linear mult two registe tecture of t e generated proposed in te S; cted ,ERR=0 then ti-errors are ti-errors are dant digits a ¯ e1¯, x2¯ = x2¯; =0; ti-errors are

of the En

ecting Co

t the encode ecting codes sed architec (see Section e des and RS c ister (LFSR well studied le the parall dundant bits ation bits an oder for the ti-error cor ers for the c the encode by Theorem n [26]. The p 0; e detected ,E e detected ,E are detected = x2¯ e2¯; e detected ,

ncoder an

odes

er and the d s. We estim ctures and co n V). codes are co R) architect d in the com lel LFSR n at the cost nd is the pa e BCH code rrecting co computation r for the n m 3 is show parallelism ERR=1; ERR=1; ,

d the Dec

decoder arch mate the area

ompare them onventional ure. Both t mmunity. In eeds only of higher ha arallelism le es and RS des require n of the non nonlinear ( wn in Fig. 2. level of the

coder for

hi-tectures f a, the latency m to archite ly impleme the serial a n general, t clock ardware com evel of the L codes, the es one mo nlinear redu (8281,8201, The design e design is 1

Nonlinea

for the prop y and the po ectures base

ented based and the par the serial L cycles to fi mplexity, w LFSRs. encoder for ore finite undant bits. 11) 5-bit e n is based on 10. During

ar

osed ower ed on on a rallel LFSR inish where r the field The error n the each

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clock cycle, 10 information bits are inputted to the encoder. The most significant bit of the message is input via a separate port. The first information bit for the BCH code is derived by XORing with the first bit of at the first clock cycle (when as shown in the figure). The bottom half of the architecture is a parallel LFSR used to generate the redundant bits for BCH codes. is a 10 70 binary matrix . During each clock cycle, the 10 most significant bits in the shift register are XORed with the new input and then multiplied by . The output of the multiplier is XORed with the shifted data from the shift register to generate the input to the register. The top half of the architecture is for the computation of nonlinear redundant bits. During the even-numbered clock cycles, the 10-bit input is buffered. During the odd-numbered clock cycles, the buffered data is multiplied by the new input in and then added to the output registers. A 10-bit mask is XORed with the data in the output register to generate the nonlinear redundant bits. For the (8281,8201,11) 5-error-correcting code, 820 clock cy-cles are required to complete the encoding of the message.

The encoder for the (8280,8200,11) nonlinear 5-bit error correcting code based on Theorem 1 is similar to the one shown

Fig. 2: Architecture of the encoder for the (8281,8201,11) nonlinear 5-error-correcting code.in Fig. 2. The same structure (top half) is used to compute the 10-bit nonlinear redundant bits. The main difference be-tween the two encoders is as follows. First, the encoder for the (8280,8200,11) code does not require a separate port for . All information bits are input via in 820 clock cycles, assuming a parallelism level of 10. Second, the encoding of the (8280,8200,11) code needs one more clock cycle to complete compared to the (8281,8201,11) code. At the 821th clock cycle, the input to (Fig. 2) is switched to the already-generated nonlinear check bits using a 10-bit 2:1 multiplexer.The former, however, requires that all operations are performed in

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B. D The deco mai poly the erro and corr is a Hen be thro cloc fo need erro algo stud min gen need of th per co con arch erro Decoder Ar e decoding oding of a inly contain ynomial gen BCH codes or magnitud then prese recting code 1) Syndrom narrow-sen . For a , where nce only odd

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112 shif deta poly poly Forn is th sum com deco simi be c Firs synd reco line the mis F sligh exam bit e 167 and BCH 28 ft operation ail of the arc

4) Error M ynomial , ynomial where ney’s algori he derivativ m of the ter mpu-tation o 5) Decoder oder for th ilar to the d completed b st, the non drome (s ompute a ear codes is decoder of correction o Fig. 3: Synd The decode htly more c mple, the de error correc 5 clock cyc the syn-dr H code, th s resulting chitecture, p Magnitude the Berleka defined b ithm , the er ve of an rms with od of . r Architectu he nonlinear decoders for by the stand nlinear mult ee Algo-rith after correct completed the nonline of errors can drome comp er for the no complicated e-tailed arch cting code i cles assumin rome of the he decoding in much lo please refer Computati amp-Massey by rror magnitu nd is an in dd degrees

ure for the

r multi-erro r BCH code dard BCH or ti-error cor hm 1) when ting errors l and is re ear code to v n be prevent putation bloc onlinear mu d than the d hitecture of is shown in ng a par-all e BCH code g procedure ower hard-w to . ion for RS y algorithm is the ude at posit nteger. It is in an Nonlinear or cor-rectin s and RS co r RS decode rrecting cod n receiving located by ecom-puted, verify the er ted. ck with a pa ulti-error co de-coder fo f the decode n Fig. 5. Th lelism level e are compu e will be c E. Ramakr ware compl S Codes: B can also ge syndrome tion can be easy to ver nd can be d Multi-Erro ng codes p odes. In fact er. The mai des need t the possibl . Second, , one more rror correcti arallelism le orrecting cod or codes ba er for the (8 he whole de l of 10. Dur uted. If no completed rishna Naik exity (see F Besides the enerate the e polynomial e computed rify that directly deri or Cor-recti presented in t, most of th in dif-ferenc to compute ly distorted , after the d clock cycle ing results s evel of q for des based o ased on The 281,8201,1 ecoding pro ring the firs errors are at the 828t & L.S. Dev Fig. 4). For e error loc error magni l. Accordin d as where is simply ived during ing Codes: n Theorem he decoding ce is as follo e the nonli codewords decoding of e is required so that pos-s r BCH code on Theorem eorem 1. A 1) non-linea ocedure requ st 827 cycle detected by th clock cy varaj r the cator itude ng to y the g the The 1 is g can ows. inear and f the d for sible es. m 3 is As an ar 5-uires es, y the ycle.

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Dep ERR no e gen BCH anot sear loca is arch con Star cod regi pending on R will be pu errors occur eration and H code, whi Fig. 4: Stre If errors are ther 20 cloc rch block will exhau ations. If

then the err

shortened B ne hitecture is stant inputs instead of is initial rting from eword) and isters. At ea the value o ulled down rring to the the Chien ich can effe

ength-reduce e detected b ck cycles to ustively tes ror location BCH code is eed to be slightly m s to lized to be the 848th c d the decod ach odd-num of , either by the ERR e informatio search will ectively redu ed Chien se by the BCH generate th st all possi . (8270,8200 s used, only computed modified for o the bottom . and is s clock cycle ded 10-bit mbered clock the first tw R generating on bits of th be incurred uce the aver

arch archite code, the B he error loca ible error Since 0,11) y . The orig r the deco m Galois fi serially upd e, the 10-bi error vecto k cycle, is wo informat g circuit wh he code. Th d only when rage decodin ecture with a Berlekamp-M ator polynom , a ginal streng ding of sh ield multipli dated durin it FIFO out or will b s updated as tion bits wi hich indicate he error loca n errors are ng latency. a parallelism Massey algo mial . Afte gth-reduced hortened BC iers in Fig. 4 ng the Chie tput (po be buffered s follows: ill be flippe es that there ator polyno detected by m level of q orithm will er this the C d Chien se CH codes. 4 are set to en search st ossibly disto d in two 10 ed or e are omial y the q. take Chien earch The be tage. orted 0-bit

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113 sign mak non redu non inve (22) mul Let real 0 Fi At the 167 nificant two ke adjustme Theorem 3 nlinear 5-bit 1. All ope perform 2. The 5-d serial d clock cy with a p 3. One mo the arch block an The error m uce the har nlinear synd erter in )]. In gene ltipliers. Th Given the f lized using s ig. 5: Decod 75 clock c bits are suc ent to these t 3 presented error correc erations of med in digit error c esign can ac ycles to the parallelism l ore block fo hitecture sh nd generate magnitude p rdware ove drome are is req eral, inverte hus a four-st , can b fact that a fo square oper der architect nonlinear 5 ycle, ccessfully c two bits acc d in Sectio cting code a f the decod . correcting c chieve a sim e decoder fo level of 10. or the comp hown in Fig es the final d polynomial i erhead, mul e reused to quired to co ers in Galo tage pipelin be represent our-stage pi rations and

ture for the 5-error-corre and are corrected. A cording to th on V and are dif-feren der for the code does n milar de-cod or the (828 putation of t g. 5. The bl decoded me is generated ltipliers in generate th ompute ois field h ne is added ted as ipeline is im five multipl E. Ramakr proposed (8 ecting code. used to r A 2-bit error he check res the decode nt as follows e 5-digit e not require ding latency 1,8201,11) the error ma lock is conn mory conte d by the Be f he error ma according t have much to reduce t mplemented, lications in rishna Naik 8281,8201,1 . recheck wh r mask will sults. er for the s. error cor-re a par-allel y in terms o 5-bit error agni-tude is nected to th nts. rlekamp-M for the cal agnitude po to Forney’s longer cri the latency , the above . & L.S. Dev 11) hether the m be generate (8281,8201 cting code architectur of the numbe correcting c s integrated he Chien se assey block culation of oly-nomial. algorithm tical path of the inve function ca Again we r varaj most ed to 1,11) are re. A er of code into earch k. To f the One [see than erter. an be reuse

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the multipliers in other blocks for the purpose of reducing the hardware overhead. Since the square operation is simple in , the inverter adds minimal area overhead and has a latency similar to the Galois filed multiplier in our design.

C. Area, Latency, and Power Consumption

The area, latency, and the power consumption for architec-tures based on the six alternatives presented in Section V are shown in Table III. The designs are modelled in Verilog and synthesized in RTL Design Compiler using 45-nm NANGATE library [34]. In practice the logic circuits used in NAND flash memory could be different from those used in standard digital designs. The estimation presented here is only for the purpose of investigating the increase in area, power and latency of archi-tectures based on the proposed nonlinear multi-error correcting codes compared to architectures based on the widely used BCH codes and RS codes.

During the synthesis we fixed the clock rate for the encoder and the decoder and compared the area and the power consump-tion for architectures based on different codes. The encoders work at 1 GHz. The decoders work at a lower frequency— 400 MHz—due to the long critical path in Berlekamp-Massey block [12]. The six alternatives require the similar latency in terms of the number of clock cycles for encoding and decoding. Due to the computation of the error magnitude and the pipeline for the inverter in the Galois field, digit-error correcting codes (RS, etc.) need eight more clock cycles to complete the decoding compared to bit-error correcting codes (BCH, etc.).

The encoders for the digit-error correcting codes require 40% 50% more area overhead and power than the encoders for bit-error correcting codes (see Figs. 6 and 7) due to the fact that all operations are in . The decoders for digit-error correcting codes, however, require 20% 30% less overhead in area and power because of a much simpler serial architecture.

Compared to BCH codes and RS codes, the proposed non-linear multi-error correcting codes need about 10% 20% more area and power in total for the encoder and the decoder and have the similar latency in terms of the number of clock cycles required to complete the encoding and decoding. The(8281,8201,11) nonlinear 5-bit error correcting codes based on Theorem 3 (columns 6 and 7 in Table III), for example, requires 17.5% more area and consumes 10.0% more power in total for the encoder and the decoder compared to the (8262,8192,11) BCH code.

We note that the encoder and the decoder are only a very small portion in the MLC NAND flash memory chip, where the major portion is the memory cell array. Thereby the increase in area overhead for the encoder and the decoder is not significant for the reliable memory design.

5. Implementation and Results

The proposed NAND Flash Memories Storage Reliablity Using Nonlinear Multi Error Correction Codes. The code is completely synthesized using Xilinx XST and

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implemented on device family Spatran 3E, device XC3S500E, package FG 320 with speed grade -4.

6. Conclusion

In this paper, the constructions of two nonlinear multi-error correcting codes are proposed. Their error correcting algorithms are presented. The proposed codes have much less undetectable and miscorrected errors than the conventional BCH codes and RS codes.

The designs of reliable MLC NAND flash memories based on the proposed nonlinear multi-error correcting codes are pre-sented. We compare the area, the latency and the power con-sumption of the reliable MLC NAND flash architectures using the proposed nonlinear multi-error correcting codes to architectures based on BCH codes and RS codes. The encoder and the decoder for all the alternatives are modeled in Verilog and synthesized in RTL Design Compiler. The results show that architectures based on nonlinear multi-error correcting codes can have close to zero undetectable and miscorrected errors while consuming less than 20% more area and power consumption than architec-tures based on the BCH codes and the RS codes.

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