Trka 10da14r Datasheet d

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Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

Features

• Digital Signal Processor (DSP) Based with Bel Firmware • Provides Power Up and Power Down Sequencing Logic • Stand Alone or Command Based Feature Set

• Fault Detection and Reporting

• 100-Pin 12mm x 12mm TQFP package

• I2C, SMBus, or PMBus compatible serial interface options

• Configurable through serial interface, Customizable through software • 3V3 logic levels

• Voltage Margining via Closed Loop Trim • Analog Input Monitoring

• Comparator function

• Programmed parameters saved in non-volatile memory • Intelligent configuration capability

• Power-down data log for identifying fault conditions • Boot loader for in-system upgrading

Applications

• Data Storage Servers • Networking

• Telecommunications

Description

This on board power system controller provides a cost effective high performance solution for controlling, monitoring, and sequencing multiple Point of Load (PoL) converters on a system board. The sequencer uses a digital signal processor (DSP) engine and Bel’s firmware to implement a portfolio of board level control features typically required in a multiple voltage configuration. This device can perform active trim control and monitor up to 10 PoL converters and enable and monitor up to 18 digital PoL or VRM converters (some of the enable signals are shared), and monitor two additional analog inputs.

Figure 1 provides a block diagram of the device.

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February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

Digital I/O Control I2C Engine Active Trim Control Sequence Up/Down Control Analog Voltage Monitoring APoL Converters 1 of 10 Enable Trim Vout Vin Monitor

DPoL, VRM, or Other voltages to monitor

I2C Clock

Data

Margin Up/Down, Reset In, Power Good Out, Warning Out,

Reset Out, etc.

Main Engine Power System Controller External Reference PWM Output

APoL Vout Monitors

DPoL or VRM Enables Digital I/Os

Figure 1

Functional Block Diagram

I/O Assignment Summary

I/O Type Quantity Signals

Analog Input 32 Vin, APoLs (10), DPoLs (38), Analog x Monitor, Analog y Monitor, Analog ID

Digital Input 12 Mfg Mode, Board ID (3), Enable, Margin (2), Thermal (2), Resets (2), Alternate Voltage Set-point Control

Digital Output 25 APoL Enables (8), DPoL Enable (11), IO PIF Enable / OVP Trip, Alert/Warning, Power Good, Reset or Comparator Out (3) PWM Trim 10 8 Hardware PWM outputs for APoLs 1-8

2 PWM outputs implemented using timer interrupts for APoLs 9 and 10. External Reference 2 VREF-, VREF+

I2C Communication 2 I2C Data, I2C Clock

Power 14 VDD, VSS, AVDD, AVSS, VCAP/VDDCORE Programming 3 MCLR*, PGD, PGC

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February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

I/O Definitions

Pin Pin Name Signal Description I/O Type or Function 5V Tolerant

1 RG15 DPoL 14 Enable Digital Output Y

2 VDD 3V3 VDD Power

3 AN29 Analog x Monitor Analog Input

4 AN30 Analog y Monitor Analog Input

5 AN31 Analog ID Analog Input

6 AN16 DPoL 6 Monitor Analog Input

10 RG6 Board ID 0 Digital Input Y

13 MCLR* CMD Reset/Vpp Programming Y

14 RG9 Alert/Warning Digital Output Y

15 VSS Logic Ground Power

16 VDD 3V3 VDD Power

17 RA0 Enable/Board Seated Digital Input Y

20 AN5 APoL 5 Monitor Analog Input

25 AN0 Vin Monitor Analog Input

28 VREF- Analog Ground External Reference

29 VREF+ 3V00 External Reference External Reference

30 AVDD Filtered VDD Power

31 AVSS Analog Ground Power

38 RA1 APoL 1 Enable Digital Output Y

39 RF13 Margin Low Digital Input Y

40 RF12 Margin High Digital Input Y

47 RD14 Thermal Trip Digital Input Y

48 RD15 Power Good Digital Output Y

49 RF4 Alternate Voltage Set-point Control Digital Input Y

50 RF5 Manufacturing Mode (Margin Enable) Digital Input Y

51 RF3 DPoL 18 Enable Digital Output Y

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February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

Pin Pin Name Signal Description I/O Type or Function 5V Tolerant

54 RF7 APoL 10 Trim Digital Output Y

55 RF6 APoL 9 Trim Digital Output Y

56 SDA1 I2C Data I2C Communication Y

57 SCL1 I2C Clock I2C Communication Y

61 RA5 APoL 5/6 Enable Digital Output Y

63 RC12 Reset B / Analog Y Comparator Out Digital Output

64 RC15 Reset C Out Digital Output

66 RA14 Reset In Digital Input Y

67 RA15 Reset A Out Digital Output Y

68 RD8 APoL 10 Enable Digital Output Y

69 RD9 DPoL 1-4 Enable Digital Output Y

70 RD10 DPoL 5/9 Enable Digital Output Y

72 OC1 APoL 1 Trim PWM Trim Y

73 PGD2 Program Data Programming

74 PGC2 Program Clock Programming

80 RD13 IO PIF Enable / OVP Trip Digital Output Y

85 VCAP/VDDCORE Core Decoupling Capacitor Power

89 RG1 APoL 7/8 Enable Digital Output Y

90 RG0 APoL 9 Enable Digital Output Y

95 RG14 DPoL 13 Enable Digital Output Y

96 RG12 VR Hot Digital Input Y

97 RG13 DPoL 8/12 Enable Digital Output Y

The voltage on 5V tolerant digital input pins can exceed VDD as indicated in the Absolute Maximum Ratings section. 5V tolerant digital output pins can be configured with the open-drain feature which allows the generation of outputs higher than VDD by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification defined in the Electrical Specifications.

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February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

Signal Definitions

Signal Type Definition

VDD Power Positive supply (3.3V) for peripheral logic and I/O pins. See Powering the Sequencer below.

VSS Power Ground reference for logic and I/O pins. See Powering the Sequencer below.

AVDD Power Positive supply (filtered VDD) for analog modules. See Powering the Sequencer below.

AVSS Power Analog ground reference. See Powering the Sequencer below.

VCAP/VDDCORE Power Core decoupling capacitor. See Powering the Sequencer below.

MCLR* Programming Master Clear (Reset) input. This pin is an active-low Reset to the device.

PGD Programming Data I/O pin for programming communication. PGC Programming Clock input pin for programming communication. I2C Clock I2C Synchronous serial clock input/output for I2C

communication. Since this is a slave device, the master drives the clock. Clock stretching may occur if necessary according to the I2C specification.

I2C Data I2C Synchronous serial bi-directional data line for I2C communication.

VREF+ External Reference Analog voltage reference (high) input. VREF- External Reference Analog voltage reference (low) input. Alternate Voltage Set-point

Control Digital Input When asserted the alternate voltage limits will be used for converters configured for dual set-points. Any analog POL converters configured for dual set-points will be trimmed to the alternate set-point.

When de-asserted the normal voltage set-points and limits will be used.

Board ID (0-2) Digital Input These three digital inputs along with the Analog Board ID define a board identification number for controlling which board specific configuration data is loaded.

Enable/Board Seated Digital Input When asserted the board is sequenced up if the input voltage is valid. When de-asserted the board is sequenced down. This function can be overridden as defined in the separate interface document.

Manufacturing Mode Digital Input Enable signal for the hardware margin signals. When asserted the margin high/low inputs will cause the analog PoLs to be margined to their configured high/low margin values.

Margin High Digital Input See Manufacturing mode above. Margin Low Digital Input See Manufacturing mode above.

Reset In Digital Input When asserted, causes Reset A-C to assert.

Thermal Trip Digital Input When asserted, the configured thermal trip action occurs. VR Hot Digital Input When asserted, the configured VR Hot action occurs. IO PIF Enable / OVP Trip Digital Output If this pin is configured as the IO PIF Enable, it is the enable

signal for the IO PIF circuit. Asserted during sequence up and de-asserted during sequence down. If an OVP fault is detected (any monitored output voltage is greater than the power good upper limit), the IO PIF Enable is de-asserted first at power down. If no OVP fault occurs, the IO PIF Enable is de-asserted last at power down.

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Bel Power Inc., a subsidiary of Bel Fuse Inc.

If this pin is configured as OVP Trip, it is asserted when an OVP fault is detected (any monitored output voltage is greater than the power good upper limit).

APoL Enables (8) Digital Output Enable signal for the 10 analog PoL converters. Note that some of the enables are shared. Asserted during sequence up and de-asserted during sequence down.

Alert/Warning Digital Output If this pin is configured for the Alert function, then this output is asserted when an I2C error occurs.

If this pin is configured for the Warning function, then this output is asserted when any of the monitored output

voltages are less than their configured warning lower limit or greater than their configured warning upper limit.

DPoL Enable (11) Digital Output Enable signal for the 18 digital PoL or VRM converters. Note that some of the enables are shared. Asserted during sequence up and de-asserted during sequence down. If the corresponding analog input is configured as a comparator then this enable signal is used as the comparator output instead of enabling/disabling the converter during sequence up/down.

Power Good Digital Output Asserted after the configured power good delay after all of the outputs have been sequenced up and are operating within their configured power good limits. De-asserted prior to sequencing down due to a fault or commanded to do so. Reset Out (A-C) Digital Output Asserted when Reset In is asserted. De-asserted when any

outputs in configured reset masks are outside of power good limits. Reset outputs can also be controlled by PMBus commands.

Analog Y Comparator Output Digital Output If pin 63 (RC12) is configured for Analog Y Comparator then this signal is the output of the Analog Y Comparator

function.

APoL Trim (1-10) PWM Output PWM outputs for actively trimming the analog PoLs to their desired set points. See Using the PWM Trim Outputs below.

The trim PWMs for APoLs 1-8 are hardware based. The PWM output duty cycle will remain fixed even when the controller is performing long operations (such as flash memory erases and writes).

The PWM outputs for APoLs 9 and 10 are implemented using timers. The PWM output is suspended during long operations (such as flash memory erases and writes). During these intervals the output is tri-stated, so the trim circuit should have a pull-up to set the trim voltage to as close to the desired voltage as possible to reduce glitches on the PoL output.

APoL Monitor (1-10) Analog Input Analog PoL output voltage monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage). Analog Board ID Analog Input See Board ID above.

Analog X Monitor Analog Input Analog X monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage). Analog Y Monitor Analog Input Analog Y monitor (must be scaled using attenuating

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February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

resistors if voltage exceeds reference voltage).

DPoL Monitor (1-18) Analog Input Digital PoL, VRM, or other voltage monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage).

Vin Monitor Analog Input System input voltage monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage).

Powering the Sequencer

Microchip P/N MCP1702T-3302I/MB or Equivalent 3V3 Output LDO D1 BAT54 C1 1000uF 25V C2 1uF 16v X5R C4 1uF 16v X5R C5 1uF 16v X5R C6 1uF 16v X5R C7 1uF 16v X5R C3 2.2 uF 10v X5R R2 4.64 Ohm R3 1 Ohm R1 20 Ohm 1206 +12Vin +12V_in Return V_DD VSS AV_DD AV_SS In Out GND VDD Core C8 2.2 uF 10v X5R

Figure 2

V

DD

Interface

Figure 2 is a schematic of the typical VDD interface to the sequencer IC. A Microchip LDO, P/N

MCP1702T-3302I/MB, is used to produce the 3.3V VDD supply to the DSP. This device is in a SOT89 package and in most

applications will be sufficient in size to handle the power dissipation when powering the circuit from a 12V source. Capacitors C4, C5, C6, and C7 are the decoupling capacitors for the DSP and they should be located directly across each pair of VDD and VSS pins on the DSP IC. The device has a VDD core pin which is used to

decouple the internally generated core voltage. Capacitor C8 is the decoupling capacitor for the VDD core. This decoupling capacitor should be a low ESR ceramic capacitor and can be as large as 10uF. Capacitor C3 is the decoupling capacitor for the analog VDD (AVDD) and it should be located directly across the AVDD and AVSS

pins on the DSP IC. Resistor R2 in combination with C3 provides a filter for the analog VDD. Resistor R3 is

intended to separate AVSS from VSS. Capacitor C2 is the input decoupling capacitor for the LDO and it should

be connected directly across the LDO’s input and ground pins. Capacitor C1 is used as a hold up capacitor. Its purpose is to hold up the supply voltage to the LDO and maintain a stable VDD for the DSP for a short period

after the +12Vin source is removed. This would be desired if a short communication stream is required during

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February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

prevents C1 from being discharged after +12Vin is removed. Resistor R1 is used to protect D1 during the inrush

event associated with the application of the +12Vin. The single pulse peak current rating for a typical BAT54

diode is approximately 600mA. If the rise time of the +12V source is slow enough to limit the peak charging current into C1 it is possible to eliminate R1. Assuming a 40mA current draw by the DSP C1 will provide approximately 188 us of hold up time per uF of capacitance.

Using the PWM Trim Outputs

Reference Ry Rz +Sense Rx TRIM PWM +V_in +Vout Zf Zi -+ E/A

Figure 3A.

Reference +Sense PWM +Vin +Vout Zf Zi -+ E/A Rx TRIM Ry

Figure 3B.

+Sense PWM +V_in +Vout Z_f Z_i -+ E/A TRIM uController or Equivalent Reference

Figure 3C.

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February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

The drawings in figure 3 show the three most common trim methods used in PoL converters. In all of these schemes a power conversion stage contains a PWM device that receives a control voltage from an error amplifier. The error amplifier (E/A) compares a scaled version of the output voltage to a reference. The output voltage of the converter module is simply the reciprocal of the scaling factor multiplied by the reference value. The output voltage can be adjusted by changing this scaling factor (Figure 3A) or by modifying the reference (Figures 3B, C).

The most common trim method is shown in figure 3A. The popularity of this method stems from the fact that most highly integrated PWM control IC’s have an internal reference that is not accessible and cannot be controlled externally. In this scheme the output is scaled by adding a resistor from the trim pin to ground. This modifies the feedback divider and moves the output voltage to a higher value. The output can also be modified by superimposing an offset voltage on the feedback divider by connecting a voltage source to the trim pin through a resistor. Either of these two approaches will move the output voltage to a new value. The common characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a higher output voltage or a larger voltage superimposed on the trim pin will cause Vout to decrease.

Some PoL converters incorporate the trim scheme shown in figure 3B. With this method the feedback ratio is kept constant and the reference value is modified to move the output voltage. The common characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a lower output voltage and a larger voltage superimposed on the trim pin will cause Vout to increase.

The method shown in figure 3C is occasionally used. This is similar to the method in figure 3B except the modification of the reference is mapped through a device such as a microcontroller. This is the least common of the 3 methods and requires the vendor’s data sheet to determine the trim characteristic because the micro controller can map the reference in many different ways.

R_a

C_a R_b

Margin PWM PoL Trim Pin

3V3 0 V_Trim Average V_Trim Ripple Figure 4A R_a C_a R_b

Margin PWM PoL Trim Pin

3V3 0 VTrim Average V_Trim Ripple PoL Vout or V_DD Figure 4B

The power sequencer has the ability to do independent closed loop trim and closed loop margining of the output voltage for each PoL controlled by the device. Each PoL’s output voltage is monitored and by an analog to digital converter (ADC) in a continuous loop. In firmware the most recent measured output voltage is compared against the desired value and the PoL’s output is adjusted by delivering a trim value to the corresponding PoL’s trim pin. This trim voltage is created from a digital PWM output and an external low pass filter. Each digital PWM is labeled <PoL “n” Margin PWM> where n indicates a specific converter which corresponds to the monitoring channel labeled with the same “n” value. The external low pass filter creates a DC value from the PWM signal which is then delivered to each PoL converter through a range limiting resistor.

Figure 4 shows the typical circuits used to interface the sequencers Margin PWM signals to PoL converters. In each of the circuits shown Ra and Ca construct a low pass filter while Rb is used to limit the trim range. The

effective trim voltage is equal to the Margin PWM duty cycle multiplied by VDD and is controllable in 1024 steps

from 0 to VDD. The effective trim resistor value is equal to Ra + Rb. Ra and Ca are chosen to reduce the trim

voltage ripple. Typical values for Ra and Ca are 1K for Ra and 0.22uF to 1uF for Ca. Rb is used to limit the

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Bel Power Inc., a subsidiary of Bel Fuse Inc.

This trim equation is usually available from the PoL manufactures data sheet. The sequencer learns the trim direction by making a minor adjustment to the Margin PWM and then determining the direction that Vout moves

based on this stimulus. Once the trim direction is known it knows whether increment or decrement the TRIM PWM value until the desired Vout is achieved. The accuracy of the active trim is a function of the ADC accuracy

which is mostly controlled by accuracy of the applied reference to the sequencers Vref pins.

Either circuit in Figure 4 will work with any of the trim methods shown in Figure 3. When interfacing to PoL modules that use the trim method in Figure 3A the circuit in Figure 4B is the optimum interface configuration. By connecting the filter capacitor Ca to the PoL’s Vout or to a positive voltage reference the effective of filtering the Margin PWM signal remains intact. With this method there will not be a discharged capacitor connected to ground that could cause the PoL’s output to overshoot during power up as this capacitor becomes charged. In the case that the circuit in figure 4A is used with the trim configuration in Figure 3B the sequencer will pre-charge the capacitor before enabling the PoL converter and then decrement the Margin PWM to achieve the desired Vout. This requires additional start up time during system initialization. When interfacing to PoL

converters of the type shown in Figure 3B the interface circuit in figure 4A is optimum.

Monitoring Via ADC Channels

The imbedded ADC channels are converted as 10 or 12 bit results with full scale equal to a chosen reference. The device is intended to be powered from a 3V3 source and can be configured to use this source as the ADC reference or to use an externally provided reference. Closed loop margining and set point adjustments always use the entire 10 or 12 bit result to trim the output voltages to specified values. Monitored voltages are reported via I2C communication using PMBus data formats as defined in the separate communication manual. The voltage range reported is determined by the entered set points. Any monitored output that is greater than the ADC reference or that can be margined above this reference should have a voltage divider to limit the maximum input to the corresponding ADC channel to a value equal or less than the ADC reference. Monitored voltages below the chosen ADC reference do not require this voltage divider. A four sample moving average is used to filter the ADC results. In most cases this will eliminate the need for external filtering.

The input voltage (Vin) monitoring channel requires a voltage divider so that Vin maximum is scaled to a value

less than the maximum value of the ADC reference.

Connecting the Control and Monitor Signals

The three primary control interface signals to the attached PoL converters are an enable signal, a voltage monitoring signal, and trim control signal. The enable signals are labeled <APoL x Enable>. The Monitoring signals are labeled <APoL x Monitor>. The trim signals are labeled <APoL x Trim>. Each APoL converter is required to share the corresponding enable, monitor, and trim signals. The installed firmware assumes that the connections are made this way when controlling system.

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Bel Power Inc., a subsidiary of Bel Fuse Inc.

Communication with the Device

Serial communication is achieved via an I2C bus. The communication protocol is derived from the PMBus command set and is defined in a separate communications manual. The communications manual (TRKA-10DA14R Protocol) also defines the protocol for device programming via embedded boot loader software. The parameters and voltage readings for each PoL converter or analog input can be accessed using PMBus page mode. Figure 5 shows the page assignments.

I2C Engine & Page Switch Page 1-10 APoL1-10 Set Point Control

Scaling Margin Limits PGD/Warning Limits Voltage Reads Page 29-30 Analog x-y Scaling PGD/Warning Limits Voltage Reads Page 0 Not Used Hard Coded I2C Address I2C Bus Page 11-28 DPoL1-18 Scaling PGD/Warning Limits Voltage Reads Figure 5

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Bel Power Inc., a subsidiary of Bel Fuse Inc.

Absolute Maximum Ratings

Ambient temperature under bias ... -40°C to +125°C Storage temperature ... -65°C to +150°C Voltage on VDD with respect to VSS ... -0.3V to +4.0V

Voltage on any pin that is not 5V tolerant with respect to VSS ... -0.3V to (VDD + 0.3V)

Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V... -0.3V to +5.6V

Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V... -0.3V to 3.6V

Voltage on VDDCORE with respect to VSS ... 2.25V to 2.75V Maximum current out of VSS pin ...300 mA Maximum current into VDD pin ... 250 mA Maximum output current sunk by any I/O pin ...4 mA Maximum output current sourced by any I/O pin ...4 mA Maximum current sunk by all ports ...200 mA Maximum current sourced by all ports ...200 mA

Electrical Specifications

Parameter Symbol Min Typ Max Units Notes

Input Voltage Range VDD 3.0 3.30 3.6 VDC

Input Current IDD 46 55 mA Typical is at 3.3V, 25C, 20 MIPS. _{Max is at 3.3V, 85C, 20 MIPS}

Logic Low Input Level VIL VSS 0.2*VDD VDC

VDD Non 5V tolerant pins

Logic High Input Level VIH 0.7*VDD _5.5 VDC _{5V tolerant pins}

Logic Low Output Level VOL 0.4 VDC VDD = 3.3V

Logic High Output Level VOH 2.4 VDC VDD = 3.3V, IOH = -3.0mA

VDD Rise Rate SVDD 0.03 V/mS 0 to 3.0V in 100mS

Capacitance I/O Pin to

GND CIO 50 pF

I2C Bus Capacitance CB 400 pF SCl and SDA

PWM Series Resistor RPWM 1 kΩ External Series Resistor

Margin PWM Frequency FPWM 10 kHz

Reference Input Vref AVSS + 1.7 AVDD VDC

Program Flash Memory

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February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

Mechanical Outline

Bel 100-pin 12x12x1mm TQFP Sequencer Figure 6A

100-Lead Plastic Thin-Quad Flatpack, 12x12x1mm Body

Units Millimeters

Dimension Units Min Nom Max

Number of Leads N 100

Lead Pitch e 0.40 BSC

Leads per side n1 25

Overall Height A - - 1.20

Molded Package Thickness A2 0.95 1.00 1.05

Standoff A1 0.05 - 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0˚ 3.5˚ 7˚ Overall Width E 14.00 BSC Overall Length D 14.00 BSC

Molded Package Width E1 12.00 BSC Molded Package Length D1 12.00 BSC

Lead Thickness c 0.09 - 0.20

Lead Width b 0.13 0.18 0.23

Mold Draft Angle Top α 11˚ 12˚ 13˚

Mold Draft Angle Bottom β 11˚ 12˚ 13˚

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Champers at corners are optional; size may vary.

3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

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CORPORATE FAR EAST EUROPE

Bel Fuse Inc. Bel Fuse Ltd. Bel Fuse Europe Ltd.

206 Van Vorst Street 8F/ 8 Luk Hop Street Preston Technology Management Centre

Jersey City, NJ 07302 San Po Kong Marsh Lane, Suite G7, Preston

Tel 201-432-0463 Kowloon, Hong Kong Lancashire, PR1 8UD, U.K.

February 10, 2014

Bel Power Inc., a subsidiary of Bel Fuse Inc.

Revision History

Date Revision Changes Detail Approval

2012-11-12 A First preliminary draft. S. Moore 2012-11-15 B Added OVP Trip function. S. Moore 2012-12-27 C Added Analog Y Comparator output function. S. Moore 2014-2-10 D Added information about 5V tolerant pins. S. Moore

Errata

Refer to TRKA-10DA14R Errata document for additional information specific to each code release.

RoHS Compliance

Complies with the European Directive 2002/95/EC, calling for the elimination of lead and other hazardous substances from electronic products.