A SIMULATION BASED APPROACH TO
SHOW VARIOUS FACTORS AFFECTING
THE GIDL IN MATLAB
DEBASIS MUKHERJEE E&CE, SPSU and USIT, GGSIPU, Udaipur, 313601 and Delhi, 110006; India
PIYUSH KUMAR TRIPATHI VLSI Design, CDAC Noida,
Noida, 201307, India B.V.R. REDDY USIT, GGSIPU, Kashmere Gate,
Delhi, 110006. Abstract:
As low-power design has become a concern in digital VLSI design, especially for portable and high performance. S o l e a k a g e c u r r e n t i s o f p r i m e c o n c e r n . WHEN the MOSFET is in off-state, a significant leakage current passing through the drain electrode can be detected at drain voltage much lower than the breakdown voltage. Many researchers have attributed the leakage current to the band-to-band tunneling occurring in the overlap region and named the phenomenon gate-induced drain leakage current(GIDL). This leakage has actually been observed in DRAM trench transistor cells and identified as the dominant leakage mechanism in discharging the storage node. In this paper we have studied different models on GIDL and tried to find out what are the various factors affecting the GIDL.
Keywords: Breakdown voltage; GIDL (Gate Induces drain leakage current); DRAM.
1. Introduction
Control of off state drain leakage (Ioff) is one of the most important issues of today VLSI. For deep submicron region
as effective gate length (Leff) decreases the leakage increases because of the following scaling trends.1).
Sub-threshold leakage (Isub) increases exponentially due to threshold voltage reduction.2).Gate edge direct tunneling
current (IEDT) and gate induced drain leakage (Igidl) increases exponentially due to reduced gate oxide thickness.3).
Bulk band to band tunneling leakage (IB BTBT). Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This sub breakdown leakage can dominate the drain leakage current at zero V, in thin-oxide MOSFET’s. This is called Gate Induced Drain Leakage (GIDL) current.
2. Different models for GIDL
2.1. CHEN model
Source: J. Chen, T. Y. Chen, C. Chen, P. K. KO, and C. Hu, “Sub breakdown drain leakage current in MOSFET,” IEEE Electron Device Lett.,
vol. EDL-8, pp. 515-517, Nov. 1987.
A deep-depletion region is formed in the gate-to-drain overlap region. The energy-band diagram illustrates the band-to-band tunneling process and the flow of carriers. Valence-band electrons tunnel into the conduction band and are collected at the drain. The holes created flow to the substrate. We interpret the sub breakdown current as due to the band to-band tunneling process in the gate-to-drain overlap region as illustrated in Fig. Drain current is due to the tunneling of valence-band electrons into the conduction band. The holes created by the tunneling of electrons flow to the substrate. Note that tunneling is only possible in the presence of a high electric field. The field in silicon at the Si-Si02 interface depends on the doping concentration in the diffusion region and the difference between VD and VG, i.e., VDg. Band-to-band tunneling current density is the highest where the electric field is the largest and the band bending is large than the energy band gap Eg. A simple expression for the surface electric field at the tunneling point in the gate-to-drain overlap region can be obtained as follows:
where Es, is the vertical electric field at silicon surface, 3 is the ratio of silicon permittivity to oxide permittivity, and Tox, is the oxide thickness in the overlap region. A band bending of 1.2 eV is the minimum necessary for band-to-band tunneling to occur. The theory of tunneling current predicts
Where A is a pre exponential constant and B = 21.3 MV/cm with m* = 0.2m0. According to (l), Es is proportional to VDG - 1.2.
2.2. Model of R.Shirota, T.Endoh
Source: R. Shirota et al., “An accurate model of sub breakdown due to band to band tunneling and its application,” in IEDM Tech. Dig., 1988,pp.
26-29
2.2.1. The vertical electric field and the value of vbend
The holes flow into the substrate due to the lateral field in the overlap region. The overlap region forms a deletion layer and the vertical electric field can be expressed in depletion approximation as
Eq. (1) Where
impurity doping concentration in the drain region; dielectric constant of the silicon;
q electron charge;
x coordinate normal to the Si–Si02 interface.
The maximum value of the vertical electric field near the drain-to-gate overlap region is at Si–Si02 interface
Because the surface field is dominant, the x in the equation is equal to the depletion width W, which can be expressed as
Eq. (2) From (13) the vertical field Esi becomes
Eq. (3)
Eq. (4) Where,
Eox electric field across Si02 Tox oxide thickness
Vfb flat band voltage
εox dielectric constant of the oxide so, from (4) we have
Squaring both sides
2.2.2. Sub-breakdown current
The band-to-band tunneling rate, as a function of the electric field in Si, is given by using the two-band theory of KANE as follows:
Where P is the tunneling rate per second per cubic centimeter.
The sub breakdown current Id is obtained by integrating the tunneling rate through the whole depletion layer as
Where the electric field in the depletion layer is given by
Kane's two-band model is valid only when the electric field Esi can be regarded as uniform at least in the range of tunneling path Egap/Esi. In this model, the tunneling current is calculated with the tunneling probability P( Esi) only using the local Esi, regardless of the field uniformity. However, this approximation is valid when the electric field in Si is strong enough to make band-to-band tunneling occur. The electric field and the width of the depletion region depend strongly on the distribution of the impurity density as well as on the drain voltage and the oxide thickness. Thus, the distribution of the impurity density and oxide thickness must be taken into account in order to calculate the
0 5 10 15
0 2 4 6 8 10 12
vdg in volts
V
bend i
n v
ol
ts tox=25*10(-9);
vfb=-.55;
q=1.6*10(-19);
nd=8*1022;
subbreakdown current.. As a result, the subbreakdown current can be calculated by this model without using any fitting parameters.
2.2.3. Calculation of subbreakdown current
Source: R. Shirota et al., “An accurate model of sub breakdown due to band to band tunneling and its application,” in IEDM Tech. Dig., 1988,pp. 26-29.
The drain impurity distribution is given as above. Fig shows the drain impurity distribution No(XO, Yo, Z). The point (Xo, Yo) is the center of the drain-to-gate overlap region. The depth where the impurity distribution NO(X, Y, Z) is nearly uniform is about200 to 300 A. On the other hand, the width of the deep depletion layer where band-to-band tunneling occurred is only about 100 to 200 A. Therefore, the value of No(X,Y, Z ) can be regarded approximately as that of the surface impurity distribution N,(X, Y) at the Si-Si02 interface. Thus, only the N, (X, Y) distribution is considered in this model.
2.3. A Bouhdada, S Bakkali model
The current Igidl is considered as one of the important leakage currents at the offstage in a mos transistor .The experimental studies, carried out on the current Igidl ,shows a strong dependence of this current on several parameters.
-4 -3.5 -3 -2.5
10-14 10-13
10-12
10-11
vg in volts
I gi
dl
i
n A
tox=25*10(-9)
no=8*10(24)
The leakage current Igidl is described by the following equation
(1)
Where w is the channel width, ∆l is the length of the gate to drain overlap region where the tunneling effect is The band to band tunneling rate is given by
(2) With
and
h is the Plank’s constant divided by 2∏ and mr is the reduced mass of electron given by
Where mc and mv are the electron mass in the valence band and conduction band respectively. These masses are given by
and
With mcx =0.98*mo, mcy = mcz=0.19*mo, mlh=0.16*mo and mhh=0.49*mo
where mo is the rest mass of electron
The silicon energy band gap depends upon the temperature and can be calculated by the following equation
(3) The electric field Esi in the depletion region can be given by the following expression
(4)
Where the expression for the band bending value Vbend is given by
Where Vdg is the potential difference between the drain and gate. Considering the equation (4) and assuming
and
So the
Esi = c1*(1-x*√ c2)
and Using the binomial expression for the second term
we will finally get
So from equation (1) the expression for Igidl can be rewritten as
Let
So
Putting the limits we get
substitute
=1 So now
Implementing exp(-2*x) << exp(-x) so we can make
=0
Since, <<
(we can check it by putting the values)
So putting the above values
Simplifying
C1 can also be shown as C1 = Esi(x=0)
So substituting
2.4. Three –terminal band to band tunneling model on GIDL in MOSFET
The model of J.Chen ignores two physical parameters dependence. The most noticeable parameter is the lateral electrical field near the drain-to-gate overlap region. The other parameter that should be considered is the dependence of the band bending on the drain doping concentration. The model in the work of Endoh only considers the dependence of the band bending on drain doping profile and vertical field near the drain-to-gate overlap region, but it neglects the dependence of the lateral electrical filed. Thus, it is evident that the band-to-band tunneling model for the GIDL current could be improved. In this paper, an analytical three-terminal band-to-band tunneling current model is developed. The model considers the drain doping concentration and the vertical and lateral field in the drain-to-gate overlap region
-4 -3.5 -3 -2.5 -2 -1.5 -1
10-15
10-14 10-13 10-12 10-11 10-10
vg in volt
Ig
id
l in
A
T = 300 k
Na =1.5*10(15)/cm3
Nd =8.0*10(18)/cm3
L= 10(-4) cm
,W=11*10(-4)
Source : J.H. Chen ,S.C.Wong, Y.H.Wang,”An Analytic Three Terminal Band-to-Band Tunneling Model on GIDL in MOSFET” IEEE Transaction on Electron Devices ,Vol 48, pp1400-1404 July 2001
-4 -3.5 -3 -2.5 -2 -1.5 -1
10-14
10-13 10-12 10-11 10-10
10-9
10-8
10-7
GATE VOLTAGE VG(V)
I G
ID
L
(
A
M
P
)
tox=25*10(-9);
vfb=-.55v; me=.2*mo zeeta=3 vd=3v
2.5. Band trap band tunneling model
Various carrier transition processes are illustrated in Fig.
Ge(= Ra - Rb) and Gh(= Rd - R,) stand for the thermionic emission rates for electrons and holes. Te(= Fa - Fb) andTh(= Fd - F,) denote the tunneling rates for electrons and holes.
From the SRH theory Ge and Gh are expressed as bellow
where Vth is the thermal velocity, ni is the intrinsic carrier density,
ft is the electron occupation factor of interface traps, Ei is an intrinsic Fermi level,
Et is the trap energy,
σn and σp are the capture cross-sections of electrons and holes, and n,and p, are the electron and hole densities at the interface.
The tunneling rates Te and Th for electrons and holes are shown below,
Where τe, and τh are time constants for electron tunneling and hole tunneling. fc and (1 - fv) are electron and hole occupation factors in the conduction band and in the valence band, respectively. According to the Fermi-Golden rule, the dependence of τe, and τh on electric field at trap level Et is obtained.
Τov and τoc are effective transit times in the valence bandand in the conduction band. Here a constant electric field is assumed in tunneling. It should be emphasized again that only the lateral field F1 is involved in the expression of
τh while a total field F is used in τe. For FI < F, the lateral field plays a more important role in the interface
trap-assisted tunneling process. In a steady state, the total hole emission rate is equal to the total electron emission rate for the number of trapped electrons remains constant.
3. Influence of various factors on GIDL
3.1. Oxide thickness
The curve shows an important increase of leakage current Igidl when the oxide thickness decreases. This is translated by the increase of the electrical field at the surface of overlap region ,which favours the transit of electrons by band to band tunneling.Consequently ,the band to band tunneling rate increases and entails the leakage current Igidl increases For an oxide thickness variation of 8-20 nm ,the current Igidl varies about eight decades for a zero gate bias.The simulation result shows that the oxide thickness reduction influences strongly on the leakage current Igidl variation .So it is important to take into account during the manufacture process of the integrated circuit with the thin gate oxide.
3.2. Impurity density in the gate to drain overlap region
The impurity concentration in the gate to drain overlap region plays an important role in the evolution of the leakage current Igidl. For the impurity density concentration inferior to 10^(18) cm^(-3) ,there is an increase of the current density Jgidl .As the impurity density increases ,the depletion layer width becomes less and electrical field in the depletion layer increases , which favours the carrier’s generation by band to band tunneling effect , and consequently , leakage current density Jgidl increases For the impurity density concentration superior to 10^(18) cm^(-3) ,there is an decrease of the current density Jgidl. When the impurity density is high enough ,the width of the depletion layer where the band to band tunneling occurred ,becomes very small and the current density coud be suppressed .Therefore the carrier’s phenomena decreases .That is explained by decrease of leakage current density In order to suppress the current density below 10^(-12 ) A/um2 in 15 nm thick oxide device ,the impurity density must be higher than 10^(19) /cm3 or lower than 10^(18) /cm3.
0.5 1 1.5 2 2.5 3 3.5 4 4.5
x 10-8 10-35 10-30 10-25 10-20 10-15 10-10 10-5 100
tox in nm
Ig
id
l in
A
T = 300 K NA = 1016 /CM3 ND = 5*10(19) /CM3 L = 10(-4) CM W= 50*10(-4) CM VD = 6 V
VG = OV
VG = -3 V
3.3. Temperature
The gate induced drain leakage current Igidl increases with temperature .this dependence is attributed mainly , to band to band tunneling rate P(Esi) ,which increases with temperature and favours carrier generation .This is translated therefore by an increase of the leakage current Igidl for the higher temperature values.
4. Conclusion
We can reduce the leakage by increasing the oxide thickness tox to reduce the electric field.2)Using LDD (lightly doped drain) structure to reduce the electric field near the drain side.3)Decrease the trap density.4)Increase the doping concentration of the drain to decrease the depletion layer width. The electric field exist inside drain and gate overlap region is assumed to be constant by many researchers, but actually there exist a space varying electric field which has to be taken into account for accurate modeling.The drain doping concentration is assumed to be constant but actually there exist Gaussian distribution of impurities inside drain.
References
[1] J. Chen, T. Y. Chen, C. Chen, P. K. KO, and C. Hu, “Sub breakdown drain leakage current in MOSFET,” IEEE Electron Device Lett., vol. EDL-8, pp. 515-517, Nov. 1987.
[2] T. Y. Chan, J. Chen, P. K. KO, and C. Hu, “The impact of gate induced drain leakage current on MOSFET scaling,” in IEDM Tech.Dig.,
1987, pp. 718-721.
[3] R. Shirota et al., “An accurate model of sub breakdown due to band to band tunneling and its application,” in IEDM Tech. Dig., 1988,pp.
26-29
[4] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. John Willy &sons
[5] Y.S.Lin, C.C.Wu, C.S.Chang ,“Leakage Scaling in Deep Submicron CMOS for SOC” IEEE Transaction on Electron Devices ,Vol 49, pp1034-1040 June 2002
1017 1018 1019 1020 10-12 10-11 10-10 10-9 10-8
IMPURITY DENSITY NA /CM(-3)
I G ID L ( A M P )
T = 300 K TOX = 15 NM NA =10(16)/CM3 L= 10(-4) CM W = 50* 10(-4)CM VDG =5 V
VDG = 4 V
0 50 100 150 200 250 300
0.6 0.8 1 1.2 1.4 1.6 1.8 2x 10
-11
Temperature T ( K)
lea k a ge c u rr en t I gi dl
[6] J.H. Chen, S.C.Wong, Y.H.Wang,”An Analytic Three Terminal Band-to-Band Tunneling Model on GIDL in MOSFET” IEEE Transaction on Electron Devices, Vol 48, pp1400-1404 July 2001
[7] S.H.Kim ,S.E.Kim,J.H.Park,” An Analytic Model for a GIDL in a Buried Channel PMOSFET ”Journal of Korean Physical Society ,Vol 43, pp863-867 November 2003
[8] E.O.Kane ,”Zener Tunneling in semiconductors” J.Phys.Chem.Solids Pergamon Press 1959, Vol 12. Pp 181-189
[9]A. Bouhdada, S.Bakkalli ,”MODELING OF GATE INDUCED DRAIN LEAKAGE IN RELATION TO TECHNOLOGICAL PARAMETERS AND TEMPERATURE”
MICROELECTRON PARAGAMON PRESS 1997 ELSEVIER SC.LTD. vol 37 pp 649-652
[10])A.J.Scholten ,G.D.J.Smith,”The Physical Background of JUNCAP 2”, IEEE transactions on Electron devices ,VOL 53,NO 9, Sep 2006 pp 2098-2107
About Authors:
Debasis Mukherjee was born in Bankura, West Bengal, India on August 20, 1980. He is Pursuing Ph.D. from USIT, GGSIPU,
Delhi, India from 2010. He received the M. Tech. degree in VLSI Design from CDAC Noida in 2008 and bachelor degree in Electronics and Instrumentation Engineering from BUIE, Bankura, West Bengal, India in 2003. He achieved first place in district in “Science Talent Search Test” 1991. His father is Sukumar Mukherjee & Mother is Sabita Mukherjee. He has 3 years of Industry experience & 3 years of teaching experience. He has 4 papers in International Journals & 4 papers in International Conferences. He is life time member of ISTE & member of VSI.
Peeyush Kumar Tripathi was born on January 16, 1982. He received the M. Tech. degree in VLSI Design from CDAC Noida
in 2008 and M.Sc. (Electronics) from Avadh University, Faizabad, U.P, India in 2005 and B.Sc. from Avadh University, Faizabad, U.P, India in 2003. He received two Gold Medal award for being top in M. Tech (VLSI Design) in GGSIPU university and M.Sc. (Electronics) in Avadh University.
Dr. B.V. Ramana Reddy is Dean of USIT, GGSIPU, Delhi, India. He obtained his ME and Ph. D (ECE) degrees during
