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3D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model.

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Figure

Figure 2.1 Cross-section of various gate transistor.
Figure 2.2 3D Schematic diagram of VCAT-based DRAM cell [11].
Figure 2.3 DRAM Cell Layout.
Figure 2.5 Recessed gate transistor threshold voltage trend.
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