• No results found

Evaluation of Power Delay Product for Low Power Full Adder Circuits based on GDI Logic Cell using Mentor Graphics

N/A
N/A
Protected

Academic year: 2020

Share "Evaluation of Power Delay Product for Low Power Full Adder Circuits based on GDI Logic Cell using Mentor Graphics"

Copied!
7
0
0

Loading.... (view fulltext now)

Full text

(1)

International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014)

680

Evaluation of Power Delay Product for Low Power Full Adder

Circuits based on GDI Logic Cell using Mentor Graphics

Saravanan R

1

, Kalaiyarasi M

2

, S. Jim Hawkinson

3

, D Sathya

4

1

PG Scholar, 3Assistant Professor, Dept of ECE, Muthayammal Engineering College, Rasipuram, Tamilnadu

2Assistant Professor, Dept of EIE & Bannari Amman Institute of Technology, Sathyamangalam, Tamilnadu, 4Assistant Professor, Dept of ECE, Maha Barathi Engineering College, Kallakurichi, Tamilnadu

Abstract -This paper presents high speed and low power

full adder cells designed with an alternative internal logic structure and Gate Diffusion Input (GDI) logic styles and hybrid CMOS logic style that lead to have a reduced Power Delay Product (PDP). The main design objective for this adder module is not only providing low-power dissipation and high speed but also full-voltage swing. In the first design, hybrid logic style is employed. The second design is based on a different new approach which eliminates the need of XOR/XNOR gates for designing full adder cell and also by utilizing GDI, technique in its structure, it provides Ultra Low-Power and high speed digital component as well as a full voltage swing circuit. The work carried out makes a comparison against other full adders reported for low PDP in terms of speed and power consumption. All the full adders were designed with 180nm technology, and were tested using a comprehensive test bench that allowed measuring the current taken from the full adder in-outs, besides the current provided from the power supply. Post layout simulations are expected to show that the full adder’s output from its counterpart’s exhibiting an average PDP advantage of close to 80%.

Key words-- GDI, PDP, Full adder, Low power and Mentor

graphics

I. INTRODUCTION

Addition is one of the fundamental arithmetic operations. It is used extensively in many Very Large Scale Integration (VLSI) systems such application specific digital signal processing architectures, microprocessors, etc. In most of these systems the adder lies in the critical path that determines the overall system performance. Since adder cells are normally cascaded to form useful arithmetic circuits, their drivability must be ensured.

The driving cell must provide not only full-swing voltage outputs but also sufficient current to the driven cell. Otherwise the performance of the circuit will be degraded dramatically or no operative under low supply voltage. The logic style used in logic gates basically influences the speed, size, power dissipation, and the wiring complexity of a circuit.

The circuit delay is determined by the number of inversion levels, the number of transistors in series, transistor sizes (i.e., channel widths), and intra and inter cell wiring capacitances.

Circuit size depends on the number of transistors and their sizes and on the wiring complexity. Energy efficiency is one of the most required features for modern electronic systems designed for high-performance and/or portable applications.

II. EXISTING METHODS

With the intensified research in low power, high speed embedded systems such as mobiles, laptops, etc has led the VLSI technology to scale down to nano regimes, allowing more functionality to be integrated on a single chip.

(2)

International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014)

681 Several different static CMOS logic styles have been proposed to implement Low-Power adder cells [7,8]. Generally they are divided into two main categories: classical designs which use only one logic style for the whole full adder design and the hybrid CMOS logic styles that use more than one logic style in their structure. Conventional CMOS (C-CMOS) full adder [8–11] is an example of classical approach. This full adder is based on the regular CMOS structure with PMOS pull-up and NMOS pull-down transistors.

One of its merits is its robust structure against voltage scaling and transistor sizing. This circuit provides full-swing which is essential when utilized in a more complex structure. The layout of the C-CMOS full adder is simple, symmetric and efficient due to the complementary transistor pairs however due to employing number of large PMOS transistors in its structure, the input capacitance is large and also the existence of sized up PMOS transistors has a direct impact on its area.

The Complementary Pass transistor Logic (CPL) [8, 9, 11, 12] full adder with swing restoration is another classical circuit. It has a dual-rail structure with 32 transistors. It provides high-speed, full swing output and good driving capability due to the output static inverters and the fast differential stage of cross coupled PMOS transistors. The main drawback of CPL is large power consumption due to existence of a number of internal nodes and static inverters which are the primary source of the leakage and static power dissipation.

The other two full adder designs contain Transmission Function full Adder (TFA) [8, 9, 13] and Transmission Gate full Adder (TGA) [13, 14, 20]. These designs are based on transmission function theory and transmission gates. Transmission Gate (TG) [14, 15] consists of a PMOS transistor and an NMOS transistor that are connected in parallel which is a particular type of pass-transistor logic circuit. There is no voltage drop problem but it requires double the number of transistors to design a similar function. TFA and TGA are low power consuming and they are suitable for designing XOR or XNOR gates [8, 9, 10, 16]. The main disadvantage of these logic styles is that they lack driving capability. When TGA or TFA are cascaded, their performance degrades significantly. Hence, in order to improve its weak driving capability additional buffers are needed. These additional buffers increase the power consumption and chip area.

III. METHODS FOR ANALYSIS

The main objective of this paper is to analyze a full adder with full voltage swing and reduced power and delay.

A.New hybrid full adder

In this section a novel Low-Power full adder, which has good characteristic in terms of speed and power is introduced. Our design is based on SEMI XOR-XNOR gates (Lack of ability to generate all of the possible outputs in conventional XOR-XNOR gates). XOR-XNOR gates have been employed, however in this paper a new Cout circuit structure is shown, which results in having a modular, flexible, robust and low power circuit.

Fig.1 Schematic of SEMI XOR and SEMI XNOR

The SEMI XOR gate has the ability to generate the first four states of the sum output, with the remaining states produced with the SEMI XNOR gate shown in Fig 1.

In order to design the Sum circuit, these SEMI XOR- XNOR gates could be employed with Cin input used as a selector. When Cin is equal to ‘0’, the SEMI XOR gate is similar to the Sum, and when Cin is equal to ‘1’, the SEMI XNOR gate is more like the remaining states of the SUM. Hence the structure of circuit is illustrated in Fig. 2. As mentioned before, SEMI XOR and SEMI XNOR circuit cannot generate all the possible outputs of the Sum and the depicted high impedance states would cause a malfunction in the circuit. One of these two situations occurs when ‘A’ and ‘B’ inputs are equal to ‘1’ and Cin input is ‘0’.

In order to have the correct value at the output node, one more transistor have added to compensate for the in ability of the presented circuit in this specific state.

(3)

International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014)

[image:3.612.59.280.131.393.2]

682 Fig. 2 Circuit structure for new hybrid full adder

As it is apparent, this novel hybrid adder cell minimizes the static power consumption by eliminating any possible direct path between Vdd and the ground due to the use of NMOSs and PMOSs in a complementary manner.

By utilizing this technique, when each part of the circuit is in the conducting mode, the other part is in the off situation, so there is no short-circuit current. The truth table of Sum and Cout with SEMI-XOR and SEMI-XNOR is shown in Table I.

Table I

Truth Table Of Sum And Cout With Semi-Xor And Semi-Xnor

Cin B A SUM Cout SEMI-XOR SEMI-XNOR

0 0 0 0 0 0 -

0 0 1 1 0 1 0

0 1 0 1 0 1 0

0 1 1 0 1 - 1

1 0 0 1 0 0 -

1 0 1 0 1 1 0

1 1 0 0 1 1 0

1 1 1 1 1 - 1

Moreover, by utilizing ULPD level restorer not only the leakage current is eliminated but also this capable device provides good driving capability which is essential when this circuit is used in a cascaded or a more complex situation.

Using ULPD as level restorer eliminates the need of output buffers which are the main source of static power consumption. This design uses 20 transistors and because of its low transistor count in comparison with its counter- parts, our hybrid design has low dynamic power dissipation due to its low switching capacitance. In terms of the speed, this circuit is superior to the previously reported full adder cells.

B.GDI-MUX full adder

[image:3.612.373.516.510.621.2]

In this section a new approach for designing full adder cell eliminating the need for complicated XOR-XNOR gates is introduced. In the second step the implementation of this ULPD circuit using GDI technique is discussed. By considering the full adder’s Truth-Table it can be seen that Cout is equal to (A AND B) when Cin ¼ ‘0’, and Cout is equal to (A OR B) when Cin ¼‘1’. Thus, a multiplexer can be used to obtain the Cout output. Following the same criteria, the SUM output is equal to (A OR B OR Cin) when Cout ¼ ‘0’, and SUM is (A AND B AND Cin) when Cout ¼‘1’. Again, Cout can be used to select the respective value for the required condition, driving a multiplexer. Hence, an alternative logic scheme to design a full adder cell can be formed by AND, OR and MUX logic blocks as shown in Fig. In order to have an implementation of this alternative logic scheme, GDI technique issued. The basic schematic of GDI cell is shown in Fig. 3.

Fig. 3 Basic schematic of GDI cell

[image:3.612.64.276.536.674.2]
(4)

International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014)

[image:4.612.64.276.130.369.2]

683 Fig. 4 Circuit structure for GDI-MUX full adder

These features give the GDI cell two extra input pins to use, which makes the GDI design more flexible than usual CMOS design. The GDI scheme requires Silicon On Insulator (SOI) process in order to be implemented. GDI is suitable for designing fast, Low-Power circuits, using a reduced number of transistors (as compared to CMOS and PTL techniques), while improving logic level swing and static power characteristics.

The circuit structure for GDI-MUX full adder is shown in Fig. 4. More over GDI solves the problem of Top-Down design complexity of Pass Transistor Logic which has no simple and universal cell library preventing them from having a major role in real VLS by providing small cell library. In order to implement (A OR B), N input is connected to Vdd, P is connected to B and G is connected to A.

IV. SIMULATION RESULTS AND ANALYSIS

The results are obtained by simulating the implemented circuits in mentor graphics tool at 180nm technology and its power, delay and power-delay product were found. In this section, the two full adder cells shown in Figs. 2 and 4 are evaluated and compared to the ones chosen from the literature. All the circuits are implemented using Mentor Graphics and extracted using 180nm CMOS technology. Simulations are carried out using this tool, with the capacitances extracted from the layout. The full adder cells are simulated with 100 MHz frequency and the supply voltages varying from 0.6 to 1.2 V for 180 nm.

Different loading conditions are also considered to evaluate the performance of the test circuits.

Comparison of full adder cells is discussed below in three subsections referred to Delay, Power and PDP.

A.Delay

The circuit delay is determined by the number of inversion levels, the number of transistors in series, transistor sizes (i.e., channel widths), and intra and inter cell wiring capacitances. Circuit size depends on the number of transistors and their sizes and on the wiring complexity.

The cell delay is defined as the time duration taken from the moment the inputs reach 50% of the voltage supply level (assume that all inputs are coming from registers at the same time), till the time the latest output (S or Cout) reaches the same voltage level (50%). To measure the cell delay, one should consider the previous values of the inputs together with the current values. If the inputs are unchanged, the outputs will not change, and accordingly no delay can be measured.

B.Power

Power is the rate at which energy is delivered or exchanged. In VLSI chips, electrical energy is converted to heat energy during operation. The rate at which energy is drawn from the power supply and converted into heat is the power dissipation. For digital CMOS circuits there are two main sources of power dissipation, dynamic power and static power.

Dynamic power is the power dissipated in the circuit due to the current flowing while charging or discharging the circuit node capacitors during transistor switching. The static power is the power dissipated while the circuit is in steady state.

C. Power Delay Product

(5)

International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014)

[image:5.612.61.278.137.288.2]

684 Fig. 5 Result of hybrid full adder

The new hybrid circuit was drawn and waveforms are obtained. The total power dissipation of this circuit is 66.5pW and delay 180.87fs was obtained from the result.

Fig. 6 Result of GDI-MUX full adder

The GDI-MUX circuit was drawn and waveforms are obtained. The total power dissipation of this circuit is 47.34pW and delay 270.96fs was obtained from the results

D. Power comparison of different applied voltage

Table II

Power Comparison For Different Voltages

POWER

in (pW) 1.8V 1.6V 1.4V 1.2V 1.0V

GDI-MUX 47.34 37.94 29.90 22.64 16.48

NEW

HYBRID 66.50 57.12 49.27 38.39 29.93 ULPFA 172.09 137.14 106.77 80.66 58.64

HYBRID 323.77 256.54 198.57 147.99 106.84

CCMOS 547.06 420.30 315.10 229.10 159.32

CPL 633.90 589.61 446.79 328.54 231.58

[image:5.612.328.559.155.401.2]

E. Delay comparison of different applied voltage

Table III

Delay Comparison For Different Voltages

DELAY 1.8V 1.6V 1.4V 1.2V 1.0V

GDI-MUX 270.96 fS 412.87 fS 530.91 fS 718.16 fS 837.16 fS NEW HYBRID 180.87 fS 250.18 fS 370.87 fS 420.11 fS 530.77 fS

ULPFA 467.09 fS 639.11 fS 818.11 fS 977.87 fS 1.76 pS

HYBRID 780.53 fS 918.16 fS 1.42 pS 33.37 pS 79.87 pS

CCMOS 120.77 pS 149.42 pS 180.71 pS 198.53 pS 215.87 pS

CPL 9.98

nS 47.09 pS 80.77 pS 120.87 pS 150.53 pS

For different input values full adder produced different power and delay value. These values are tabulated above. From the tabulation, the power and delay value should be depending upon the input applied voltages.

F. PDP comparison of different applied voltage

Table IV

Pdp Comparison For Different Voltages

PDP 1.8V 1.6V 1.4V 1.2V 1.0V

GDI-MUX 3.9* 10-23 2.7* 10-23 9.5* 10-24 5.2* 10-24 9.2* 10-25 NEW HYBRID 3.5* 10-23 2.3* 10-23 9.2* 10-24 5.0* 10-24 3.2* 10-23

ULPFA 2.9* 10-22 1.3* 10-22 8.3* 10-23 5.2* 10-23 2.7* 10-23

HYBRID 2.5* 10-20 8.5* 10-21 2.1* 10-22 9.3* 10-22 5.3* 10-22

CCMOS 2.1*

10-20 8.3* 10-20 5.3* 10-21 2.3* 10-22 1.2* 10-22

CPL 1.6*

[image:5.612.63.274.336.495.2] [image:5.612.315.571.492.707.2]
(6)

International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014)

685

[image:6.612.326.562.126.413.2]

G. Power comparison of different bit full adders

Table V

Comparison Of 2, 4, 8, 16 Bit Full Adders

POWER 2 BIT 4BIT 8 BIT 16 BIT

GDI-MUX (pW)

98.35 98.11 201.73 410.77

NEW HYBRID

(pW)

137.44 280.9 408.11 803.83

ULPFA

(pW) 342.97 685.95 462.3 924.78

HYBRID 647.58 PW

1.2 NW

1.3 NW

2.7 NW

CCMOS

(nW) 1.09 2.1 1.8 3.7

CPL (nW) 1.5 3.0 2.8 5.7

This is the tabulation for different bit full adders. The power value should be increased when the number of input bits increases. From the table the number of power value and delay value for different full adders is shown.

H. Comparison of power and delay

Fig. 7 Power Vs Applied voltages for different logics

Fig. 8 Delay Vs Applied voltages for different logics

Fig. 9 Power comparison of 2, 4, 8, 16-bit full adders for different logics

The Fig. 7 and Fig. 8 are drawn from the table 2 and table 3 values. From this bar charts the GDI-MUX full adder contain less power and delay compared with the other full adders were easily obtained.

From the comparison of 1-bit, 4-bit, 8-bit, 16-bit full adder implemented results in above tables and their corresponding bar-charts it is clear that the power, delay and PDP of hybrid and GDI-MUX full adder is better than the C-CMOS, CPL, hybrid and ULPFA.

V. CONCLUSION

[image:6.612.53.285.149.390.2] [image:6.612.51.285.455.638.2]
(7)

International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014)

686 All the results were post layout simulated by 180nm CMOS technology. The adder designs demonstrate less power, delay and power delay product compared to standard designs. The use of the new approach results a competitive technique with respect to full adders and recent researches. This architecture is also easy for pipeline implementation. The number of transistors used is significantly reduced resulting in a great reduction in switching activity and area. This considerable reduction in power by minimizing static and dynamic power dissipation as well as some techniques to enhance the speed of the design leads to the best PDP.

REFERENCES

[1] K. Navi, M.H. Moaiyeri, R. FaghihMirzaee, O. Hashemipour, B.

MazloomNezhad, Two new low-power full adders based on majority-not gates, Microelectronics Journal (Elsevier), 40, 126–130.

[2] M.H. Moaiyeri, R. FaghihMirzaee, K. Navi, T. Nikoubin, O.

Kavehei, Novel direct designs for 3-input XOR function for low power and high-speed applications, International Journal of Electronics (Taylor and Francis) 97 (6) (2010) 647–662.

[3] K. Navi, M. Maeen, V. Foroutan, S. Timarchi, O. Kavehei, A novel

low power full-adder cell for low voltage, Integration the VLSI Journal (Elsevier) 42 (4) (2009) 457–467.

[4] M. Alioto, G. Palumbo, Analysis and comparison of the full adder block, IEEE Transactions on VLSI 10 (6) (2002) 806–823.

[5] R. Shalem, E. John, L.K. John, A novel low-power energy recovery

full adder cell, in: Proceedings of the Great Lakes Symposium on VLSI, February 1999, pp. 380–383.

[6] R.X. Gu, M.-I. Elmasry, Power dissipation analysis and optimization

of deep submicron CMOSdigital circuits, IEEE Journal of Solid-State Circuits 31 (5) (1996) 707–713.

[7] S. Goel, A. Kumar, M.-A. Bayoumi, Design of robust,

energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (12) (2006) 1309–1321.

[8] C.H. Chang, J. Gu, M. Zhang, A review of 0.18 um full-adder

performances for tree structure arithmetic circuits, IEEE Transactions on Very Large Scale Integration(VLSI) Systems 13 (6) (2005).

[9] A.M. Shams, T.K. Darwish, M.A. Bayoumi, Performance analysis of

low-power 1-bit CMOS full adder cells, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 (1) (2002) 20–29. [10] Y. Jiang, A. Al-Sheraidah, Y. Wang, E. Sha, J. Chung, A novel

multiplexer-based low-power full adder, IEEE Transactions on Circuits and Systems II: Express Briefs 51 (7) (2004).

[11] R. Zimmermann, W. Fichtner, Low-power logic styles: CMOS

versus passtransistor logic, IEEE Journal of Solid-State Circuits 32 (1997) 1079–1090.

[12] S. Issam, A. Khater, A. Bellaouar, M.I. Elmasry, Circuit techniques

for CMOS low-power high performance multipliers, IEEE Journal of Solid-State Circuits 31 (1996) 1535–1544.

[13] N. Zhuang, H. Wu, A new design of the CMOS full adder, IIEEE Journal of SolidState Circuits 27 (1992) 840–844.

[14] M.M. Vai, VLSI Design, CRC Press, Boca Raton, FL, 2001.

[15] N. Weste, K. Eshraghian, Principles of CMOS VLSI Design. A

System Perspective, Addison-Wesley, Reading, MA, 1993.

[16] D. Radhakrishnan, Low-voltage low-power CMOS full adder, IEEE

Proceedings in Circuit Devices and Systems 148 (1) (2001) 19–24.

[17] Arkadiy Morgenshtein, A. Fish, Israel A. Wagner, Gate-diffusion

input (GDI): a power-efficient method for digital combinatorial circuits, IEEE Transactions on VLSI Systems (2002) 566–581.

[18] H.T. Bui, A.K. Al-Sheraidah, Y. Wang, New 4-transistor XOR and

XNOR designs, in: Proceedings of the 2nd IEEE Asia Pacific Conference ASICs, 2000, pp. 25–28.

[19] D. Hassoune, I.O Flandre, Connor, J.D. Legat, ULPFA: a new

efficient design of a power-aware full adder, IEEE Transactions on Circuits and Systems—I: Regular Papers 57 (8) (2010).

[20] V. Dessard, SOI Specific Analog Techniques for Low-noise,

High-temperature or Ultra-low Power Circuits, Ph.D. Thesis, UCL, Louvain, Belgium, 2001.

[21] D. Levacq, C. Liber, V. Dessard, D. Flandre, Composite ULP diode

fabrication, modeling and applications in multi-FD SOI CMOS technology, Solid State Electronics 48 (6) (2004) 1017–1025. [22] V. Kilchytska, D. Levacq, L. Vancaillie, D. Flandre, On the great

potential of nondoped MOSFETs for analog applications in partially-depleted SOI CMOS process, Solid State Electronics 49 (5) (2005) 708–715.

[23] J.-M. Wang, S.-C. Fang, W.-S. Feng, New efficient designs for XOR

and XNOR functions on the transistor level, IEEE Journal of Solid-State Circuits 29 (7) (1994) 780–786.

[24] K. Yano, Y. Sasaki, K. Rikino, K. Seki, Top-down pass-transistor logic design, IEEE Journal of Solid-State Circuits 31 (1996) 792– 803.

[25] M. Vesterbacka, A 14-transistor CMOS full-adder with full voltage swing nodes, in: Proceedings of the IEEE Workshop on Signal Processing Systems, October 1999, pp. 713–722.

[26] H.T. Bui, Y. Wang, Y. Jiang, Design and analysis of low-power

10-transistor fulladders using novel XOR–XNOR gates, IEEE Transactions on Circuits and Systems. Part II: Analog and Digital Signal Processing 49 (1) (2002) 25–30.

[27] G.A. Katopis, Delta-I noise specification for a high performance

computing machine, Proceedings of the IEEE 73 (9) (1985) 1405– 1415.

[28] G. Balamurugan, N.R. Shanbhag, The twin-transistor noise-tolerant

dynamic circuit technique, IEEE Journal of Solid-State Circuits 36 (2) (2001) 273–280.

[29] F. Frustaci, P. Corsonello, S. Perri, G. Cocorullo, High-performance

noisetolerant circuit techniques for CMOS dynamic logic, IET Circuits, Devices & Systems 2 (2008) 537–5486 2 (2008) 537–548.

[30] H. Mahmoodu-Meimand, K. Roy, Diode-footed domino: a

leakage-tolerant high fan-in dynamic circuit design style, IEEE Transactions on Very Large Scale Integration Systems 3 (51) (2004) 495–503.

[31] Vahid Foroutan, MohammadReza Taheri, Keivan Navi, Arash Azizi

Figure

Fig. 2 Circuit structure for new hybrid full adder
Fig. 4 Circuit structure for GDI-MUX full adder
Table III Delay Comparison For Different Voltages
Fig. 8 Delay Vs Applied voltages for different logics

References

Related documents

In this paper, the author proposed a new location based energy efficient scheme with AODV (DREAM-EAODV) protocol. In this scheme, energy dependent nodes route the information

Comparative means based on ANOVA test of male captive and wild black- footed ferrets for each of the 23 cranial measurements and PC1-5. Measurement Captive Mean Captive

(COMPUS) program, within the Canadian Agency for Drugs and Technologies in Health (CADTH), and in collaboration with the Cochrane Effective Practice and Organisation of Care

Understanding the knowledge, attitude and practice of EBF and determinants of practice may be a necessary step to help improve infant feeding practices among rural lactating mothers

Mobilized peripheral blood stem cells compared with bone marrow as the stem cell source for unrelated donor allogeneic transplantation with reduced-intensity conditioning in

This survey of 502 physicians from 4 clinical specialties of various ICU practice settings revealed that practice patterns in fluid resuscitation vary broadly with respect

Hindawi Publishing Corporation EURASIP Journal on Wireless Communications and Networking Volume 2006, Article ID 78954, Pages 1?9 DOI 10 1155/WCN/2006/78954 Exploiting Diversity for

Each detected aTID junction is proposed to form by a separate deletion event that removes one symmet- rical junction of the parent sTID, rendering that junction asymmetric (right