JECET; March - May 2013; Vol.2.No.2, 467-476.
Journal of Environmental Science, Computer Science and Engineering & Technology
An International Peer Review E-3 Journal of Sciences and Technology
Available online at www.jecet.org Engineering & Technology
Research Article
JECET; March- May 2013; Vol.2.No.2, 467-476. 467
Comparative Analysis of Leakage current and Ground Bounce Noise using MTCMOS combinational circuit
Garima Mittal 1 and Nidhi Bajpayee 2
Department of Electronics & Communication Engineering, IMS Engineering College, Ghaziabad, Uttar Pradesh, India
Received: 18 May 2013; Revised: 26 May 2013; Accepted: 31 April 2013
Abstract: This research presents the comparison of leakage current of different sizes of transistors and ground bounce noise of different sizes of transistors with the help of MTCMOS (Multi Threshold CMOS). The simulation has carried out on tanner tool using 90nm CMOS technology. The circuit consists of Low Vth block (1 bit full adder) and high Vth block (different combination of NMOS and PMOS transistors). Leakage current and ground bounce noise are evaluated for Tri-mode, Dual switch and Tri- Transistor techniques. The power results are satisfying low power consumption of recent technology. MTCMOS is used to reduce the leakage current. MTCMOS has high threshold voltage and low threshold voltage MOSFET’S on a single LSI.
Keywords: Multi-threshold CMOS, Ground bounce noise, leakage current, sleep to active mode transition, intermediate mode, Low Vth block, High Vth block
INTRODUCTION
For low power design supply voltages and threshold voltages are reduced with advanced CMOS technology. Lowering the threshold voltage introduces the increase in leakage current. Leakage current
JECET; March- May 2013; Vol.2.No.2, 467-476. 468 contributes the part to the total power consumption. For battery operated portable devices such as mobile phones, laptops, computers leakage power has to be reduced to increase the battery life time.
MTCMOS is a technique to reduce the leakage current. This technique disconnects the low Vth block (1 bit full adder) from power supply line and ground line by cutting off high Vth sleep transistors whenever circuit is in idle mode. Leakage current which is produced by MTCMOS circuit is reduced in sleep mode. When leakage current has been reduced then it arises a new problem i.e. Ground bounce noise. Ground Bounce noise is generated during sleep to active mode transition. An intermediate mode is introduced between sleep mode and active mode to reduce the ground bounce noise. MTCMOS technique is a effective way to reduce the leakage current. This technique has low threshold voltage and high threshold voltage MOSFET’S on a single LSI. Low threshold voltage MOSFET’S increases the speed performance at low supply voltage i.e. 1V or less. High threshold voltage MOSFET’S decreases the leakage current during sleep mode. In this paper we evaluate the leakage current and ground bounce for different sizes of transistors and compare them.
MTCMOS CIRCUIT TECHNIQUES
Different MTCMOS circuit techniques for combinational circuit are used to evaluate the leakage
current. In this paper, three techniques have been studied:
(1). Tri-mode technique (2). Dual Switch technique (3). Tri transistor technique
Tri-Mode MTCMOS Technique: A schematic of tri-mode technique is shown in figure 1 & 2. In sleep mode both N1 and parker are turned off. Sleep mode is used to reduce the sub-threshold leakage current of an idle circuit. The voltage of virtual ground line is maintained at VDD during this mode. An additional intermediate park mode is added between sleep and active mode to reduce the ground bounce noise. A parker is a high Vth transistor which is connected parallel with sleep transistor (N1).
Fig.1: Schematic to evaluate leakage current using Tri-mode Technique
JECET; March- May 2013; Vol.2.No.2, 467-476. 469 Fig.2: Schematic to evaluate Ground bounce noise using Tri-mode Technique
(2).Dual Switch MTCMOS Technique: In this technique, a high Vth NMOS transistor N2 is connected in parallel with a header sleep transistor P1between real power supply and virtual power line. Similarly a high Vth PMOS transistor P2 is connected in parallel with a footer sleep transistor N1 between virtual ground line and real ground. During sleep mode P1, N1, P2, and N2 are turned off. It is necessary to reduce the sub-threshold leakage current. The voltages of the virtual power and ground line are approximately equalized (Vmid). In intermediate mode P2 and N2 are turned on. Intermediate mode is HOLD mode. During intermediate mode a differential voltage VDD-Vtn-Vtp is produced between virtual power line and virtual ground line. To complete reactivation of the circuit P1and N1 are activated and P2,
N2 are turned off. The virtual power line is charged to VDD and virtual ground line is discharged toVgnd. The schematic of Dual switch technique is shown in figure 3 & 4.
Fig.3: Schematic to evaluate Leakage current using Dual switch Technique
JECET; March- May 2013; Vol.2.No.2, 467-476. 470 Fig. 4: Schematic to evaluate Ground bounce noise using Dual switch technique
(3).Tri Transistor MTCMOS Technique This is enhanced version of MTCMOS technique to suppress the ground bounce noise. An additional high Vth PMOS called Dozer is connected in parallel with footer sleep transistor in fig .During sleep mode sleep transistors (sleep1, sleep2) and Dozer transistors are cut off to reduce the sub-threshold leakage current. Dozer mode is an intermediate mode.
In Dozer mode header and dozer are turned on and footer is turned off. In active mode header and footer both are turned on. Sleep mode is preferable to minimize the leakage power. Dozer mode is an intermediate mode to reduce the ground bouncing noise. The voltage of the virtual power line and virtual ground line are approximately equalized (Vmid). During sleep mode to dozer mode transition voltage is discharged to Vmid – Vtp high. Again voltage is discharged from Vtp high to Vgnd during transition from Dozer mode to active mode. The schematic of Tri transistor is shown in figure 5 & 6.
Fig. 5: Schematic to evaluate Leakage current using Tri transistor technique
JECET; March- May 2013; Vol.2.No.2, 467-476. 471 Fig. 6: Schematic to evaluate Ground bounce noise using Tri transistor technique
EXPERIMENT RESULTS
A. Leakage Power: Leakage power is reduced during sleep mode. Leakage power has been calculated for three different sizes of transistor shown by graph and tables. The width of the parker in tri-mode, Dozer in tri transistor mode and Hold in dual switch mode are assumed to be varied in this section.
W = 5µm Deep sleep mode
Fig.7: Variation in Leakage power with supply voltage for all three techniques 5µm technology
JECET; March- May 2013; Vol.2.No.2, 467-476. 472 Table-1: Comparison of all MTCMOS technique in sleep mode for 5µm technology
W= .12µm Deep sleep mode
Fig. 8: Variation in Leakage power with supply voltage for all MTCMOS technique in .12 µm technology
S. No. Voltage (V)
Tri-mode (µW)
Dual Switch
(µW) Tri transistor(µW)
1 0.5 16.4475 10.952 8.83
2 0.6 21.5076 14.1684 5.2812
3 0.7 25.0922 18.5031 12.88
4 0.8 29.9424 27.9192 27.888
5 0.9 35.1765 35.1162 35.109
6 1 40.82 40.817 40.81
7 1.1 46.9007 46.9007 46.893
8 1.2 53.4336 53.4336 53.424
9 1.3 60.8985 60.4305 60.424
10 1.4 67.907 67.907 67.9
JECET; March- May 2013; Vol.2.No.2, 467-476. 473 Table- 2: Comparison of all MTCMOS technique in sleep mode for 12µm technology
S. No. Voltage (V)
Tri-mode (µW)
Dual Switch
(µW) Tri transistor(µW)
1 0.5 16.448 10.788 11.228
2 0.6 20.606 14.152 4.405
3 0.7 25.093 17.404 6.268
4 0.8 29.942 20.776 15.587
5 0.9 35.177 27.569 27.364
6 1 40.821 40.638 40.637
7 1.1 46.901 46.889 46.888
8 1.2 53.434 53.434 53.434
W = 15µm Deep sleep mode
Fig.9: Variation in Leakage power with supply voltage for all three techniques 15µm technology
JECET; March- May 2013; Vol.2.No.2, 467-476. 474 Table- 3: Comparison of all MTCMOS technique in sleep mode for 15µm technology
S.
No.
Voltage (V)
Tri-mode (µW)
Dual Switch (µW)
Tri transistor(µW)
1 0.5 16.448 16.447 3.096
2 0.6 20.606 20.605 5.667
3 0.7 25.0928 25.092 38.740
4 0.8 29.943 29.941 29.498
5 0.9 35.177 35.175 35.157
6 1 40.82 40.819 40.819
7 1.1 46.901 46.900 46.902
8 1.2 53.434 53.432 53.434
Leakage power is reduced with decrease in supply voltages as shown by table and graphs. With the increase in size of the transistor leakage power is reduced in tri transistor technique.
(B).Ground Bounce Noise: Ground bounce noise is generated during sleep to active mode transition.
In this section Ground bounce noise is evaluated for all three techniques and compare them.
W=.12µm W=5µm
Fig.10:Ground bounce noise for Fig. 11: Ground bounce noise for
JECET; March- May 2013; Vol.2.No.2, 467-476. 475 all three techniques (.12µm) all three techniques (5µm)
W=15 µm
Fig.12: Ground bounces noise for all three techniques (15µm)
Table- 4: Comparison of Ground Bouncing Noise of all three techniques with different sizes of transistors
Ground bounce noise has been increased with increase of the size of the transistor. Tri-mode MTCMOS technique is the best technique. It has minimum ground bounce noise. Dual switch is the worst technique. It has maximum ground bounce noise.
CONCLUSION
In this paper multi threshold CMOS technique has been proposed to reduce the leakage current as well as it controls the ground bounce noise. Comparison of all three MTCMOS technique has been done for Leakage current shown by figure and tables (7, 8, 9 & 1, 2, 3) .and comparison for ground bounce noise shown by figure and tables (10, 11, 12, & 4). Tri –transistor is the best technique to reduce the leakage current. Leakage current has been decreased with the increase in size of the transistor. To minimize ground bounce noise Tri-mode is the best technique. Ground bounce noise has been increased with the increase in size of the transistor. Leakage power has been increased with increase in supply voltage.
REFERENCES
1. H. Jiao and V. Kurson , Proceedings IEEE Asia Symposium on Quality Electron Design, 2009, 64 2. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, IEEE J. Solid-State Circuits,
1995, 30, 8, 847
Technique Size of the transistor (W)
0.12mµ 5µm 15µm
Tri Mode 88.60µv 968.73µv 2.65mV Dual Switch 97.72µv 1010µv 2.89mV Tri
Transistor
90.41µv 998.59µv 2.69mV
JECET; March- May 2013; Vol.2.No.2, 467-476. 476 3. M. Pattanaik, B. Raj, S. Sharma and A. Kumar, Advanced Materials Research Trans tech Publications,
Switzerland, 2012, 548, 885
4. M. H. Chowdhury, J. Gjanci, and P. Khaled, Proc. IEEE Comput. Soc. Annu. Symp. VLSI, 2008, 437 5. S.G. Narendra and A. Chandrakasan, Springer-verlag, 2006
6. Piguet, C., CRC Press, 2005.
7. S. Sharma, A. Kumar, M. Pattanaik, and B. Raj,” Forward Body biased Multimode Multi threshold technique for Ground bounce noise reduction in static CMOS Adders, 4th international conference on Electronics Computer Technology ICECT 2012.
8. P. Khaled, J. Xu, and M. H. Chowdhury, “Better Leakage Reduction by Exploiting the Built-in MOSFET-Vth Characteristics, IEEE EIT 2007 Proceedings.
*Correspondence Author: Garima Mittal Department of Electronics & Communication Engineering, IMS Engineering College, Ghaziabad, Uttar Pradesh, India