BANG PHASE LOCKED LOOP BACKGROUND OF THE INVENTION. CDR circuits typically use a phase-locked loop (PLL) to determine, from the

AttorneyDocket No. 10031355-1

CONTROLLING A VOLTAGE CONTROLLED OSCILLATOR IN A BANG- BANG PHASE LOCKED LOOP

FIELD OF THE INVENTION

[001]

The

invention_{relates to} phase-lockedloops,

and more

particularly, to controlling the voltage controlled oscillator in a

bang-bang

phase-lockedloop.

BACKGROUND OF THE INVENTION

[002]

Clock and

data recovery

(CDR)

circuitsarewidely used

when

a data signal is sent across a

communications

linkwithout an

accompanying

dedicated clock signal.

CDR

^circuitstypicallyuse a phase-locked loop

(PLL)

todetermine,

from

the transitions

between

physical data values, the exactfrequencyat

which

data isarriving

and

the

optimum

phaseat

which

to

sample

the

incoming

data'

PLLs

typically include a

VCO,

a frequency_detector,

and

a

phase

detector.

The

phasedetectorisusedto determinethe

optimum

phaseat

which

to

sample

the

incoming

data.

Phase

detectors requirethatthe frequency

of

a

VCO be

veryclosetothefrequency

of

the

incoming

signalbefore frequency

and phase

lock can beachieved.

For

example, the

frequencies

of

the

VCO and incoming

signal should be within

0.5% of each

other beforethe

phase

detectoris ableto"pull-in" the

VCO

frequencyto

match

the

incoming

signal.

Frequency

detectors are designedtobring thefrequency

of

the

VCO

towithinthepull-inrange, or

deadband

region, ofthephasedetector.

Frequency

detectors relinquish control

of

the

VCO

signalto thephase detector

once

the

VCO

frequency has

been

brought intothe

deadband

region.

[003]

PLLs

often use

"bang-bang"

type phasedetectors.

Bang-bang phase

detectors, also referredtoas "binary" or

"up/down"

phase detectors,output an indication

of

the

phase of

the

incoming

signal relative tothe

VCO

signalusing an

up

.AttorneyDocket No. 1003 1355-1

or

down (up/down)

signal.

The up/down

signal has

no

information

on how

farthe phase

of

the

VCO

signal differs

from

the

incoming

signal.

The

pull-inrange

of

a

bang-bang phase

detectorisproportional to thesize

of

the

immediate change

in

VCO

frequencythat results

from

an

up

or

down

signal.

The immediate change

in

VCO

frequencythat results

from

an

up/down

signal isgenerally referredto asthe"bang-

bang

step size"orsimplythe "step size."

PLLs

thatutilize

bang-bang phase

detectors are often referredtoas

bang-bang PLLs.

[004]

One problem

with

PLLs,

including

bang-bang PLLs,

is frequency

detectorovershoot.

Frequency

detectorovershoot occurs

when

thefrequencydetector causesthe

VCO

^frequencyto oscillate

around

the

deadband

region without beingable todrive the

VCO

^{frequency intothe}

deadband

region. This

can happen

ifthe

deadband

regionistoonarrow.

Another common problem

with

PLLs

ischarge

pump

leakage.

Charge pump

leakage

can make

thephasedetector'spull-inrange asymmetrical

and can

preventthe

PLL from

lockingifthe

deadband

region is

approached from

the

wrong

side.

A

^narrower

deadband

regioncan

remedy

this problem, butthis

may

leadtofrequencydetector overshoot.

[005]

Although

current

bang-bang PLLs work

well, there is still a

need

for

bang-bang PLLs

thatarelesssusceptibletoovershoot

and

charge

pump

leakage.

SUMMARY OF THE INVENTION

[006] In accordance withthe invention, thefrequency

changes

ina

bang-bang

PLL

thataregenerated using adigitalphasedetector's

up/down

signal areinitially set to

produce

afaster pull-in rate

and

arethen

reduced

to

produce

a smallerpull-in rate.

The

faster pull-in involvesrelativelylarge frequency changes,

which

allow fora

wider deadband

region

and

reduce the negative effects

of

charge

pump

leakage.

The

slowerpull-in rate involvessmallerfrequency

changes

thatenable finecontrol

of

the

PLL

in aregularoperatingstate.

The

finecontrol allowsthe

PLL

toachieveprecise frequency

and phase

lock.

[007]

The changes

infrequency

of

a

bang-bang PLL

can

be implemented

using a stepsize controllerthatincludestimingcontrol logic

and

stepsize logic.

The

function

of

thetimingcontrol logicistocontrol thetiming

of

stepsize changes. In

AttorneyDocket No.10031355-

1

particular, thetimingcontrol logic controls the transition

of

the step size

from an

initiallylarge stepsize toa

lower

stepsize.

The

timingcontrol logic initiates a

change

inthe step size

some

timeafterfrequency lockisestablished.

The

timing control logic

communicates

timingcontrol informationtothe step sizelogic viaa timingcontrolsignal.

The

step sizelogicreceives thetimingcontrol signal

from

the timing control logic

and may

receivea

programming

signal

from

a

programming

inputand/ora clocksignal

from

aclocksource.

The

function

of

the step sizelogicis to setthe stepsize

of

thefrequency

changes

that are

made by

the

VCO

ⁱⁿ responseto the

pd_up/down

signal that isdelivered directly tothe

VCO from

thedigital

phase

detector.

The

stepsize logic

may be

configured toprovide only

two

stepsizes, for example, a firststep sizethatis

used

initially

and

a second smallerstepsizethatis

transitioned toafter

some

period

of

time. Alternatively, the step size logic

may be

configuredtoprovide multiple intermediate stepsizes thatprovideatransition

from

the largeststep size tothesmallest stepsize.

BRIEF DESCRIPTION OF THE DRAWINGS

[008] Fig. 1 depicts

an embodiment of

a

bang-bang PLL

that includesastep size controller inaccordance withthe invention.

[009] Fig. 2depicts

an example of

the logicinvolved in controlling the step size

of

a

VCO

ⁱⁿaccordance withthe invention.

[0010] Fig. 3 depictsa

VCO and an embodiment _of

the step size controller depicted inFig. 1

.

[0011] Fig. 4depicts

exemplary waveforms

relatedtothe step sizecontroller

of

Fig. 3,

where

the step sizelogicprovides only

two

stepsizes.

[0012] Fig. 5 depicts

exemplary waveforms

related tothe step size controller

of

Fig. 3,

where

the step sizelogicprovidesmultiple intermediate step sizes thatprovide atransition

from

the largeststepsize tothe smallest step size.

[0013] Fig.

6A

depicts details

of an embodiment of

thetimingcontrol logic depicted inFig. 3.

[0014] Fig.

6B

depicts

waveforms

for

an exemplary

operation

of

thetiming control logicthat isdepictedinFig.

6A.

AttorneyDocket No. 10031355-1

[0015] Fig. 7

A

depictsdetails

of

another

embodiment of

thetimingcontrol logic depicted inFig. 3.

[0016] Fig.

7B

depicts

waveforms

foran

exemplary

operation

of

thetiming control logicthatis depictedinFig. 7A.

5 [0017] ^Fig. 8 depictsdetails

of

an

embodiment of

the step sizelogicdepicted in Fig. 3.

[0018] Fig. 9depictsdetails

of

another

embodiment of

the step size logic depictedinFig. 35

which

isconfiguredtoprovideintermediate stepsizes.

[0019] ^Fig. 10 depictsdetails

of

another

embodiment of

the step size logic 10 depictedin Fig.3,

which

isconfiguredtoprovideintermediate step sizes.

[0020] ^Fig. 1 1 depicts details

of

another

embodiment of

the step size logic depicted inFig. 3,

which

isconfiguredto allowthe

programming

to

be changed

without causing a countertorollover.

[0021] ^Fig. 12depicts

example waveforms

that illustrates

changes

ina counter 15 value

and

a

programming

inputusingthe stepsize logic

of

Fig. 11.

[0022] Fig. 13 depicts

an embodiment of

a

PLL

thatis configuredtoprovide

two

different step sizes ina

PLL

thatdoes not provideadirectinputtothe

VCO from

thedigital

phase

detector.

[0023] Fig. 14 ^isa process flow

diagram of

a

method

forcontrollinga

VCO

ⁱⁿa

20 bang-bang PLL.

[0024]

Throughout

the description similar reference

numbers

are

used

to identifysimilarelements.

25 DETAILED DESCRIPTION

[0025]

The

task

of

a

PLL

isto lockthe frequency

and phase of

a

VCO

signal to aparticularsignal, referred to herein asadata inputsignal (datajn). In

PLLs

with

bang-bang phase

detection, the

phase

detector adjusts thefrequency

of

the

VCO

30

signalusing a simple

up/down

signal. Inaccordance withthe invention, the

frequency

changes produced

using an

up/down

signal are initially settocause afaster pull-in rate

and

then

reduced

tocause a slowerpull-inrate.

The

slowerpull-in rate is

then maintained duringregular

PLL

operation.

AttorneyDocket No. 10031355-1

[0026] Fig. 1 depicts

an embodiment of

a

bang-bang PLL

100that includesa voltagecontrolled oscillator

(VCO)

102, adigitalphasedetector 104,a frequency detector 106, amultiplexer 108,a charge

pump

110,a loop filter 112,

and

astep size controller 114.

The

digital

phase

detector 104 isconnectedtoreceive

an

input signal 5 (data_in)

from

a signal source

and

a portion

of

the

VCO

signal

(VCOin) from

the

VCO. The

input signal carries the datathatisto

be

recovered.

As

part

of

the

PLL

operation, the digital

phase

detector

compares

transitions

of

theinput signalwith transitions

of

the

VCO

signal

and

generates

an

output(referred to herein as the

"pdup/down"

signal)that indicatesthephasedifference

between

the input signal

and

10 the

VCO

^signal.

The

digital

phase

detectorproduces an

"up"

signal

when

the

phase

of

the input signal leads the

phase of

the

VCO

^signal

and

a

"down"

signal

when

the

phase of

the input signal lags the

phase of

the

VCO

signal.

The pd up/down

signal is

providedtothecharge

pump

via themultiplexer

and

directly tothe

VCO. An up

signal drives thefrequency

of

the

VCO upward

whilea

down

signal drives the

15 frequency

of

the

VCO

^signal

^downward,

thereby

advancing

or retarding, respectively, the

phase of

the

VCO

^signal.

The

digital phasedetector also outputs therecovered data (data out). This datais notcriticalto theinvention

and

isnot described further.

Inan alternative

embodiment,

the

pd_up/down

signalisprovideddirectly tothe

VCO

afterthe

pd_up/down

signal passesthroughthemultiplexer 108.

20

[0027]

The

frequencydetector 106 isconnectedtoreceive a portion

of

the

VCO

signal

(VCOin) from

the

VCO

102

and

areferenceclocksignal (ref clk)

from

a reference clock source(often external to the system

and

not

shown

here).

The

frequencydetectorusesthereferenceclocksignal todetermine

whether

ornotthe

VCO

^signal should

be

controlled

by

thefrequencydetector.

The

frequencydetector 25 controls the

VCO when

thefrequency

of

the

VCO

signal isoutsideapre-established

deadband

regionthat iscenteredatthe setpointfrequency

of

the

VCO. The

frequency detectorgenerates acontrol signal (referredtoherein asthe"fd_en" signal) that indicates

whether

the

VCO

^isto

be

controlled

by

thefrequencydetector or thedigital

phase

detector 104 (thatis,

whether

control

of

the

VCO by

thefrequency detectoris

30

enabled or disabled).

When

thefrequencydetectordoes notcontrolthe

VCO because

thefrequency

of

the

VCO

^iswithinthe

deadband

region, the

PLL 100

issaid to

be

"in frequencylock."

When

thefrequencydetectordoes controlthe

VCO ^because

^the

frequency

of

the

VCO

^isoutside the

deadband

region, the

PLL

issaid to

be

"out

of

AttorneyDocket No. 10031355-1

frequencylock."

The

frequencydetector also generates

an

output(referredto herein asthe

"fd_up/down"

signal) thatindicates the sign

of

thefrequencydifference

between

the frequency

of

the

VCO

signal

and

the setpointfrequency.

The

frequency detectorproduces

an "up"

signal

when

thefrequency

of

the

VCO

is

below

the setpoint 5

frequency of

the

VCO and

a

"down"

signal

when

the frequency

of

the

VCO

^is

above

the setpointfrequency.

An up

signal drives thefrequency

of

the

VCO

^signal

upward

while a

down

signal drives thefrequency

downward.

[0028] Inthe

embodiment of

Fig. 1,

when

the control signal (fd_en)

from

the frequencydetector 106 is high, theoutput (fd_up/down)

from

thefrequencydetector 10 controls the

VCO

102. Conversely,

when

the control signal (fd_en) is low, theoutput

(pd_up/down) from

thedigital

phase

detector 104controls the

VCO. The

portion

of

the

VCO

signal thatisreceived atthe frequencydetector

and

the digital

phase

detector

may be

divided

by N

using asignal divider (notshown). In

an

alternative

embodiment,

the function

of

the frequencydetectorcan be

performed by

a

more

15 general "lockdetector,"

which

determines

whether

control

of

the

VCO

should

be

given

up

tothedigital

phase

detector. Instead

of

basingthe control decision

on

the frequencydifference

between

the actual frequency

of

the

VCO and

a setpoint

frequency(asisthecasewiththe frequencydetector),the lockdetector

may

use other criteria, suchasbiterrorsor consistency

of

phase,to determine if/whencontrol

of

the

20 VCO

should

be

given

up

tothedigitalphasedetector.

Even

iflockdetectionis not

based on

afrequency

measurement,

thereis stilla

need

for afrequencydetectorthat generates a signal representing the sign

of

thefrequencydifference

between

the

VCO

signal

and

areference signal.

[0029]

The

multiplexer 108receives the control signal (fd_en)

from

the

25

frequencydetector 106

and

allowsthecorrespondingcontrol signal(either

fd_up/down from

thefrequencydetector or

pd up/down from

thedigital

phase

detector 104) tocontrol thecharge

pump

110.

The

charge

pump

receives the correspondingsignal (referred toherein simply asthe

"up/down

signal")

from

the multiplexer

and

transfers apositivecharging currenttotheloopfilter 112 ifthe

30 up/down

signal is

"up"

ora negative chargingcurrentifthe

up/down

signal is

"down." The

loop filtergenerates a

VCO

tuningsignal(referred tointhe figures as Vtune) inresponsetoan output

from

the charge

pump.

In general,

when

apositive chargingcurrent isreceived

from

thecharge

pump,

thetuningvoltage output

from

the

AttorneyDocket No. 10031355-1

loopfilter is increased,thereby causingthefrequency

of

the

VCO

102 to increase.

Conversely,

when

a negative chargingcurrentis received

from

thecharge

pump,

the tuning voltage output

from

the loopfilterisdecreased,thereby causingthe frequency

of

the

VCO

todecrease.

5 [0030]

The

step sizecontroller114is connectedtoreceive the control signal (fd en)

from

thefrequency detector106

and may

receive a

programming

input

from

an optional

programming

interface 116.

The

stepsizecontrolleroutputs astep size signal (referredto in the figures as the "step_size"signal) inresponsetothe control signal (fd_en)

and

the optional

programming

input.

The

stepsize signal (step_size) 10 ^setsthe step size

of

frequency

changes

thatare

made

inresponsetothe

up/down

signal thatisprovided directlytothe

VCO

¹⁰²

from

thedigital phasedetector 104.

The

stepsizecontroller

and

step size controltechniquesaredescribedin

more

detail

below

with regardtoFigs.

2-12.

[0031]

The VCO

102 includesinputs for receiving the

VCO

tuningsignal 15 (Vtune)

from

the loopfilter 112,the

pdup/down

signal directly

from

the digital

phase

detector 104,

and

the stepsize signal (step_size)

from

the step sizecontroller 114!

The

directinput

of

the

pdup/down

signal

from

thedigital phasedetector

produces

relativelysmall adjustments inthe frequency

of

the

VCO

thatare

used

forachieving precise control

of

the

VCO ^when

^the

PLL

is in frequency lock(i.e.,

when

the digital

20

phasedetector controls the

VCO). The

step size signal(step_size) setsthe step size

of

frequency

and phase changes

that are

made

inresponsetothe

pd up/down

signal that

isreceiveddirectly

from

thedigital pliase detector. In analternative

embodiment,

the^

VCO may

receivethe

pd_up/down

signalafterthe

pd up/down

signal passes

through

themultiplexer 108 (at

which

point the

pd_up/down

signalisreferredto

simply

as the 25

up/down

signal).

The up/down

signal

can be

provideddirectly tothe

VCO by

asignal

paththatbranches offthe signalpath

between

themultiplexer 108

and

the charge

pump

¹10.

[0032] Operation

of

the

bang-bang PLL

100 depictedin Fig. 1 involves tuning the

VCO

102 inresponsetocontinuous feedback

from

thedigital

phase

detector 104, 30 thefrequencydetector 106,

and

the step sizecontroller 114. Startingatthe

VCO

^for

descriptionpurposes,the

VCO

receives the

VCO

tuningsignal (V^ne)

from

the loop

filter 112,the step_size signal

from

the stepsize controller,

and

the

pd_up/down

signal directly

from

thedigital

phase

detector. In response, the

VCO

^outputsa

VCO

AttorneyDocket No. 1003135^5-

1

signal

having

aparticularfrequency

and

phase.

A

portion

of

the

VCO

signal

(VCO

in) isfed intothedigitalphasedetector

and

thefrequencydetector.

The

digital

phase

detector

and

thefrequency detectorgenerate outputsignals

(pd_up/down,

fd_en,

and fd_up/down)

asdescribed

above

inresponse tothe

VCO

signal

(VCO

in).

When

the frequency

of

the

VCO

signal isoutside the

deadband

region(i.e.,the

PLL

isout

of

frequencylock), the frequencydetector controls the

VCO

throughthe

VCO

tuning signal _(Vtune).

When

thefrequency

of

the

VCO

^iswithinthe

deadband

region (i.e.,the

PLL

isin frequencylock),thedigital

phase

detector controls the

VCO

^{through a}

combination of

the

VCO

tuningsignal (V^ne)

and

thedirectlyprovided

pd up/down

signal.

The magnitude of

thefrequency

change produced

inresponseto thedirectly provided

pd_up/down

signal isset

by

the step size signal (step_size).

[0033] In

accordance

withthe invention, the stepsize signal isinitially setto

produce

relatively largefrequency

changes once

frequency lockisestablished

and

is

subsequently adjustedto

produce

smallerfrequency changes.

The

initial period

of

relatively largefrequency

changes

causesfaster pull-in, allowsfora

wider deadband

region,

and

reduces the negativeeffects

of

charge

pump

leakage. Subsequently adjusting the step size signal(stepsize)to

produce

smallerfrequency

changes

enablesfine control

of

the

PLL

100 inaregularoperatingstate,

which

allows the

PLL

toachieve precisefrequency

and phase

lock.

[0034] Fig. 2depicts

an example of

the logicinvolvedincontrolling the step size

of

a

VCO.

First, itis

determined whether

the

PLL

is in frequency lock,decision point220. Ifthe

PLL

isnotin frequency lock(i.e.,thefrequency

of

the

VCO

^isnot withinthe

deadband

region),thenthe frequencydetector controls.the

VCO,

block 222. Ifthe

PLL

is in frequency lock(i.e., thefrequency

of

the

VCO

iswithinthe

deadband

region), thenthedigital

phase

detector controls the

VCO,

block 224.

Once

frequency lockisobtained

and

thedigital phasedetector controls the

VCO,

the

VCO

frequencyis

changed by

afirststepsize, block 226. Next, itisdetermined

whether

the step sizeshould

be

changed, decisionpoint228.

Examples of how

this

determinationis

made

aredescribedin detail

below

withreferencetoFigs.

6A and

7A. In

an embodiment,

the step size

change

occurs

some

timeafter frequency lockis

established(i.e., afterthe control signal (fd_en)goes low). Ifthe step size isnotto

be

changed, thenthe

VCO

frequency continuesto

be changed by

thefirststepsize,block 226. If the step size isto

be

changed, thenthe step sizeis

changed

toa

second

step

AttorneyDocket No. 10031355-1

size, block 230.

Examples of how

the step size is

changed

aredescribed indetail

below

withreference to Figs. 8

-

_{1i. Afterthe stepsizeischanged, the}

VCO

frequencyis

changed by

the

second

stepsize,block 232. Next, itis determined

whether

frequency lockismaintained, decision point234. Iffrequency lockis

5 maintained, thenthe

VCO

frequency continuesto

be changed by

the secondstep size, block 232. Iffrequency lockisnot maintained(i.e.,the

PLL

fallsout

of

lock), then thefrequencydetector takesovercontrol

of

the

VCO,

block 222.

[0035]

As

statedabove,the inventionrelates tothe step sizecontroller

114 and

step sizecontroltechniquesthatare

implemented

usingthe stepsize controller. Fig. 3 10 depictsa

VCO 302 and an embodiment of

astep sizecontroller

314

that includes

timingcontrol logic

336 and

step size logic 338.

The

timingcontrol logic receives the control signal (fd_en)

from

thefrequencydetector 106(Fig. ₁₎

and may

receivea clock signal(elk)

from

an internalorexternalclock source (notshown).

The

function

of

thetimingcontrol logic istocontrol the timing

of

step sizechanges. Inparticular, 15 thetimingcontrol logic controlsthetransition

of

the stepsize

from an

initially large

step size toa smallerstepsize. Inthe

embodiment of

Fig. _3, thetimingcontrol logic initiatesa

change

inthe step size

some

timeafterfrequency lockisestablished (i.e., afterthecontrol signal (fd_en)

goes

low).

The

timingcontrol logic

communicates

timingcontrol informationtothe stepsizelogicviaa timing control signal (referred to

20

ⁱⁿ the figures as the

"pulMn"

signal).

The

delay

from when

the frequencydetector

gives

up

control

of

the

VCO

^{(i.e., after}the controlsignal(fd_en) goes low)to

when

stepsizereductionisinitiated (i.e.,

when

the control signal

(pulMn) goes

low) is typically

chosen

to

be

^{at least}long

enough

forthe

PLL

to pull the

VCO

frequencyto

be

equaltothefrequency

of

the inputsignal. In

some

applications, the delay is set 25 with

enough margin of

errorthat itisnotnecessaryto

know

theexacttime required

by

the

PLL

to

complete

frequencypull-in.

[0036]

The

stepsize logic

338

receives thetimingcontrol signal

(pulMn) from

thetimingcontrol logic

336 and may

receivea

programming

input

from

the

programming

interface 116 (Fig. 1) and/or a clocksignal(elk)

from

aclock source

30

(notshown).

The

function

of

the stepsize logicisto setthe step size

of

thefrequency

changes

thatare

made by

the

VCO 302

inresponsetothe

pd_up/down

signalthat is

delivereddirectly tothe

VCO from

thedigital

phase

detector 104 (Fig. 7). Inthe

.

embodiment of

Fig. 3, the step sizes are set

by

the step sizesignal (step_size).

The

AttorneyDocket No. 10031355-1

optional

programming

input is

used

to

program

the step sizes

and

the optional clock signal(elk)is

used

to control thetiming

of

stepsize transitions.

The

stepsize signal (step_size)

may be an

analogordigital signal

depending on

theimplementation.

The

step sizelogic

may be

configuredtoprovideonly

two

stepsizes, forexample, afirst 5 step size thatis

used

initially

and

asecond smaller stepsizethatistransitioned toafter

some

period

of

time. Alternatively, the stepsize logic

may

be configuredtoprovide multipleintermediate step sizesthatprovide atransition

from

the largeststepsize to the smallest stepsize.

[0037] Fig.

4

depicts

exemplary waveforms of

thecontrol signal(fd en) 440, 10 thetimingcontrol signal (pullin) 442,

and

the stepsize signal (step_size)

444

generated

by

the step size controller 314

of

Fig. 3, in

an example

in

which

the step sizelogicprovides only

two

stepsizes. InFig. 4,the control signal(fd_en) startsout high indicating that the

PLL

isout

of

frequency lock

and

then

changes

to

low

indicating thatfrequency lock has

been

established.

The

timingcontrol signal 15 (pull in) startsouthigh

and

then

changes

to

low

after

some

time in responsetothe

change

inthecontrol signal (fd_en).

The change

inthetimingcontrol signal (pull_in) to

low

inturncausesthe step size signal (step_size) to

go from

alargevalueto a small value. In general, thedelay

between

the

change

inthe control signal(fd en)

and

the

change

in thetimingcontrol signal (pull in)is controlled

by

thetimingcontrol logic

20 336 and

the

change from

the large step sizetothe small stepsizeiscontrolled

by

the stepsize logic338.

The

large stepsizecorrespondstolargerfrequency

changes and

enablesfasterpull-in

and

a

wider deadband

region.

The

larger stepsize istypically used forashorttime

immediately

afterfrequency lock isestablished.

The

smaller step sizecorrespondsto smallerfrequency

changes and

enablesprecise control

of

the

25 VCO. The

smallerstep sizeistypicallyused duringregular operation.

That

is, forall

operatingtime exceptforthe initialperiodafterfrequency lockisestablishedorre- established.

[0038] Fig. 5 depicts

exemplary waveforms of

the control signal(fd en) 540, thetimingcontrol signal (pull_in) 542,

and

the step sizesignal (step_size)

544 30

generated

by

the step size controller

314 of

Fig. 3, inan

example

in

which

the step

sizelogicprovides multiple intermediatestepsizes thatprovide atransition

from

the largeststep sizetothe smallest step size. Fig. 5is similar toFig. 4 exceptthatthe step sizesignal (step_size)begins atransition

from

thelargest tothe smallest step size

AttorneyDocket No. 1003135 5-

1

once

thetimingcontrol signal (pull_in) goes low. It

may be

desirable to transition the step size

from

the largestto the smallest step sizeusingmultiple intermediatestep sizes

because

in

some bang-bang PLLs, changing

the step size

from

the largevalueto thesmall valueinasingle

jump can

causethe

PLL

to losefrequencylock. In

5 particular,the

PLL

will likelylose frequency lockifthe

change

in frequencythatis

caused by

the

change

instep sizeis

much

largerthanthe difference

between

the

"up"

and "down"

frequencysteps

of

the

VCO

ⁱⁿthe regularoperation

mode. The

transition

from

the largesttothe smallest stepsize

may

involve multiplediscrete stepped

changes

(as

shown

inFig. 5) ora continuous

smooth

transition. Ifthe step 10 sizeistransitionedwith gradual intermediate step sizechanges,there

does

not

need

to

be any

delay

between when

frequency lockisobtained

and when

the step size transitionbegins.

The

step sizetransitionisregardedasbeing "gradual"

when

step sizereduction

does

notget

ahead of

thefrequencypull-in.

[0039]

The

functionalitydescribedwithreferencetoFigs. 1

-

₅

_{can be}

15

implemented

in

many

different

ways.

Fig.

6A

depictsdetails

of an embodiment of

the timingcontrol logic

336

depictedin Fig. 3.

The

timingcontrol logic

636

depictedin Fig.

6A

includes

two

flip-flops(FF)

646 and 647 and

an

OR

gate 648.

The

logic functions toassertthetimingcontrol signal(pullin) aslong asthe

PLL

isout

of

frequency lock(i.e., fd_en is high)

and

fora period

of

timeafterfrequency lock is

20

established(i.e., fd en islow). Inthe implementation, the control signal (fd_en) is thedatainputtothefirstflip-flop

and

theclocksignal (elk)is

used

forclockingboth

of

theflip-flops.

The

output signal(A)

from

thefirstflip-flopis thedatainputtothe

second

flip-flop.

The

outputsignal (D)

of

the

second

flip-flopis

one of

theinputs to the

OR

^gate. In operation, theclocksignal(elk) clocksthestate

of

the control signal

25

(fd_en)into the

two

flip-flops.

Any changes

tothe control signal(fd_en)

show up on

signals

A and D on

successive

edges of

theclocksignal(elk).

The OR

^{gatesets its}

output(pull in)highwhilethe control signal (fd_en)is high.

The

control signal is

maintained highfor

one

or

two

cycles

of

theclocksignal (elk) afterthe control signal

(fden)

goes

low depending on where

thetransition

of

the control signal(fd_en)

30

^N occurred.

Waveforms

thatdepict

an exemplary

operation

of

thetimingcontrol logic

aredepictedinFig. 6B.

[0040]

While

thetimingcontrol logic

636

depictedinFig. 6

A assumes

thatthe control signal (fd_en) ishigh withoutinterruptionuntil the

VCO

frequencyiswithin

AttorneyDocket No. 10031355-1

the

deadband

region, there are implementations

of

frequencydetectorsthat

have

control signalsthatarehigh intermittentlywith avariableduty cycleforaslongas the

VCO

^frequencyisoutside the

deadband

region.

For

thistype

of

frequencydetector, thetimingcontrol logic

of

Fig.

6A might

not

work

since

an edge of

theclocksignal (elk)

might miss

the

asynchronous

pulses

of

the control signal (fd_en)

and

causethe timingcontrol signal

(pulMn)

toturnoff too soon.

[0041] Fig. 7

A

^{depicts details}

of

another

embodiment of

thetimingcontrol logic

336

depicted inFig. 3 thatisconfiguredto

work

in conjunction with frequency

detectorsthatarepulsed-on asdescribed above.

The

timingcontrol logic

736

includesareset

(RS)

flip-flop749, aflip-flop750,

an AND

gate 751,

and

an inverter 752.

When

the control signal (fd_en) ishigh,the outputsignal (A)

of

the

RS

flip-flop is high.

The

risingedges

of

theclocksignal (elk),theperiod

of which

should

be

longer thanthelargest

gap between

control signal(fd en) pulses, clockthelevel

on

theoutput signal (A)totheoutput(pull_in)

of

theflip-flop750.

The

risingedges

of

theclocksignal (elk)alsoresetthe

RS

flip-flop via the pulsegeneratorthatis

formed by

the

AND

gate

and

theinverter.

[0042]

When

the control signal (fd en) stops pulsing, the

RS

flip-flop

749

is

no

longerset

between

clockedges

and

thetimingcontrol signal

(pulMn)

drops

low

after at least

one more

cycle

of

theclocksignal(elk). This

embodiment of

thetiming control logic

736

will

work

forboth constant-on

and

pulsed-on type frequency detectors.

Waveforms

thatdepict

an exemplary

operation

of

thetimingcontrol logic aredepictedinFig. 7B.

[0043] Fig. 8 depictsdetails

of

an

embodiment of

the stepsize logic

338

depictedinFig. 3.

The

step size logic

838 of

Fig. 8includes multiple

OR

^gates

754

thatprovide outputstoadigital-to-analogconverter

(DAC)

756.

The DAC

provides

an

analogstep sizesignal (step_size) as

an

output.

Each of

the

OR

gates includesa

firstinputthatis usedto seta

programmable

stepsize

and

a

second

inputthatreceives thetiming control signal

(pulMn).

All

of

thefirstinputs

make up

a

programming

input816. In operation,

when

thetimingcontrol signal

(pulMn)

ishigh, all

of

thebits thatare

used

to drivethe

DAC

are settologic 1 because

of

the

OR

gates.

The DAC

outputs its

maximum

(full-scale) analog value

when

allofthebitsaresetto logic 1.

When

thetimingcontrol signal

(pulMn)

islow, the

magnitude of

the step size signal

is set

by

the asserted bits

of

the

programming

input.

AttorneyDocket No. 1003135 5-

1

[0044]

As

described above, it

may be

desirable totransitionthe stepsize

from

the largestto thesmallest step sizeusingmultiple intermediate stepsizes. Fig. 9 depictsdetails

of

another

embodiment of

thestep size logic

338

depictedin Fig 3 that isconfiguredtoprovide intermediate stepsizes.

The embodiment of

Fig. 9 is similar tothe

embodiment of

Fig. 8exceptthatthestep sizelogic

938 of

Fig! 9 includes

a

low-pass filter

958

thatprovidesthe intermediate step sizes.

The

low-passfilter.

includesaresistor

960 and

acapacitor

962

connectedtotheoutput

of

the

DAC

^956.

The

low-passfiltertime constant is

chosen

such thatitprevents theanalogstep size signal(step size)

from changing

fasterthanthe

PLL can

track the

VCO

disturbance.

The

resistor

of

the

low

pass filter

may

not

need

to

be implemented

asaseparate physical

component

iftheoutput

impedance of

the

DAC

^islarge

enough

to

make

a suitablelow-passfiltertimeconstantwiththe capacitor alone.

[0045] Fig. 10depictsdetails

of

another

embodiment of

the step size logic

338

depicted inFig. 3 thatis configuredtoprovideintermediate step sizes.

The

step size logic

1038 of

Fig. 10 includesa counter 1064, a

NOR

gate 1066, a

comparator

1068,

and

a

DAC

1056.

The

step sizelogic receives a

programming

input(PI)

from

a register 1016. In alternative

embodiments,

theregister

may be

incorporatedintothe stepsize logic.

The

counterreceives the control signal (fd en), aclocksignal(elk),

and

acounter enablesignal(ctr_en).

The

counter outputs an n-bitcounter value

(CV)

tothe

DAC and

tothecomparator.

The

comparatorreceives the n-bitcounter value

(CV) from

thecounter

and an

n-bit

programming

input(PI)

from

theregister

and

outputs

an

equal signal(eq).

[0046] In operation, the voltage or current

of

the step sizesignal (step_size) is set

by

the

DAC

1056.

The DAC

^iscontrolled

by

thecounter value

(CV)

attheoutput

of

then-bitcounter 1064.

Whenever

thetimingcontrol signal

(pulMn)

ishigh, the counterispreset toits

maximum

valuevia the presetinput.

For

example, asserting the preset input sets each

of

thecounterbitshigh (e.g., logical 1).

The

counterpreset value could

be any

valuesuitable forthe desired

PLL

pull-inrate, butsettingallbits to logic 1 is easily

implemented.

[0047]

When

thetimingcontrol signal

(pulMn)

ishigh, thecounter enable signal (ctr_en) is forcedtoalogic0.

The

counter enablesignal (ctr_en)

being low

preventsthecounter

1064 from changing

state(e.g.,

decrementing

ifthecounteris a

down

counterorincrementingifthecounter isan

up

counter) inresponsetotheclock

AttorneyDocket No. 10031355-1

signal(elk)

and

therefore thecounter keepsoutputting itspresetvalue as thecounter value (CV).

[0048]

The

register

1016

contains the_n-bitvalue

of

the

programming

input (PI),

which

represents the value

of

the step sizesignal (step_size) thatisto

be

used during regular operation. Ina

system

withoutthe acceleratedpull-in, this registercould

be connected

directly tothe

DAC

1056.

[0049]

The comparator 1068 compares

then-bit values(PI

and CV)

thatare output

from

theregister

1016 and

the counter

1064 and

outputs

an

equal signal(eq) thatishighifthe

two

values are equal.

The comparator

_outputsan equal signal(eq) thatis

low when

the

two

valuesare notequal.

[0050]

During

pull-in(i.e., whilethetimingcontrol signal

(pulMn)

ishigh,

which

forces thecounter

1064

to its

maximum

value),theequal signal (eq)will

be

at logiclow.

When

thetimingcontrol signal

(pulMn)

drops low, the preset functionis

released, thecounter enablesignal (ctr_en)goes low,

and

thecounteris allowedto

change

state(e.g., decremented).

When

boththetimingcontrol signal

(pulMn) and

theequal signal (eq) are low, as will generally

be

the case

immediately

afterthe timing.control signal (pull_in)dropslow, the

NOR

gate

1066

willoutput a high counter enablesignal(ctr_en).

The

high counter enablesignal (ctr_en) allowsthe counterto

be decremented one

count per clock

edge

until itsoutput value

matches

the output value

from

theregister 1016.

When

thecount output

from

thecounter equals theregistervalue, theequal signal (eq)

of

the

comparator 1068

will

go

high

and

the

NOR

gate

1066

will dropthecounter enable signal (ctr_en)low.

Dropping

the

counter enable signal (ctr_en)

low

preventsthecounter

from decrementing

further

and

fixesthebitvaluethatisprovidedto the

DAC 1056

attheregistervalue.

As

stated above,theregistervalueisselected tocorrespondtothe regularoperatingcondition.

Note

that this

sequence of

preset

and

then count

down

tothe registervaluewillrepeat itselfevery timethefrequencydetector turns

on

thetimingcontrol signal

(pulMn)

without intervention

of

an external controlsignal.

[0051] After frequency lockisestablished

and

duringregular operation, there

may be

a

need

to

change

thevalue

of

the

programming

input(PI) storedin theregister 1016.

Changing

the value

of

the

programming

input (PI)toa largervalue

can

cause the

PLL

to losefrequency lock ifthe counterisrequiredto "rollover"to reachthe larger value. Fig. 1 1 depicts

an embodiment of

the step size logic

338

depictedin.Fig.

AttorneyDocket No. 10031355-1

3 thatis configuredtoallowthe

programming

input(PI) to

be changed

without requiringthe countertorollover,

which would

likely

push

the

PLL

out

of

lock.

The

step size logic 1138 issimilar to the stepsizelogic 1038

of

Fig. 10exceptthatthe counter is abletocount

up

or

down

(thecounter isreferred to hereinas

an "up/down

counter") inresponsetorespective

up

or

down

controlsignals.

The

stepsize logic depictedin Fig. 11 operates similarlytothe stepsize logicdepictedinFig. 10with a

few

differences. Specifically, the

comparator compares

thecounter value

(CV)

with the

programming

input(PI)

and

instead

of

outputtingan equal signal (eq),

which

indicates

whether

thecounter value

(CV) and

the

programming

input (PI) are equal, the

comparator

outputs an enable

up (enup)

signal(e.g.,

enup

is high)

when

the counter value

(CV)

is lessthanthe

programming

input(PI)or

an

enable

down (endn)

signal(e.g.,

en_dn

ishigh)

when

thecounter value

(CV)

isgreaterthanthe

programming

input(PI).

The

^result

of

this logic isthatthecounter

does

not

have

to rollovertoreacha

programming

input(PI) thatis

changed

afterfrequency lockis

achieved(e.g., tryingtoreach a

programming

input(PI) that isadjusted

upward

with

a down

counter).

[0052] Fig. 12depicts

example waveforms

thatillustrate

how

the counter value

(C V) changes

with

changes

inthe

programming

input(PI) inthecase

where

the

programming

inputisincreased(e.g.,

PV2 > _{PV1) and}

inthecase

where

the

programming

input(PI) isdecreased(e.g.,

PV3 < _PV2)

usingthe step sizelogic depictedinFig. 11.

Whether

the

programming

input(PI) isadjusted

upward

or

downward,

thecounter value

(CV) changes

tothe

programming

value (PI) without rollingoverin either direction.

[0053] Typically, the

pd up/down and

step size signalsarecontinuously providedto the

VCO and

are

always

influencing the

VCO

to

some

degree.

However, when

the

VCO

isbeingcontrolled

by

the frequencydetector(e.g.,

when

fd_en is

high), the influence

on

the frequency

of

the

VCO

^isinsignificant

compared

tothe influence

of

the

VCO

tuningsignal

(V

tune).

That

is,the

magnitude of

the

changes

in frequency

caused by

thedirectinput

of

the

pd_up/down

signal

and

thestep sizesignal (step_size) are so small

compared

tothe changes caused

by

the

VCO

tuningsignal (Vtune) thatthey

have no

practical effect

on

the

VCO

frequency

when

the

VCO

^isout

of

lock.

AttorneyDocket No. 10031355-1

[0054]

Because

the influence

of

thedirectly input

pdup/down

signal is

insignificant

compared

tothe influence

of

the

VCO

tuning signal(Vtune)

when

the

VCO

^isout

of

lock,the step size signalcan

be

"preset"atthedesiredhigh levelbefore frequency lockis established.

Once

frequency lockisestablished

and

the frequency 5 detector relinquishes controltothedigitalphase detector

and

thedesired step size is

alreadyset.

[0055]

A bang-bang PLL can be

controlled to

have two

different step sizes

even though

its

VCO ^does

notreceiveadirectinput

from

thedigital phasedetector(e.g., the

pd_up/down

signal). Fig. 13 depictsan

embodiment of

a

bang-bang PLL 1300

10 thatisconfiguredto provide

two

different step sizes

when

the

VCO 1302 does

not

receiveadirectinput

from

thedigitalphase detector 1304. Similartothe

systems

described

above

withreference toFigs. 1

and

3, the

system of

Fig. 13 includesa step sizecontroller

1314

that controls the stepsize

of

the

VCO once

the

VCO

establishes lock(i.e.,

when

the digital

phase

detector controls the

VCO and

fd_enislow).

The

15 step sizecontrollerincludes timingcontrol logic

1336 and

stepsizelogic 1338.

The

timingcontrol logicissimilar to thetimingcontrol logicdescribed

above

with referencetoFigs. 3,

6A, and 7A. The

timingcontrol logic outputsa timingcontrol signal (pullin)tothe step size logic.

The

stepsizelogic includesa switch

1372 and

a resistor

1374

thatarein serieswiththeresistor

1376 and

the capacitor

1378

that

make 20 up

the loopfilter

of

the

PLL.

In operation, the stepsize logic

1338

determinesthe

size

of

the ripple(i.e., instantaneouschanges)

on

the

VCO

tuningsignal(Vtune),

which

result

from

thevoltagedrop

of

the charge

pump

outputcurrent(I_cp)across thetotal resistanceisserieswiththecapacitor 1378.

When

the

PLL

isout

of

lock(i.e.,

fd_en

ishigh),thetimingcontrol signal (pull_in) ishigh

and

theswitchis

open

(as

shown

in 25 Fig. 13).

When

theswitchis open,thetotal resistanceis

R ⁼ Ro +

_Ri,

which

causes

the

magnitude of

the ripple

on

the

VCO

tuningsignal

(V

_tune)to

be

larger.

The

larger ripple

on

the

VCO

tuningsignal

(V

_tUne)translatesto a larger step size.

Some

time after lockisachieved

and

the control signal (fd_en)goes low, thetimingcontrol signal

(pulMn)

will

go low and

causetheswitchto close.

When

theswitch isclosed,

30

thetotalresistanceis

R ⁼

Ro,

which

causesthe

magnitude of

the ripple

on

the

VCO

tuning signal (V^ne)to

be

smaller than it

was when

theswitch

was

open. This causes the step size to

go

to its regularoperatingcondition. In

an embodiment,

theswitch

AttorneyDocket No. 10031355-1

could

be implemented

asa

MOSFET

orapair

of complementary MOSFETs

to

form

a

"passgate."

[0056] Fig. 14depictsa process flow

diagram of

a

method

forcontrolling a

VCO

ⁱⁿa

bang-bang PLL. At block

1490, a

VCO

frequency is

changed by

a firststep 5 size

upon

obtaining frequency lock.

At

block 1492, the

VCO

^frequencyis

changed by

a

second

step size afterthe

VCO

frequency has

been changed by

thefirststepsize,

wherein

thefirststepsizeislargerthan the

second

step size.

[0057]

Although

specific

embodiments

inaccordance with theinvention

have been

described

and

illustrated,the invention isnot limited tothe specific

forms and

10

arrangements

ofpartsso described

and

illustrated.

The

invention is limitedonly

by

theclaims.

>.