DVD BACK PANEL BOARD

(1)

(2)

(3)

(4)

SPDIF_IN

Reserv ed for SPDIF input

STANDBY voltages still carry power durin

g Standby Mode

CVBS

LEFT

RIGHT

STI5505 - Back Panel Connectors

VIDFILTR

{Value}

RED

GREEN

BLUE

CHROMA

LUMA

CVBS

RED_OUT

GREEN_OUT

BLUE_OUT

CHROMA_OUT

LUMA_OUT

CVBS_OUT

SPDIF

#BPRESET

SDA

SCL

SDATA1

PCMCLK

SDATA0

BPPIO1

LRCLK

BPPIO0

SCLK

SDATA2

BPPIO3

BPPIO2

LUMA_OUT

BLUE

CHROMA

CVBS_OUT

CHROMA_OUT

GREEN_OUT

RED_OUT

RED

BLUE_OUT

GREEN

CVBS

LUMA

VCC-STANDBY

+12V

+5V

VCC3-STANDBY

VCC-PCM

-12V

J11

FFC20

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

20 C90

10uF

16V

R60

100K

1%

R59

562R

1%

C92

10uF

16V

R62

100K

1%

R61

562R

1%

C91

1500pF

C93

1500pF

U13

CS4334

MCLK

4 SCLK

2 LRCLK

3 SDATA

1 AG

ND

6 VA

7 AOUTL

8 AOUTR

5 J12

FFC20

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

20 R145

75R

C145

47pF

JP11

HEADER 6

1

2

3

4

5

6 SPDIF

#BPRESET

SCL

SDATA2

BPPIO3

BPPIO2

SDATA0

SDATA1

SCLK

BPPIO1

BPPIO0

LRCLK

PCMCLK

SDA

CVBS

CHROMA

LUMA

GREEN

BLUE

(5)

I2C Address: 0xA0 (Write), 0xA1(Read) Defa ult configuration

STI5505 - Core Logic

MD[0..15] MA[0..11] MD2 MA5 #SDRAS MD11 MD1 MA1 MD7 MD6 MD14 MD4 MA10 DQMU MA6 #SDCS1 MD13 MA11 MA0 #SDWE MD8 MA3 #SDCS0 MA8 MD5 SDCLK MD3 MA4 DQML MD12 MD9 MD15 MD0 #SDCAS MD10 MA2 MA9 PARA_STR PARA_REQ PARA_SYNC BPPIO0 BPPIO1 BPPIO2 BPPIO3 #TRST TDO TDI TCK TMS MA7 #RAS1 #OE #CAS1 SDATA2 #CAS0 LUMA SDATA0 IR R/W #BE0 SCLK AUDCLK SDATA1 RED BLUE SPDIF CHROMA PIXCLK #CE3 LRCLK CVBS GREEN INT SCL SDA

ADR9 ADR13 ADR17 ADR8 ADR15 ADR19 ADR6 ADR7 ADR16 ADR18 ADR2 ADR4 ADR14 ADR20

ADR1 ADR3 ADR5 ADR10 ADR11 ADR12 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15

ADR[1..20] DATA[0..15] #CE1 FS0 FS1 SR0 #SOFT_RESET #BPRESET #FERESET PARA_DATA0 PARA_DATA1 PARA_DATA2 PARA_DATA2 PARA_DATA3 PARA_DATA3 PARA_DATA3 PARA_DATA4 PARA_DATA4 PARA_DATA4 PARA_DATA4 PARA_DATA5 PARA_DATA5 PARA_DATA5 PARA_DATA5 PARA_DATA5 PARA_DATA6 PARA_DATA6 PARA_DATA6 PARA_DATA6 PARA_DATA6 PARA_DATA6 PARA_DATA7 PARA_DATA7 PARA_DATA7 PARA_DATA7 PARA_DATA7 PARA_DATA7 PARA_DATA7 PARA_DATA[0..7] TRIGOUT TRIGIN #READY #RAS0 PARA_DVALID PARA_DATA6 PARA_DATA7 #RESET #JTAG_RESET #RESET RXD TXD CTS RTS #PUSH CLOSE #SENSE OPEN PARA_DVALID VCC3 VCC3 VCC3 VCC3-PCM VCC3-DENC VCC R27 56R R41 11K5 1% R40 18K7 1% R42 10K C88 .0033uF C87 330pF R8 10K R7 10K R22 10K U2 I2C-EEPROM 256x8 A0 1 A1 2 A2 3 SCL 6 SDA 5 WC 7 R10 33R TP1 R19 33R R39 4K7 R38 4K7 R26 75R C86 47pF R49 0R0 R50 NS R45 10K R43 0R0 R44 NS R12 10K R14 10K R15 10K R16 10K R17 10K R18 10K R9 NS R28 220R R29 220R R30 220R R31 220R R32 220R R33 220R R34 220R R35 220R R21 10K R13 10K R20 10K J3 HEADER20 Shrouded 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 U1 STi5505 DATA0 141 ADR1 161 DMAXFER134 VSS 87 DATA1 142 ADR2 162 CS 135 DATA2 143 PPCCLK137 ADR3 163 DQ0 92 DATA3 144 READY136 ADR4 164 DATA4 145 PPC_MODE138 VSS 150 ADR5 165 DATA5 146 VSS 77 DATA6 147 ADR6 166 VSS 103 PIO0_6/PCM_OUT2 21 VDD3 18 DATA7 148 ADR7 167 AD0 78 DATA8 151 PIO1_0/SDA 9 ADR8 168 PIO1_2/SCL 10 DATA9 152 YUV7/PIO1_3 198 ADR9 169 DATA10 153 ADR10 170 PIO1_4 199 ADR11 173 VDD3 34 DATA11 154 VDD3 67 ADR12 174 VDD3 75 VSS 120 VDD3 86 ADR13 175 VDD3 95 DATA12 155 VDD3 1 VDD3 102 ADR14 176 VDD3 110 CE1 124 VDD3 130 VDD3 119 ADR15 177 PIO1_5/TXD1 11 VDD3 139 ADR16 178 VDD3 149 DATA13 156 ADR17 179 VDD3 171 VDD3 159 CE2 125 ADR18 180 VDD3 184 DATA14 157 VDD3 208 ADR19 181 VDDA3_PC M 48 VSS 68 VDDA3 53 ADR20 182 VDDA3 60 CE3 126 ADR21 183 DATA15 158 PIO1_6/RXD1 12 R/W 133 VSS 35 OE 123 PIO1_7/TXD3 13 BE0 121 VSS 19 BE1 122 VSS 4 CAS0 129 VSS 96 RAS0 127 CAS1 132 RAS1 128 VSS 111 DQ1 93 AD1 79 PIO2_0 3 VSS 140 YUV0/PIO4_0 191 PIO3_0 201 YUV1/PIO4_1 192 YUV2/PIO4_2 193 PIO2_5 7 YUV3/PIO4_3 194 PIO3_1 202 YUV4/PIO4_4 195 G_OUT56 R_OUT57 PIO2_7 8 YUV5/PIO4_5 196 B_OUT55 DQ2 94 Y_OUT62 ODD/EVEN52 SCLK 43 HSYNC51 PCM_CLK45 PCM_OUT044 SPDIF 47 IRQ0 23 YUV6/PIO4_6 197 LRCLK 46 IRQ1 25 C_OUT63 PIO3_2 203 CVBS_OUT64 PCM_OUT124 PIO3_3 204 PIO2_3 5 AD2 80 PIO2_4 6 PIXCLK _27Mhz 118

PIO3_4 205 OSD_ACTIVE117 DQ3 97 PIO3_5 206 PIO3_6 207 VSS 131 PIO3_7 2 VSS 172 VSSA 61

V_REF DAC RG

B

58

VSS

160

I_REF DAC RG

B 59 DQ4 98 VSSA 54 AUXCLK116

V_REF DAC YC

65

VREF_PCM

49

AD3 81

I_REF DAC YC

66 VSS 185 DQ5 99 VSSA_PCM 50 VSS 200 AD4 69 PIO4_7/RXD3 14 DQ6 100 AD5 70 DQ7 101 DQ8 106 AD6 71 DQ9 107 AD7 72 DQ10 108 AD8 73 AD9 74 SDCS0 84 SDCS1 85 AD10 82 SDRAS 88 DQ11 109 SDCAS 89 AD11 83 DQMU 10591 DQML

DQ12 112

SDWE 90

MEMCLKIN 10476 MEMCLKOUT

DQ13 113 DQ14 114 DQ15 115 RESET 29 PARA_SYNC/PIO0_0 15 PARA_REQ/PIO0_3 16 PARA_STR/PIO0_4 17 PARA_DATA0/PIO0_5 20 PARA_DATA1/PIO0_7 22 PARA_DATA2/B_DATA 36 PWM0/OSLINK_SEL 26 PWM2 28 PWM1/BOOTFROMROM 27 PARA_DATA3/B_BCLK 37 TDI 186 PARA_DATA4/B_FLAG 38 TCK 188 TMS 187 TDO 189 PARA_DATA5/B_SYNC 39 TRST 190 NRSS_CLK/B_WCLK 40 NRSS_IN/B_V4 42 PARA_DVALID 33 PARA_DATA6/SDAV_CLK 30 PARA_DATA7/SDAV_DATA 31 SDAV_VALID 32 NRSS_OUT 41 R132 33R R133 33R R134 33R R135 33R R128 33R R129 33R R130 33R R131 33R R23 10K R11 10K R147 10K R148 10K R149 10K R25 10K R24 10K JP3 JUMPER U3 LMOS TC4S81F 1 2 4 R127 33R TP7 TP8 TP9 TP10 TP11 TP16 TP13 TP14 TP15 R168 NS TP17 R202 33R R203 33R R204 33R R205 33R R206 33R R207 33R MD[0..15] MA[0..11] SDCLK DQMU #SDCS0 #SDCS1 #SDRAS #SDCAS #SDWE DQML ADR[1..20] DATA[0..15] BPPIO2 BPPIO1 BPPIO0 BPPIO3 CVBS SDATA1 #CAS1 SPDIF LUMA IR INT SCL AUDCLK RED #WE LRCLK CHROMA SDATA0 #OE PIXCLK #RAS1 #CAS0 GREEN BLUE SCLK R/W SDATA2 SDA #CE3 #CE1 PARA_REQ PARA_SYNC PARA_STR PPCCLK SR0 FS0 FS1 #BPRESET #RESET #FERESET #POWERON_RESET PARA_DATA[0..7] #READY #RAS0 RTS RXD CTS TXD OPEN #PUSH #SENSE CLOSE FP_CLK FP_STB FP_DATA

(6)

- place RC terminati

on close to U8 & U9

Note:

- route SDCLK as

short as possible

- 125MHz SD RAMs are required

STI5505 - Decoder / OSD Memory

MD3

MD2

MD7

MD6

MA6

MD6

DQML

#SDWE

MA11

MD12

#SDRAS

MA10

MD1

#SDCS0

MA9

MD14

MD10

MA1

MA8

MD0

MD3

MD2

MD[0..15]

MA8

MD13

MA7

SDCLK

MA7

MD4

MA11

MA2

MA9

MD9

MA6

MD12

MA3

MD5

#SDCS1

MD13

MD11

MD15

MD11

MA4

MA5

MA3

MA4

MA2

MD8

MD4

MD7

#SDCAS

MD0

MD5

MD15

MD9

MA0

MD1

MA1

MD14

MD8

DQMU

MD10

MA[0..11]

MA5

MA0

VCC3

U8

SDRAM 1MX16

-7

3.3V

A0

21 A1

22 A2

23 A3

24 A4

27 A5

28 A6

29 A7

30 A8

31 A9

32 A10

20 A11

19 RAS

17 CAS

16 WE

15 CS

18 LDQM

14 UDQM

36 CLK

35 CKE

34 D0

2 D1

3 D2

5 D3

6 D4

8 D5

9 D6

11 D7

12 D8

39 D9

40 D10

42 D11

43 D12

45 D13

46 D14

48 D15

49 R63

75R

R66

75R

R70

75R

C100

47pF

C101

47pF

C96

47pF

R69

75R

U9

SDRAM 1MX16

-7

3.3V

A0

21 A1

22 A2

23 A3

24 A4

27 A5

28 A6

29 A7

30 A8

31 A9

32 A10

20 A11

19 RAS

17 CAS

16 WE

15 CS

18 LDQM

14 UDQM

36 CLK

35 CKE

34 D0

2 D1

3 D2

5 D3

6 D4

8 D5

9 D6

11 D7

12 D8

39 D9

40 D10

42 D11

43 D12

45 D13

46 D14

48 D15

49 C103

47pF

R65

75R

C99

47pF

R68

75R

C97

47pF

C102

47pF

C98

47pF

R67

75R

R64

75R

#SDCS1

MA[0..11]

MD[0..15]

#SDCS0

#SDCAS

#SDWE

SDCLK

#SDRAS

DQMU

DQML

(7)

Optional for 96kHz A

udio DAC support

Onl y used, if external

PLL is not used

SEE HARDWARE MANUAL FOR A

UDIO DAC SUPPORT

SHOWN: 96kHz W/ C rystal CS4334 DAC

(5505)

(DAC)

STI5505 - External PLL

PIXCLK

768fs

SR0

FS0

#BRESET

FS1

AUDCLK

PCMCLK

256fs

384fs

VCC3

VCC

VCC3

Y1

27MHz

C105

33pF

C104

33pF

R72

33R

R71

NS

R77

0R0

OSC1

NS-27MHz

NC

1 GND

4 CLK

5 VCC

8 U12

PLL1700

ML/SR0

1 MODE

2 VDD

3 GND

4 XT2

5 XT1

6 GNDP

LL

7 VDD

PLL

8 NC

9 MCK0

10 MCK0

11 SCKO1

12 SCKO4

13 SCKO2

14 GND

15 VD

D3

16 SCKO3

17 RESET

18 MD/FS0

19 MC/FS1

20 R197

NS

R198

0R0

R199

NS

R200

NS

R201

NS

R75 NS

R73

0R0

R76

0R0

R74 NS

U29

TC7W34FU

VCC

8 IN1

1 IN2

6 IN3

3 GND

4 OUT1

7 OUT2

2 OUT3

5 U30

TC7W74FU

D

2 Q

5 Q

3 PR

7 CL

6 GND

4 VCC

8 CLK

1 PIXCLK

FS1

FS0

#BPRESET

SR0

AUDCLK

(8)

Option for one Flas

h part without U10

Firmware Flash ROM (2n

d part is optional)

STI5505 - FLASH ROM Memory

ADR18

ADR4

ADR12

ADR15

ADR14

ADR5

ADR8

ADR3

ADR6

ADR2

ADR7

ADR1

ADR16

ADR9

ADR17

ADR10

ADR11

ADR13

ADR18

ADR4

ADR12

ADR15

ADR14

ADR5

ADR8

ADR3

ADR6

ADR2

ADR7

ADR1

ADR16

ADR9

ADR17

ADR10

ADR11

ADR13

#WE

#OE

#RESET

ADR[1..20]

#CEH

#CEL

ADR19

ADR20

ADR19

ADR20

DATA15

DATA14

DATA4

DATA5

DATA3

DATA2

DATA10

DATA7

DATA1

DATA12

DATA6

DATA7

DATA11

DATA8

DATA0

DATA8

DATA14

DATA11

DATA0

DATA13

DATA9

DATA5

DATA6

DATA10

DATA4

DATA3

DATA2

DATA15

DATA13

DATA1

DATA9

VCC-FLASH

R151

0R0

U6

29F800 Micron

VSS

27 DQ0

29 VSS

46 A0

25 DQ1

31 DQ2

33 A1

24 DQ3

35 DQ4

38 A2

23 DQ5

40 DQ6

42 A3

22 DQ7

44 A4

21 DQ8

30 DQ9

32 A5

20 DQ10

34 A6

19 DQ11

36 DQ12

39 A7

18 DQ13

41 A8

8 DQ14

43 A9

7 A10

6 A11

5 A12

4 A13

3 A14

2 A15

1 A16

48 A17

17 A18/NC

16 DQ15/A-1

45 BYTE

47 RP

12 RB

15 CE

26 OE

28 WE

11 VCC

37 A19/NC

9 VPP

13 #WP

14 R176

0R0

R175

0R0

U7

NS

VSS

27 DQ0

29 VSS

46 A0

25 DQ1

31 DQ2

33 A1

24 DQ3

35 DQ4

38 A2

23 DQ5

40 DQ6

42 A3

22 DQ7

44 A4

21 DQ8

30 DQ9

32 A5

20 DQ10

34 A6

19 DQ11

36 DQ12

39 A7

18 DQ13

41 A8

8 DQ14

43 A9

7 A10

6 A11

5 A12

4 A13

3 A14

2 A15

1 A16

48 A17

17 A18/NC

16 DQ15/A-1

45 BYTE

47 RP

12 RB

15 CE

26 OE

28 WE

11 VCC

37 A19/NC

9 VPP

13 #WP

14 R178

NS

R177

NS

ADR[1..20]

#ROMCEL

#ROMCEH

#RESET

#CE3

DATA[0..15]

#OE

#WE

(9)

INSTALL W HEN EPLD NOT USED

STI5505 - Front End Interface for ATAPI

#OE

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

DATA[0..15]

PARA_DATA5

PARA_DATA4

PARA_DATA3

PARA_DATA2

PARA_DATA7

PARA_DATA1

PARA_DATA0

PARA_DATA6

PARA_REQ

PARA_SYNC

PARA_STR

PARA_DATA[0..7]

#CS0ATAPI

#CS1ATAPI

#IOW

#IOR

#DMAACK

#IOCS16

#CE1

PPCCLK

#FERESET

#CE3

#ROMCEL

#ROMCEH

R/W

ADR[1..20]

ADR2

ADR19

ADR1

ADR3

ADR20

DA2

DA0

DA1

DA0

#READY

#CE1

R/W

#OE

#READY

DD11

DD14

DD11

DD7

DD4

DD12

DD8

DD15

DD4

DD9

DD6

DD13

DD1

DD5

DD15

DD14

DD0

DD6

DD0

DD9

DD7

DD3

DD2

DD13

DD1

DD10

DD8

DD2

DD5

DD12

DD3

DD[0..15]

DMAREQ

#FERESET

IORDY

TDO

TDI

TMS

TCK

#FPINT

INT

VCC3

VCC

R55

NS

R56

NS-0R0

R54

75R

C89

47pF

TP3

TP4

TP5

TP6

R155

NS-5K6

R153

NS-1K

R157

NS-100R

C149

NS-100pF

R154

NS-1K

J4

NS

1

2

3

4

5

6 R53

NS

R51

NS

U10

NS - XC9572XL-10

ATAPI Interface Controlle r for STI5505 REV 1

DATA0

52 ROMSIZE

15 DATA1

50 #ROMCEH

17 DATA2

49 #ROMCEL

16 DATA3

42 FEINT

18 DATA4

41 #IOCS16

13 DATA5

40 IORDY

14 DATA6

39 #DMACK

66 DATA7

37 DMARQ

77 DATA8

36 #IOR

67 DATA9

35 #IOW

68 DATA10

33 #CS1ATAPI

71 DATA11

32 #CS0ATAPI

70 DATA12

30 DA0

76 DATA13

29 DD0

78 DATA14

28 TCK

48 DATA15

27 DA1

74 VCC3

5 TDI

45 VCC3

26 ADR1

8 VCC3

38 TDO

83 VCC3

51 DD1

79 VCC3

57 DD2

81 VCC3

88 TMS

47 VCC3

98 DA2

72 ADR2

9 DD3

82 DD4

85 ADR3

10 DD5

86 DD6

87 ADR19

11 DD7

89 DD8

90 ADR20

12 DD9

91 FPINT

20 DD10

92 #RESET

99 DD11

93 DD12

94 CLK

22 DD13

95 DD14

96 #CE1

4 DD15

97 GND

21 #CE3

6 GND

31 GND

44 R/W

1 GND

62 GND

69 #OE

3 GND

75 GND

84 INT

23 GND

100 NC/SCL

2 NC/SDA

7 PARA_REQ

65 PARA_SYNC

63 PARA_STR

64 PARA_DATA0

61 READY

25 PARA_DATA1

60 PARA_DATA2

59 PARA_DATA3

58 PARA_DATA4

56 PARA_DATA5

55 PARA_DATA6

54 PARA_DATA7

53 R158

NS-10K

J5

NS

Shrouded

RESET

1 IOW

23 IOR

25 IOCHRDY

27 CSEL

28 INTRQ

31 HIO16

32 PDIAG

34 CS0

37 CS1

38 HA0

35 HA1

33 HA2

36 HD0

17 HD1

15 HD2

13 HD3

11 HD4

9 HD5

7 HD6

5 HD7

3 HD8

4 HD9

6 HD10

8 HD11

10 HD12

12 HD13

14 HD14

16 HD15

18 DASP

39 DMARQ

21 DMACK

29 KEY

20 GND

2 GND

19 GND

22 GND

24 GND

26 GND

30 GND

40 R52

NS-10K

R165

NS-10K

R208

0R0

DATA[0..15]

R/W

#OE

PARA_REQ

PARA_STR

PARA_DATA[0..7]

PARA_SYNC

#CE1

#FERESET

PPCCLK

#CE3

#ROMCEL

#ROMCEH

ADR[1..20]

FEINT

#READY

#FPINT

INT

(10)

DB9 PINOUT

TXD : 2

RXD : 3

RTS : 8

CTS : 7

GND : 5

(FEMALE)

STI5505 - Front End Options

TVM501

{Value}

BCLK

FLAG

SYNC

DATA

SCL

SDA

OPEN

CLOSE

#SENSE

#PUSH

#FERESET

FEINT

ATAPI & GLUE

{Value}

#FERESET

PARA_DATA[0..7]

PARA_REQ

PARA_SYNC

PARA_STR

#CE1

R/W

#OE

INT

ADR[1..20]

DATA[0..15]

#CE3

#ROMCEL

#ROMCEH

FEINT

#FPINT

PPCCLK

#READY

CLOSE

OPEN

#PUSH

#SENSE

SDA

SCL

ADR[1..20]

PARA_DATA5

B_SYNC

PARA_REQ

FEINT

#READY

PARA_DATA4

B_FLAG

#ROMCEL

FEINT

PARA_DATA3

B_BCLK

#CE3

PARA_DATA[0..7]

DATA[0..15]

INT

#CE1

PARA_SYNC

#OE

PARA_DATA2

B_DATA

R/W

PPCCLK

#ROMCEH

PARA_STR

#FERESET

TXD_B

RXD_B

RTS_B

CTS_B

VCC

U19

MAX232

C1+

1 C1-3

C2+

4 C2-5

TIN1

11 TIN2

10 RIN1

13 RIN2

8 TOUT1

14 TOUT2

7 ROUT1

12 ROUT2

9 VCC

16 GND

15 V+

2 V-

6 J9

HEADER 5X2

1

2

3

4

5

6

7

8

9

10 C151

.1uF

C154

.1uF

C150

.1uF

C153

.1uF

C152

.1uF

SDA

PARA_SYNC

PARA_STR

PARA_DATA[0..7]

PARA_REQ

#FERESET

SCL

DATA[0..15]

#READY

#ROMCEH

ADR[1..20]

#ROMCEL

#CE3

#OE

R/W

#CE1

PPCCLK

INT

CTS

RXD

RTS

TXD

#SENSE

#PUSH

OPEN

CLOSE

(11)

in1 , in2, out1, out2

pin5,

pin6, pin2, pin10

0, 0, 0, 0 (brake)

0 , 1, 0, 1 (open)

1, 0, 1, 0 (close)

1 , 1, 0, 0 (idle)

* Tray

motor must be in

idl

e state for push

sense to operate

7V

open

close

OPEN COLLECTOR

STI5505 - Front End TVM501/502 Interface

DATA

SYNC

SDA

FEINT

#FRESET

FLAG

SCL

BCLK

CLOSE

OPEN

CLOSE

VCC3

+8V

VCC

+12V

VCC

+8V

J6

PICOFLEX12

1

3

5

7

9

11

2

4

6

8

10

12 C108

.1uF

L5

22uH

J7

PICOFLEX10

1

3

5

7

9

2

4

6

8

10 L4

22uH

C109

10pF

C107

47uF

16V

U11

LB1641

OUT2

10 P2

9 VCC1

8 VCC2

7 IN2

6 IN1

5 V2

4 P1

3 OUT1

2 GND

1 J8

LOCKHEADER2

.1"

1

2 C110

.01uF

R80

10K

1%

C111

.1uF

R83

12K

1%

Q4

2N2222

R84

1K

D1

B120DI

D2

6V8

R82

1K

C112

100uF

16V

R79

15R

1/4W

R86

0R0

R87

0R0

U15A

LM393

+

-3

2

1

8

4 U15B

LM393

+

-5

6

7

8

4 C114

.1uF

R89

1K

D3

1N4148

R90

10K

C113

.1uF

R88

1K

R159

10K

FLAG

#FERESET

SCL

FEINT

BCLK

DATA

SYNC

SDA

OPEN

CLOSE

#SENSE

(12)

CONNECT TSOP18XX

STI5505 - Front Panel Connector

IR

FP_STB

FP_CLK

FP_DATA

VCC-STANDBY

JP14

JUMPER3

J13

HEADER6

1

2

3

4

5

6 FP_CLK

FP_STB

IR

FP_DATA

(13)

U1 STi5505 1 18 34 67 75 86 95 102 110 119 130 139 149 159 171 184 208 U4 DRAM 1 6 25 1 25 U5 DRAM 6 U8 SDRAM 1 7 13 25 38 44 U9 SDRAM 44 25 7 1 13 38

U6, U7 & U16 Flash ROM 37 37 U10 EPLD 5 26 38 51 57 88 98 U3 TC4S81F U2 I2C EEPROM 8 14 U12 PLL 3 16 8 OSC1 Oscillator 14 U13 PCM-DAC ANALOG 5V

TMM DRIVE SUPPLY

IN STALL R160, R161

TO BYPASS FET

POWER SWITCH

CONNECT TO

EXTERNAL

SWITCH

OPTIONAL POR CHIP

DIGITAL ANALOG

PROBE GND

CONNECTIONS

MOUNTING HOLES

ANALOG +5V

INSTALL TO-220

PACKAGE IF +5VA

CURRENT DRAW IS

OVER 150mA

TO-220 TOP

1 2 3 DPAK TOP

1 3 2

1 - VIN 3 - VOUT 2 - GND

STI5505 - Power Supply & Decoupling

AGND DGND

VCC-STANDBY VCC3-STANDBY +12V VCC3

VCC -12V

VCC VCC3 VDD3

GND VSS VDD VCC3 VCC3 VCC3-PCM VCC3-DENC VCC3 VCC3 VCC3 VCC3 VCC-FLASH VCC VCC3 VCC-STANDBY VCC3 GNDA VSSA VCC3 VCC VCC VCC3 VCC VCC-PCM +5V +5V +12V +8V +12V

VCC

Q1-1 NDS8934 2 8 1 7 Q1-2 NDS8934 4 6 3 5 C70 220uF 6V C71 .1uF C72 220uF 6V C73 .1uF C76 100uF 16V C77 .1uF C84 NS C85 NS C1 .1uF C18 10uF ELCO 16V C2 .1uF C3 .1uF C4 .1uF C5 .1uF C6 .1uF C7 .1uF C8 .1uF C9 .1uF C10 .1uF C11 .1uF C12 .1uF C13 .1uF C14 .1uF C15 .1uF C16 .1uF C17 .1uF L1 22uH L2 22uH C19 .1uF C20 22uF ELCO 16V C21 .1uF C22 22uF ELCO 16V C25 .1uF C26 .1uF C27 .1uF C30 .1uF C29 .1uF C28 .1uF C31 10uF ELCO 16V C37 .1uF C36 .1uF C35 .1uF C40 .1uF C38 .1uF C39 .1uF C43 .1uF C41 .1uF C42 .1uF C44 .1uF C46 .1uF C45 .1uF C47 10uF ELCO 16V C32 .1uF C34 10uF ELCO 16V R5 0R0 R6 NS JP1 JUMPER C55 10uF ELCO 16V C51 .1uF C49 .1uF C48 .1uF C53 .1uF C52 .1uF C50 .1uF C54 .1uF C24 .1uF C23 .1uF C56 .1uF C57 .1uF C59 .1uF C58 10uF ELCO 16V C60 10uF ELCO 16V C64 .1uF L3 22uH _C61 .1uF C62 10uF ELCO 16V C80 10uF 16V C81 .1uF C147 .1uF U17/1 SMT78M05 DPAK VI GND VO C33 .1uF U18 SMT78M08 VI GND VO C74 10uF 16V C75 .1uF C148 .1uF J1 .1" Keyed 1 2 3 4 5 6 7 8 R164 0R0

R4

100K

U14/1

ADM707

MR

1 VCC

2 GND

3 PFI

4 PFO

5 NC

6 RESET

7 RESET

8 R3

10K

C63

.1uF

R160 NS R161 NS

JP10

JUMPER

U14/2

NS-TC1270

VCC

4 RST

1 GND

2 MR

3 TP21

MT5

TP18

MT3

MT6

MT1

TP19

MT4

TP20

MT2

R152 10K U17/2 NS-7805 TO-220 VI GND VO

#POWERON_RESET

(14)

DRAM SUPPORT FOR 2x16M,

2x64M, OR 2x128M

Overlap footprints

of /1 and /2 parts

DRAM 64/128MBit (2nd

part is optional)

DRAM 16MBit

STI5505 - System Memory (ST20)

#RAS0

DATA12

DATA5

DATA1

DATA4

DATA11

DATA2

DATA15

DATA6

DATA14

DATA0

DATA13

DATA10

DATA7

DATA9

DATA8

DATA3

ADR9

ADR6

ADR10

ADR7

ADR5

ADR3

ADR2

ADR8

ADR1

#RAS1

#CAS0

R/W

#OE

#CAS1

ADR4

DATA11

DATA13

DATA5

DATA14

DATA6

DATA7

DATA8

ADR10

ADR7

ADR9

ADR3

ADR6

ADR5

ADR2

ADR1

DATA9

ADR8

DATA10

DATA1

ADR4

DATA3

DATA15

DATA12

DATA4

DATA2

DATA0

ADR12

ADR9

DATA5

DATA15

ADR13

DATA8

DATA3

ADR3

DATA11

ADR6

ADR7

DATA13

ADR13

ADR2

ADR8

ADR4

ADR11

DATA4

ADR2

ADR1

ADR5

ADR11

DATA13

DATA5

DATA0

DATA[0..15]

DATA6

DATA9

DATA6

DATA14

DATA12

DATA0

ADR7

ADR5

DATA1

DATA7

ADR8

ADR1

ADR[1..13]

ADR10

ADR6

DATA12

ADR10

DATA10

DATA1

ADR12

ADR4

DATA2

DATA15

DATA14

DATA2

DATA11

DATA4

#RAS1

ADR3

DATA9

DATA8

ADR9

DATA10

DATA7

DATA3

#RAS0

R/W

#CAS0

#CAS1

#OE

U4/2

DRAM

4Mx16 60ns

3.3V

D0

2 A0

19 D1

3 D2

4 A1

20 D3

5 A2

21 D4

7 D5

8 A3

22 D6

9 A4

23 D7

10 D8

41 A5

24 D9

42 A6

27 D10

43 D11

44 A7

28 D12

46 A8

29 D13

47 D14

48 A9

30 D15

49 RAS

14 CASL

38 CASH

37 WE

13 OE

36 A10

31 A11

32 A12/NC

33 U5/2

DRAM

4Mx16 60ns

3.3V

D0

2 A0

19 D1

3 D2

4 A1

20 D3

5 A2

21 D4

7 D5

8 A3

22 D6

9 A4

23 D7

10 D8

41 A5

24 D9

42 A6

27 D10

43 D11

44 A7

28 D12

46 A8

29 D13

47 D14

48 A9

30 D15

49 RAS

14 CASL

38 CASH

37 WE

13 OE

36 A10

31 A11

32 A12/NC

33 U5/1

DRAM

3.3V

1Mx16 60ns

D0

2 A0

21 D1

3 A1

22 D2

4 A2

23 D3

5 A3

24 D4

7 A4

27 D5

8 A5

28 D6

9 A6

29 D7

10 A7

30 D8

41 A8

31 D9

42 A9

32 D10

43 RAS

18 D11

44 CASL

35 D12

46 CASH

34 D13

47 WE

17 D14

48 OE

33 D15

49 U4/1

DRAM

3.3V

1Mx16 60ns

D0

2 A0

21 D1

3 A1

22 D2

4 A2

23 D3

5 A3

24 D4

7 A4

27 D5

8 A5

28 D6

9 A6

29 D7

10 A7

30 D8

41 A8

31 D9

42 A9

32 D10

43 RAS

18 D11

44 CASL

35 D12

46 CASH

34 D13

47 WE

17 D14

48 OE

33 D15

49 DATA[0..15]

#CAS1

#RAS0

#CAS0

#OE

R/W

ADR[1..13]

#RAS1

(15)

INSTALL 'NS' RESISTOR

S WITH 0R0 JUMPERS

TO BYPASS VIDEO BUFFER CIRCUITRY

STI5505 - Video Filters

+5V

R100

200R

1%

C121

100uF

ELCO

16V

Q6

2N2907

C124

390pF

L6

2.7uH

C125

390pF

R101

2K2

1%

R102

75R

1%

R97

12R

1%

R94

825R

1%

C116

.1uF

C115

.0033uF

R91

8R2

1%

R103

200R

1%

C122

100uF

ELCO

16V

Q7

2N2907

C126

390pF

L7

2.7uH

C127

390pF

R104

2K2

1%

R105

75R

1%

R98

12R

1%

R95

825R

1%

C117

.0033uF

R92

8R2

1%

R93

8R2

1%

R107

2K2

1%

R96

825R

1%

R108

75R

1%

C129

390pF

L8

2.7uH

R99

12R

1%

C119

.0033uF

R106

200R

1%

C128

390pF

C123

100uF

ELCO

16V

Q8

2N2907

R118

200R

1%

C136

100uF

ELCO

16V

Q9

2N2907

C139

390pF

L9

2.7uH

C140

390pF

R119

2K2

1%

R120

75R

1%

R115

12R

1%

R112

825R

1%

C130

.0033uF

R109

8R2

1%

R110

8R2

1%

R122

2K2

1%

R113

825R

1%

R123

75R

1%

C142

390pF

L10

2.7uH

R116

12R

1%

C132

.0033uF

R121

200R

1%

C141

390pF

C137

100uF

ELCO

16V

Q10

2N2907

C143

390pF

L11

2.7uH

C138

100uF

ELCO

16V

C144

390pF

C134

.0033uF

R111

8R2

1%

Q11

2N2907

R125

2K2

1%

R124

200R

1%

R117

12R

1%

R126

75R

1%

R114

825R

1%

C118

.1uF

C120

.1uF

C135

.1uF

C133

.1uF

C131

.1uF

R169

NS

R170

NS

R171

R174

NS

R173

NS

R172

NS

RED

RED_OUT

GREEN

GREEN_OUT

BLUE

BLUE_OUT

CHROMA

CHROMA_OUT

LUMA

LUMA_OUT

CVBS

(16)

I2C Add.:

I2C EEPROM 0xA0

TVM501 0x30

...

STI5505 - Overview of Decoder Board

POWER

#POWERON_RESET

FRONTPANEL

IR

FP_DATA

FP_CLK

FP_STB

BACKPANEL

#BPRESET

SPDIF

SCLK

LRCLK

SDATA0

SDATA1

SDATA2

RED

GREEN

BLUE

CHROMA

LUMA

CVBS

BPPIO0

BPPIO1

BPPIO2

BPPIO3

PCMCLK

SCL

SDA

EXTPLL

PCMCLK

PIXCLK

SR0

FS0

FS1

AUDCLK

#BPRESET

SYSMEM

ADR[1..13]

DATA[0..15]

#RAS0

#RAS1

#CAS0

#CAS1

R/W

#OE

FLASHROM

ADR[1..20]

DATA[0..15]

#OE

#WE

#ROMCEL

#ROMCEH

#RESET

#CE3

FRONTEND & GLUE

PARA_DATA[0..7]

PARA_REQ

PARA_SYNC

#FERESET

RTS

CTS

TXD

SCL

SDA

INT

RXD

PARA_STR

#OE

R/W

#CE1

ADR[1..20]

DATA[0..15]

#CE3

#ROMCEL

#ROMCEH

PPCCLK

#READY

OPEN

CLOSE

#SENSE

#PUSH

DECMEM

MA[0..11]

MD[0..15]

DQMU

DQML

#SDWE

#SDCAS

#SDRAS

#SDCS0

#SDCS1

SDCLK

STi5505

ADR[1..20]

DATA[0..15]

#RAS0

#RAS1

#CAS0

#CAS1

R/W

#OE

#WE

#RESET

#CE1

#CE3

PARA_DATA[0..7]

MA[0..11]

MD[0..15]

PARA_REQ

PARA_SYNC

PARA_STR

#FERESET

INT

RTS

CTS

TXD

RXD

AUDCLK

PIXCLK

FS1

FS0

SR0

BPPIO0

BPPIO1

BPPIO2

BPPIO3

CVBS

RED

GREEN

BLUE

CHROMA

LUMA

SCLK

LRCLK

SDATA0

SDATA1

SDATA2

SPDIF

#BPRESET

SDCLK

#SDCS0

#SDCS1

#SDRAS

#SDCAS

#SDWE

DQML

DQMU

#POWERON_RESET

PPCCLK

#READY

OPEN

CLOSE

#SENSE

#PUSH

FP_STB

FP_CLK

FP_DATA

IR

SCL

SDA

MD[0..15]

PARA_DATA[0..7]

MA[0..11]

DATA[0..15]

ADR[1..20]