2017-18_EVEN_Course_Plan_DSDV_15EC663(new format)

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Course Catalogue Description:

1. Hardware description, simulation, and synthesis using the Verilog language. 2. Design methodologies for combinational and sequential logic circuits and systems.

3. Characteristics of microprocessors, fault-tolerant computer design, computer arithmetic, advanced state machine theory.

4. Digital machine organization for testing and fault-tolerance. Pre-Requisite by Topic:

1. Digital Logic Design

2. Flip-flop and State Machine Design 3. Programming Methodology

4. Computer Architecture

Lesson Plan

Lectur e # Book & Sections Topics Portions coverage Teachin g Aids % of Syllabu s Covere d RBT Level

1-8 1.1, 1.3 to 1.5 :TB1 2.3 and 2.4 :TB1 4.3 up to 4.3.1,4.

4 up to 4.4.1 :TB1

Module 1 Introduction and Methodology:

Digital Systems and Embedded Systems, Real-World Circuits, Models, Design Methodology (1.1, 1.3 to 1.5 of Text).

Combinational Basics: Combinational Components and Circuits, Verification of Combinational Circuits.(2.3 and 2.4 of Text) Sequential Basics: Sequential Datapaths and Control Clocked Synchronous Timing

Methodology (4.3 up to 4.3.1, 4.4 up to 4.4.1 of Text). Chalk and Talk Video Lectures for some topics

20 L1, L2, L3 CMR Institute of Technology, Bangalore

Department(s): Electronics and Communication

Semester: 06 Section(s): OE Lectures/week: 04 Subject: Digital system Design using Verilog Code: 15EC663 Course Instructor(s): Chetan H

Course duration: 05 Feb 2018 – 25 May 2018

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Links to some useful online lectures:  http://slideplayer.com/slide/5743340/#  https://www.youtube.com/watch?v=ceuXLsuZhLE  https://www.youtube.com/watch?v=87Zvp6bYsqM 9-20 TB1: Chap 5 of Text Module 2

Memories: Concepts, Memory Types, Error Detection and Correction

Chalk and Talk Video Lectures for some topics 20 L1, L2, L3

Links to some useful online lectures:

 https://www.youtube.com/watch?v=ljbAysOT4WQ 21-29 TB1 Chap 6 of Text Module 3

Implementation Fabrics: Integrated Circuits, Programmable Logic Devices, Packaging and Circuit boards, Interconnection and Signal integrity

Chalk

and Talk 20

L1, L2, L3

 https://www.youtube.com/watch?v=oCh9VVG4_pE  https://www.youtube.com/watch?v=jrQ1YYgiOTo 30-38 TB1 Chap 8 of Text Module 4

I/O interfacing: I/O devices, I/O controllers, Parallel Buses, Serial Transmission, I/O software

Chalk and Talk Video Lectures for some topics 20 L1, L2, L3



https://www.youtube.com/watch?v=gyszWT5uf54

39-50 TB1. Chap 10 of Text Module 5

Design Methodology: Design flow, Design optimization, Design for test, Nontechnical Issues

Chalk

and Talk 20

L1, L2, L3, L4

Links to some useful online lectures:  http://slideplayer.com/slide/6231823/



http://slideplayer.com/slide/5743345/

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Book Type Code Author & Title Publication info Edition & Publisher ISBN #

Text Book TB1

Peter J. Ashenden, Elesvier ,”Digital Design: An Embedded Systems Approach Using

VERILOG”

2010, Morgan Kaufmann publishers

978-0-12-369527-7

References RB1 Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”

2nd_{Edition, Pearson}

Education 9788177589184

Syllabus for Internal Assessment Tests (IAT*)

*See calendar of events for IAT schedule. Sessional # Syllabus

T1 Class # 01 – 15 T2 Class # 16 – 30 T3 Class # 30 - 40

Course Learning Outcomes:

A student who successfully fulfils the course requirements will have demonstrated:

1. An ability to describe, design, simulate, and synthesize computer hardware using the Verilog hardware description language.

2. An ability to rapidly design combinational and sequential logic that works.

3. An ability to rapidly design complex state machines (present in all practical computers) that work. 4. An ability to synthesize logic and state machines using an Automatic Logic Synthesis program. 5. An ability to implement state machines using Field-Programmable Gate Arrays.

6. An ability to design high-speed computer arithmetic circuits. 7. An ability to design a computer to be fault-tolerant.

8. An ability to design a computer memory using error-correcting codes. 9. An ability to design a computer so that it can test itself with built-in circuitry. Learning Outcomes

On completion of this module the student will be able to: 1. Discriminate between combinatorial and sequential circuits. 2. Design state machines to control complex systems.

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3. Define and describe digital design flows for system design and recognize the trade-offs involved in different approaches.

4. Write synthesizable verilog.

5. Write a verilog test bench to test verilog modules. 6. Analyze code coverage of a verilog test bench. 7. Target a verilog design to an FPGA board. 8. Analyze and debug verilog modules.

9. Build a synchronous DSP system in verilog and verify its performance.

Computer Usage:

Students use the Xilinx tool to synthesize hardware from Verilog hardware descriptions, and the cadence behavioural/logic simulator to simulate the Verilog descriptions. (Optional)

Laboratory Experiences:

There are 10 Homework assignments that require students to use the circuit design software in the laboratory. (Optional)

Design Experiences:

The 10 Homework assignments are all hardware design experiences. Independent Learning Experiences:

The 10 Homework assignments.

**Based on table 01, 02, 03 in appendix, following are the Course outcomes.

Course Outcomes _PO1 _PO2 _PO3 _PO4 _PO5 _PO6 _PO7 _PO8 _PO9

PO

10

PO

11

PO

12

CO 1:

Digital Design methodology concept and work flow

3 3 3 2 0 0 0 0 1 0 0 0

CO 2:

Relate the Methodology to combinational circuit analysis and to develop verilog modules

3 3 3 2 0 0 0 0 1 0 0 0

CO 3:

Understanding basics of Numeric representations,

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develop verification methodology for the RTL modules

CO 4:

Relate the methodology for sequential designs, analyze and develop FSM related processing blocks

3 3 3 2 0 0 0 0 1 0 0 0

CO 5:

Developing different Memory architecture and developing processor modules

3 3 3 2 0 0 0 0 1 0 0 0

CO 6:

Understanding the concepts of I/O interfacing,

Implementation fabrics of digital systems

3 3 3 2 0 0 0 0 1 0 0 0

Note: Assignments, study material, Question bank and other course related content would be posted on site mentioned above.

02/02/18

Signature with date: Course Instructor Program Coordinator Head-ECE

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COGNITIV

E LEVEL REVISED BLOOMS TAXONOMY KEYWORDS

L1 List, define, tell, describe, identify, show, label, collect, examine, tabulate, quote, name, who, when, where, etc.

L2 summarize, describe, interpret, contrast, predict, associate, distinguish, estimate, differentiate, discuss, extend

L3 Apply, demonstrate, calculate, complete, illustrate, show, solve, examine, modify, relate, change, classify, experiment, discover.

L4 Analyze, separate, order, explain, connect, classify, arrange, divide, compare, select, explain, infer.

L5 Assess, decide, rank, grade, test, measure, recommend, convince, select, judge, explain, discriminate, support, conclude, compare, summarize.

PROGRAM OUTCOMES(PO), PROGRAM SPECIFIC OUTCOMES(PSO) CORRELATION LEVELS PO1 Engineering knowledge PO7 Environment and

sustainability -No

Correlation PO2 Problem analysis PO8 Ethics 1 Slight/Low PO3 Design/development of

solutions PO9 Individual and team work 2

Moderate/ Medium PO4 Conduct investigations of

complex problems

PO1

0 Communication 3

Substantial/ High

PO5 Modern tool usage PO11 Project management and finance

PO6 The Engineer and society PO1

2 Life-long learning PSO

1

Apply principles of electrical and electronic circuit theory to model digital design for complex circuits.

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2 and methodologies to verify the module.

1. Justification for levels of correlation for COs & POs/PSOs (DSDV)

PO1: Engineering Knowledge: Modeling and analysis of digital system design are based on mathematical principles and engineering fundamentals hence would have high correlation 3. (Both CO2 and CO1)

PO2: Problem Analysis: Digital VLSI design is predominantly an analysis subject which prepares the students for Digital VLSI design courses with introductory topics in design, hence high correlation 3. (Both CO2 and CO1)

PO3: Design/Development of solution: VLSI digital design is based on electronic circuit based and model based course hence designing involves in development of solutions, hence high correlation 3. (Both CO2 and CO1)

PO4: Conduct investigations of complex problems: Modeling and design would be the relatively complex task that an electronics graduate would have to perform in comparison with all subjects related to circuit design such as VLSI. Hence a correlation of 2 for C02 & C01. PO9: Individual & team work: the student is evaluated upon individual work based on internal exams and assignments which would cover the entire COs and hence a correlation of 1.

PSO1-PSO2: There is a high correlation since this PSO involves design of electronic circuits and COs are correlated from 1 to 3 based on the complexity.

2. Analysis on previous attainments.(Can be based on the following factors

Internals,externals,mapping)

Based on the report on attainment values for DSDV in the AY 2015-16

 Attainment level for Internal for DSDV: 1.83

 Attainment level for external for DSDV :2.8

 Attainment level for course is 80% of University exam + 20% of internal exam. -Attainment level for DSDV: 2.77

3. Setting targets on CO attainments and setting S1, S2, S3, M1, M2, M3

values for current semester subjects.

Rubrics for internal assessment tests

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ELSE IF S2% of students score ≥ M2 % of Max marks allotted to CO - Att.Lev. 2 ELSE IF S1% of students score ≥ M1 % of Max marks allotted to CO - Att.Lev. 1 ELSE Att. Lev. 0

Attainmen t Level

Last Year Values of S and M

( S3,M3,S2,M2,S1,M1 )

Current Year Values of S and M

( S3,M3,S2,M2,S1,M1)

S M S M

3 S3=50 M3=60 S3=50 M3=60

2 S2=40 M2=50 S2=40 M2=50