IMP 10 Special Interface Manual Oct73 pdf

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B 0 L T

BERANEK

AND

NEWMAN

INC C O N S U L T I N G D E V E L O P M E N T R E S E A R C H

i~---CAMBRIDGE

Manual for the

IMP-1~

Special Interface

to the Interface Message Processor

and the! ARPA Computer Network

October 1973

Computer Systems Division

Bolt Beranek and Newman Inc.

50 Moulton Street

Cambridge, Massachusetts 02138

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Manual for the

IMP-l~

Special Interface

to the Interface Message Processor

and the ARPA Computer Network

October 1973

Computer Systems Division

50 Moulton Street

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TABLE OF CONTENTS

· 1

1.

2.

3.

INTRODUCTION.

INSTALLATION . . • . .

INTERFACE OPERATION .

. . • 3

4.

3.1 Error Detection Logic. • .

• • .

3.2 Operation of the Host-to-IMP Section . .

3.3 Operation of the IMP-to-Host Section . .

LOG I C D RAW IN G

S. . . . -. . . • • • . • . • •

. .

..

5.

DESCRIPTION OF THE PROGRAM AND PROGRAM LISTINGS

6. WIRE LISTS . . • . . . • II) 0 • • 0 • • • • • • •

APPENDIX A Selections from Report 1822 .

. . •

• • 5

8

• 12

14

· • 26

· . 31

\ '

• • Al

APPENDIX B

APPENDIX C

Devi ce Codes. . . .

. • . . .

· B1

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1.

INTRODUCTION

The ARPA Network is being constructed to provide a capability

for geographically-separated Host computers to communicate with

each other.

However, Host computers generally differ from one

another in manufacturer, type, size, speed, word length, operating

systems, etc.

To allow these different computers to communicate,

each Host is connected into the network through an Interface

Message Processor (IMP) located on the Host premises.

The

complete network is formed by interconnecting these IMPs through

wideband communication lines (initially 50 kilobits/sec) supplied

by the telephone company.

Each IMP is then programmed to store

and forward messages to the neighboring IMPs in the network.

During a typical operation, a Host passes a message to its IMP.

This message is then passed from IMP to IMP through the network

until it finally arrives at the destination IMP, which passes

the message to the destination Host.*

The interconnection of a Host and an IMP is a joint effort

that requires the Host personnel to provide,interfacing hardware

and software.

Bolt Beranek and Newman Inc. (BBN) has built a

special interface to connect the IMP to a Digital Equipment Corp.

PDP-10 Host computer.

This report describes the design,

in-stallation, and operation of such a special interface.

Appendix A to this report reproduces Section

4

of the BBN

Report No. 1822, "Specifications for the Interconnection of a

Host and an IMP", which discusses the hardware requirements for

the special Host/IMP interface unit and describes the standard

*The initial IMP design is described in Bolt Beranek and Newman

Inc. Report No. 1763 (January 1969), AD-682-905.

The

specifica-tions for IMP-Host interconnection are described in BBN Report

No. 1822 (February 1970).

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Host/IMP interface unit in the IMP.

Appendix B contains the device code and jumpering for

specific installations.

Appendix C contains miscellaneous specific details of the

hardware, including drawings of the display panel circuitry.

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2.

INSTALLATION

The interface will normally connect to an IMP that is no

more than 30 feet from the interface.

A special Distant Host

option is required if the IMP is between 30 and 2000 feet from

the interface.

This option includes special cable drivers and

receivers required to deal with the Distant Host version of the

standard interface on the IMP itself.

The

IMP-l~

interface deals with the PDP-lO I/O BUS

ex-clusively.

The interface is built out of DEC R, B, and W-series

modules, mounted in two Type 1943 mounting panels.

A Type 728

power supply is supplied, together with a Type 844 power control

for protecting the I/O BUS circuits during power turn-on and

turn-off.

The circuit breaker and power switch on the back of

the 844 control power to the interface.

The interface mounts in a PDP-10 rack, occupying 10-1/2

inches of front panel space for two baskets of logic cards, and

16 inches of back panel space for the 728 power supply and 844

power controller.

The 5 1/411 display panel mounts at the front

of the rack in the usual manner.

Standard single-phase 115-volt

power" with a third-wire ground should be provided by the Host.

The Host should also provide switched l15-volt power to drive the

remote control relays in the 844.

The I/O BUS plugs into slots 25 through 28, and slots 29

through 32 of racks C and D, the lower basket.

A type H004

block is supplied for mounting the I/O BUS connectors.

The IMP cable plugs into slot Dl, or, in the case of a

distant Host, Dl and D2.

The device selection code is determined by jumpers on the

W990 modules in slots D6 and D7.

The jumpers should be placed

as follows:

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For

In order to effect the

device code in bit no. 3

4

5

6 7

8

9

then pin E J M E J M R

on the

W990

in

D6 D6 D6 D7 D7 D7 D7

should be connected

(to get a 0) to pin F K N F K N S

or (to get a 1) to pin

D

H L D H L P

the specific jumpering used, see Appendix

B.

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3 • I N T E R FA CEO P

E RA T

ION

To the program, the entire full duplex interface appears

as a single device that has one DATAO (Data Out), one DATAl

(Data In), and one CONO (Conditions Out), and one CONI (Conditions

In) instruction. Three interrupts are employed - - to indicate

completion of an output word, completion of an input word, and

completion of a message received from the IMP. These interrupts

may be individually program-assigned to any of the seven

inter-rupt channels. Thus, BLKO and BLKI instructions may reside in

dedicated interrupt locations, or one interrupt routine may

service two or all three interrupts, doing DATAO and DATAl

instructions functions. (Figure 1 shows the I/O Bus connections.)

Communication from the PDP-IO to the IMP is started by a

DATAO from the PDP-IO. The interface will cause an interrupt

on the "out" line to the PDP-IO on the 35th bit of each word.

The PDP-IO may then respond either with an additional DATAO,

which transmits thenext word, or with a CONO, with the "END OUT"

bit set (see Figure 2). In the latter case, the interface will

transmit the last bit to the IMP, with the "last bit" indicator

set, and then interrupt the PDP-IO again. The PDP-IO may now

respond either with another DATAO, to st~rt transmitting a new

buffer to the IMP, or with a CONO with the "STOP OUT" bit set,

which merely clears the interrupt. Input from the IMP to the

PDP-IO will cause an interrupt on the IN line each time a

com-'plete word is available. Upon receipt of the "last bit"

in-dicator from the IMP, the interface will pad with zeroes to

the end of a PDP-IO word and then cause an interrupt, both on

the IN line~ to indicate a full word, and on the END IN line,

to indicate end of message. Note that the IN interrupt should

be honored first, to complete the message, before servicing

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the completed buffer. However, the state of the END IN line should

be tested before executing the DATAl or BLOCKI, i f the two are

being serviced at the same priority level, since a new word

(the last) may have come in between the execution of the DATAl

and the next instruction. If that instruction concludes that

the word i t just took was the last, a word will be lost.

3.1

Error Detection Logic

IMP failures are indicated by an opening of the IMP relay

that connects the IMP Ready Test (ground) to the IMP Master

Ready line in the Host/IMP cable (see Figure 3). The IMP Master

Ready line provides a bit in the CONI word and any opening of

the IMP's relay is captured in the IMP-Has-Been-Down flip-flop,

which provides another bit in the CONI word. This bit is cleared

by one bit of the CONO instruct~on. Thus, the PDP-IO program

can at any time test the state of the IMP. In addition, an IN

END interrupt will be generated whenever the IMP becomes not

ready.

The PDP-IO has a corresponding relay which is controlled by

a bit in the CONO word. If the CONO IMP is issued with this bit

clear, the relay is closed. If this bit is set on the CONO, the

relay will open, and the Host will appea~ unready. The relay

is also opened by CROBAR from the

844,

or by lOB Reset.

3.2

Operation of the Host-to-IMP Section

Figure

4

is a block diagram of the logic of the Host-to-IMP

section. lOB reset presets the FIRST flip-flop to one. Upon

receipt of the first DATAO from the PDP-IO, the 36-bit shift

register is loaded from the 36 data lines. The MARK bit, to

the right of the shift register, is set to one. One microsecond

later, the shift register is shifted left by one position and

the left-most bit appears in the HSDTA flip-flop and on the Host

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FIGURE 3 - ERROR DETECTION LOGIC

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Data Line. The FIRST flip-flop is cleared at this point and

the Bit Available (BTAVL) flip-flop is set. At that time, if

the IMP is holding the Ready-For-Next-Bit (RFNHB) line true

(or shortly after the IMP brings this line true), the

There's-Your-Host-Bit (TYHB) line is brought true. When the IMP indicates

that i t has taken the bit, by bringing the Ready-For-Next-Host-Bit

line false, the pulse generator is fired, shifting the buffer one

bit to the left. A short time later, the interface again becomes

ready to give a bit to the IMP. On each shift, zeroes move into

the right end of the register.

This process continues for 35 bits. When the IMP confirms

taking the 35th bit, the interface shifts the 36th bit into

HSDTA and turns on the PlaUT flip-flop whichpresents an OUT

interrupt request to the PDP-IO. It also clears the Bit Available

. flip-flop, so that the IMP will not be given the

There's-Your-Host-Bit signal (for the 36th bit) until the program has given

the interface more information.

To send more words to the interface, the PDP-IO does further

DATAO's (or a BLKO, wh1c~ looks like a DATAO to the interface).

Note that the "preshift", one microsecond after the DATAO, does

not occur on words other than the first, since the FIRST

flip-flop 1s not set. The DATAO causes the data word to be loaded

into the shift register, puts a one into the MARK bit and turns

on BTAVL. This gives the IMP the last bit of the previous word

(which has been held in the HSDTA flip-flop of the shift register),

followed by the first 35 bits of the present word.

This process will continue until, after one of the interrupts,

the PDP-lO informs the interface via CONO END OUT that the previous

word was the last word of the message. At this point, the

inter-face will raise the Last-Host-Bit line and pass the last bit of

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the previous word to the IMP. The CONO END OUT also turns the

FIRST flip-flop back on, so that the first DATAO of the next

message will cause the "preshift" to occur.

When the IMP confirms receipt of the last bit, by bringing

down the Ready-For-Next-Host-Bit line, the interface again

inter-rupts the PDP-10. The PDP-10 may clear this interrupt either by

a

CONO STOP OUT, or by the first DATA

a

of a new buffer.

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Figure 5 is a block diagram of the logic of the IMP-to-Host

section. lOB reset sets the I'm-Ready-For-Next-Bit (IRFNB)

flip-flop. Upon receipt of a bit from the IMP, as indicated by the

There's-Your-IMP-Bit (TYIMB) line coming true, the INPUT shift

register is shifted 'one position to the left. Successive TYIMB's

have the same effect until MARK bit is shifted into the leftmost

position, indicating that the buffer is full. This causes an

interrupt request on the IN line, and also clears the IRFNB

flip-flop, to prevent bringing up the Ready-For-Next IMP-Bit line

until the word has been taken by the PDP-10.

The trailing edge of the DATAl instruction clears the

buffer, sets the MARK bit, and raises the Ready-For-Next-IMP-Bit

(RFNIB) line.

Upon receipt of the Last IMP bit indication, the interface

clears the IRFNB flip-flop, to prevent bringing the Ready-For-Next

IMP-Bit line true, and checks whether the input buffer is full.

If it is full, an interrupt request is raised on the END IN line.

If not, additional shift pulses are generated until the buffer

is full. Note that the IMP Data line is gated off during this

period by the falsity of the IRFNB flip-flop, thus forcing zeroes

to be shifted into the buffer.

(16)

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4.

LOGIC DRAWINGS

This section contains the following illustrations:

Figure

6

IMP Error Detection Logic

Figure

7

Pl OUT Channel Assignment

Figure 8

Pl IN Channel Assignment

Figure

9

Pl END IN Channel Assignment

Figure 10

I/O BUS Data Line Drivers-Receivers

Figure 11

I/O BUS Control, Host Ready Logic

Figure 12

Device Selection, Initialization

Figure 13 -- Host-to-IMP (Output) Buffer

Figure 14 -- Host-to-IMP (Output) Control Logic

Figure 15

IMP-to-Host (Input) Buffer

Figure 16 -- IMP-to-Host (Input) Control Logic

Figure 17a-- Local Host, Line Drivers and Receivers

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5. TEST PROGRAM DESCRIPTION

AND PROGRAM LISTINGS

The test program runs on the PDP-IO under any of three modes:

as a stand-alone program, as a program under a DEC 10/50 monitor

using user I/O, or as a program under a TENEX system running in

monitor space.

The program tests the interface by communicating with the

standard IMP system, repetitively sending to itself two messages

on separate links.

These messages contain sequence numbers which

are indexed with each consecutive transmission.

Upon receipt of

one of these messages from itself, the program verifies the data

includ,ing the sequence number against that transmitted and types

out any discrepancies.

A queue 6f messages waiting for tranSmission is kept, and

on receipt of the RFNM for a given message, another copy of that

message is placed on the queue, with the sequence number indexed.

If the sequence numbers for the two messages ever differ by more

than one, a RFNM has probably been dropped.

A message to this

effect is typed out and the program is reinitialized.

The program is organized as three co-routines:

an input

routine, an output routine, and a background routine.

The

back-ground routine polls the interface for input completion and

out-put completion, and calls the appropriate co-routine.

It also

tests for a number of error conditions including sequence number

differences of two or more, interface power down, IMP not ready,

IMP was down, and TIMEOUT (a long period with no activity).

Upon initialization the program clears the interface, makes

the Host appear down to the IMP, waits one second, then brings

the ready line true.

It then places four no-op messages on the

(31)

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queue of messages to be sent to the IMP, clears both sequence

counts and puts one copy of each of the two main messages on the

queue to be sent. The initial calling points of the input and

output routines are then set up and the timeout count is

initial-ized. The program then falls through to the background routine.

The input routine initializes the block-in pointer, then

loops, first calling the background routine to wait for an input

word. It then reads the interface conditions so that if the word

just input happens to be the last of the message, the ENDIN bit

can be reliably read. A BLKI is then executed to input the word.

This BLKI should never overflow, as the last word should be

re-ceived from the IMP before the input buffer is filled. The

ENDIN bit is then tested, and if not true, the input routine loops

to get another word. If the ENDIN bit was true, a CONO GOT ENDIN

is issued to the interface. The message is then tested for a

number of error conditions, any of which will cause a typeout.

A normal message from another Host, which is generally not an

error condition, will also cause a typeout. In addition, whenever

the sequence number on either link reaches a multiple of 10,000

octal, a typeout to that effect is given.

The output routine waits for the output buffer to be emptied,

then interrogates the queue to find whether there is anything

waiting to be sent. If not it returns to the background routine

to test the other background conditions. If it finds something

on the queue i t removes it, then loops, first waiting for the

output buffer to be empty, then executing the BLKO to actually

output a word. If the BLKO does not overflow, the routine loops

to wait for the buffer to be empty again. If i t does overflow,

after waiting for the buffer to be empty, a CONO END OUT is

issued. The routine then loops to again test the queue.

(32)

[

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Bolt Beranek and Newman Inc.

There are three assembly parameters which are installation

specific.

One is SYSTEM, which may be set either to BARE for a

stand-alone program, to DEC to run under a DEC 10/50 monitor with

user I/O privilege, or to TENEX to run under a TENEX system in

monitor address space.

In stand-alone mode, the program will

assemble in RIMIOB mode, with an origin of 4000.

If it is to

run under a 10/50 it will ordinarily load at location 140.

If

it is to run under a TENEX, its origin is 274000.

The remaining installation-specific parameters are the IMP

device code, called IMP, and the network address, called ADRES.

These three parameters must .be set at assembly time to the

relevant settings for the installation.

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DEC~:::1

TEN:X==2

;INSTALL~TION-SPSCIFIC AS3EM8LY pnRAMETERS

********.*************

; W HAT KIN 0 I) F S Y S 'I E t1 A i1 I RUN H ll~ GUN D E R ? II<

S!3:Zl'1==1'i::NBX ;IMP DEVICE COD):J

IMP,"=1'055,1

;MY

NET~oa~ ADDH8SS

lJ. 0 R ~ S = = , J 1 :'j 5

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;.*********.*************.*****.***********.*******~*************

;SYSTEM CAL1 DEF!NI~IONS

IFE S1STEM-LE~EX,<

SEARCH STEN:X

>

;LINK NUriBE3 TO 5E US EO

LINK==1'034.3 lIN~2==LINK+l

;INPUI ~UFF:R SIZE

IN.5IZ=='I'J225

STK3IZ==tD5 l ;PUSH DOW~ LIST SIZE

QUE3IZ=='I'D1~ ;SIZE OF OUTGOING MESSAGE QUEUE

CP=17 ;STACK POINTER

;OTHER AC'~

BLOCKI=<a10~KO=<INAC=<OUfAC=CP-1>~1>-1>-1

WHICH=<FtAGS=<TIME=<CUNDS=<QF=<OFfQ=B~OCKI-1>-1>-1>-1>-1>-1

;CONO BITS

CLR:RR==2')0~:'?I

f',

M,n. K'; ~D== 13<1;:,~ J STF)U'l'==~'3:J1 J .. :

El~DJU'I'==2:-~;;': ::.

GC.l'~ND== 1/)03·.5

ENB ~ND==4:.;r;

ENBiJUT==23Z

ENBn~== 1,~

; CONI BI'l'S

tL

F W R

u

P =::: 2 ; rH~ ?~~

Dew ~ 1 0

= =

1 ;~ tF: J

E~R==402 ,::;!1

IMPi)WN==2 11t.V·

END I N =

=

1 4 ;;' 0 'j

EMF fY==2 .:7'

FULL==10

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<DIAGNCSTICS>IMPBBN.Ai3 WED 22-NOV-7~ 1:58PM

IFE SYSTEM-BARE, <LOC 4~00

RU112io>

;DEFINE TTY OUTPUT MACROS IN CASE NOT 1~-50

>

IFE SYStEM-BARE, <DEFINE OUTSTR (ADURES) <HRRZI 1, ADORES

PUSHJ CP, TTY OUT> DEfInE ourCHR

IFE SYST!~-T3NEX, <DEFINE OUTSTR (ADORES) <HR ROI 1, A DDRES

PSO(JT>

DEFINE O(JTCHR

iMACRO TO PuT A ~ESSAGE oN TH~ OUTGOING QUEUE

DEFINE POQ (WORD)

STRING

/J>

tL

DEFINE ERC! (SX!ING)

«PUSH CP, '/

PUSH CP, 1

OUTSTR <p.SCIZ/

pUSHJ CP, PHEADR

P:'P CP, 1

p' P CP,3

JE~r .+1]>

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<DIAGN~S~ICS>IMPB8N.h;3

iIF RUNNING UNDER 12-50, CALL TapSET

START: IFE SYStEM_TENEX,<USRIO

JF.SI [OUrSTR<[AS:IZ*

USER I/O PRIVELEGF NOT AVAILABLE. ARE YOU ENABLED?

*»

HAlTF]>

IFE SYSI!~-D~C, <CALLI J,0

!1~V~I 1, ,;:

C1,LLI 1, 25

JLSI [OUTSf~<[ASCIZ*

USER I/O P3IVEL£3E NOT AVAILABLS

... J>

EXI:']>

IFF SYS1?M-EARE~ <CONO tTY, 3410>

M0V~ CP, [lOWD STKSIZ, STACK]

OUTSTR<[ASCIZ/

IMP 'IES1'EF.

/J>

C(NO IMP, MAK10D+ENBEND+ENBOUf+ENBIN

;NOW

WAIT FOR THg IMP TO SEE tHAT YOU ARE DOWN

IFN SYSIE~-O~C, <~OVSI ~, -4 .

A(JL .>

IFE SY51'r~:-;-D:::C,' <!"10VE.I J, 1

5tE-?>

;INITIALIZE QUEUE POINT~RS

H(.V~' QP, [IOWD QUESlZ, 'JUEUS)

l-I:V: OFE'Q, OP

;INITIALIZE THE IG!EBFACE

D i, I A I IMP, .!

C;~O IMP, CLRERR+ENDOUT+GOTEND

;pur

U NOP~ ON tHE OU?GOING MESSA3E QUEUE

i'j!'V::r 1, 4

NOPLOP: P-Q <[IO~D 1, NOPMES]> SLJG 1, ,'IOP1JP

. ;CLEAR BOTH SEQUS~CE COUNTBBS

SETZM MESCI

SETZ!'J ME:SC2

;QUEUE 80TH MAIN ~ESSAGES

P(:Q IOi-iDi

p~O IOWD2

;SET UP RETURN POINTERS TO POINT TO tHE BEGINNING OF THE

;INPUT AND OUTPUT ROUTINES

MrV~I I3hC, STP~I~

nCV~I aUlAC, STARTO

MCVSI TH1E, 4~;

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; <OIAGN:~!ICS>IMPE8N.A;3 WED 22-NOV-72 1:58PM

BCKGUD: C·NI IMP, CON OS ;6ACKGROUNO LOOP TESTS WHETHER

TFN~ CONDS, FULL ;INPUT WANTS SERVIC~

JnST (INAC)

TnNE CONDS, ~HFTY

JF..~i (OVI'AC)

iOR OUTPUT WANTS SERVICE

'l'IMCNT: WV; 1, M'E'SC"I

SUB 1, MESC2

JVl~fL 1, STI:P

SC JG 1, STE:f

;NOW TEST WHETHER SEQUENCE COUNTS

;OIFFER 31 MORE THAN 1, TO CHECK

iFOR DROPPED RFNMS

;NON TEST VARIOUS INiERFACE ERROR CONDITIONS

T~NN CONDS, ~WPUP

JffT [OUTSTR <[ASCIZ/

N 0 POW E F. ," ~~ I N TEa F A C [ 1

J

>

JF~J START]

TEL CONt'S, IMPOI-iN

JR5? [OUISTf <[ASCIZI

IMP IS Dowr/]>

JFS: STAr.!) 'I Hi :_ CO 1-: D S , ERR

JFS~ [OtTSiR <[ASCIZI

IMP WAS D'"~N ERiOR IJ>

PAGE 4

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H~~ ~ 1) G ; T'IIH 0 U T QUI C K L Y AFT E R If IMP WAS DOW N ..

J

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B C 1< G 1J D ]

S-JG TlhE, BCKGNC ;TOO LOnG SINCE THE LAST MESSAGE?

JIS: EROR clIME OU1, RESTARTING>

JE~T STAET

STEP: OUTSTB C[ASCIZ/

LINKS OUT cr STEP, PFNH DEep? RESTARTING

I»

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. w.-. .... '... _ '_~_ .

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iINPUI ROD1INE

STRTIN: ~~vr BLOCKI, [lOWD INSIZ, IEUFJ ;SEI UP ELKI POINTER

INLOP: JSF INle, BCKGhO ;WAIl FOB A WOBD

CC~I I~P, CONDS ;SAVE STATUS FO~ EKDIN TEST

SLYI I~F, ELOCKI ;GET THE WORD

Jrf:

ERCR <~fSSAGE FBO~ IMP ~OO BIG> ;IF BUFFER OV~RFLOWS

Ti~n CONDS, ENDIN;WAS JT THE LAST O~E?

Jrs~ INLOP ;NO

C

to

IMP, GOIEKD ;IES. RELEASE I~TEPFACE

;HAVt WOOLF MESSAGE IN CORE, CHECK IT

LOB 1, [POIEi 4, 12ur, 7J ;MESS TY~E

CLI~ 1, 5 ;BFNM1

J U

r:

P N 1, C 0 I~ :: R L ; IF U NUS U A L 11 E S SA GET Y P E

LOF 0, [POINT U, IBUF, 3J

JUrPN WtIROO ;IF IT IS FROM IMP, ETC

LOb 0, [POINT 8, IBUl', 15J

cr.!:

ADRES

JBS~ WE!RDO ;IF IT IS NOT FnOM ME

LOF WHICH, [POINT 8, IBUF, 23J ;LINK #

SUEI WHICH, LINK2

JUtPG WH:CH, EROR <LINK # TOO LARGE>

A:Jl WHICH, BROR <LICK # TOO SMALL>

UlI'I WHI:::a, 1

JU~:PE 1, NORNAL

SFNM: h~~ 1,~CHTADR(WHICH) ;INChEMENT MESSAGE COUNT

I»

FrC <IO~D1(WHICH» ,PUT MESSAG~ O~ OUTGOING QUEUE

TPr7 1, 7777 ;TIME ~O PRINT "0~00~H MESSAGE" ?

JP~~ STRTIH ;NO

M"V:":: 0,1

PU;:HJ CP, PRNUH

OUTSTR <[ASCIZ/TH MESSAGE ON LINK

IJ>

fi' ,.r~I- LINI< (HHlCH) PU;;',HJ Cl?, PF.NUM OUTSTR <[hSC!ZI

Jl1.S:: STRTIN

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WEIRDO: QUTSTR <[ASCIZ/ MESSAGE F~OM SITE /J>

LDH [POIH~ B,IBUF, 5J

PU~HJ CP, PRNUi1

PUSHJ C?, PH]ADR

JR:-:( STRTIU

WED 22-MOV-72 ':~8PM

;IS THE REC~IVED MESSAGE THE RIGHT SIZE?

NORMAL: HL~~ 0, BLOCKI

C~M~ 0, S!~TAB(HHICH)

JR~~ EROR<nIGHT MESS~GE, WRONG LENGTH>

iNOH

CHECK :HE DATA

M~"::~ 2, IOHD 1 (vrH!CH)

ADD 2, (XWD -1,1)

11'- V::I 3, IETJF COMPAR: i1';Y-: 0, (3)

CAre 0, (2)

JRS':' MIS!1A T

MATCH: ADD 3, [IND 1,1J

h I:' B J N 2, COM PAR

N~VSI TIME, 20 ;R~SET TIME COUNTER

JTIS:: STRTIN

STRANG: OU~STR ~TYP~AB-1(1)

PU~-:lh' CP, PHEADR

P"PJ CP,

CON:RL: LOR 1, [POINT 4, IBUF, 7J

PUSHJ CP, S7J:U.NG

J?S':;: STtCL';!:N 'I'L

()

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; <DIAGN~~ICS>IMPBBN.A;3

;NAMES

or

~:SSAGR TYPES .

DEFINE CONCAT(A,B) <A'B>

DEFINE NXTYFE (NkME)

<CONCAT(TYP,\N); ASCIZ/NAME/

N=!1+1>

I~= !

NXTYPE

EBRon

WITHOUT ID

NXTYPE IMP GOING DOWN

NX~YPE BLCCK~D LINK

NX~YPE NOP

NXTYPE RFNM

NX~YPE LINK TABLE rULL

NXTYPE DZSTINATION DEAD

NXTYPE ERROR WITH ID

NXTYPE INCOMPLETE TRANSMISSION

NX~YPE CEASR ON LINK

NXTYPE CEASE TIMEOUT

NXTYPE C:ASS SENT

NXT!PE TYPE;)

N X T Y PET Y P E ',"

N X 7 Y PET Y P Ei 5

I=:

TIPTtB: REF2AT N_1,<

Z CONCAT(TYP,\I)

r=:::+1>

tL

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; <DIAGN S?ICS>IMPBBN.A;3 WED22-NOV-7~ 1:58PM

MISMAT: OUT5TB <[ASCIZ/DATA MISMATCH ON THE /J>

HLnz 3

PUSHJ CP, PHNUM

OUTSTR <rASC!Z/TH WORD OF TH£ /J>

H~V: ~CNTADR (WHICH)

PU:::HJ CP, PRNUt1

OUTSTR «ASCIZ/TH MESSAGE ON LINK /J>

1"1 ,:' v :: I L I !~K ( 'II H I C H )

PU;;;HJ CP, PTINUM

OUTS'l'R <[l,SCIZ/'

SENT

I»

t·: :. "1":: (2)

PU3HJ CP, P?NUM OU:STR <[l\SCIZI RECEIVD IJ>

[','V2 (3)

PU~HJ C?, PRNU:'l

OUT S T R < [!l SCI Z 1

XOR IJ>

/J>

tL

trv'!

(2)

X~;R (3)

PUSHJ CP. PRNUi'l

OUTSTR <(.~SCIZ/

J3.S'I' 11ATCH

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<DIAGN-STICS>IHP8BN.A;3 WED 22-NOV.72 1:58PM PAGE 9

;OUTP(]T n:UI'INE

STARTO: JSB OUTAC, BCKGND iNAIT FOR THE BUFFER TO BE !MPTY

OUT: C~MN OFFO, OP ;ANITHING WAITING TO BE SENT?

JR3T TIMeNT ;~O

A: n J N OFF Q , • + 2 ; Y E; S • GET IT

M~V= OFFQ, (cIOWD QUESIZ. QUEUE>+<1,,1>J

l"l:.V2 BLOCKel, (OFFO) OUTLO?: JSP OUTAe, BCKGND

aLKO Il'lP, ELOCKO

JEST FINALO iIF

v!ts:

OUTLO?

FINALO: JSP aUTAe, BCKGND CCHO IMP, EtlDOUT

.. 1!L3T STARTO tL

-,

;WAII FOR BOFFER TO BE EMPTX jSEND A WORD

THAt ~AS THE ~AST WORD

;WAIT FOR THE BUFFER TO EMPIY

;TELL THE INTERFACE THAT'S AL~

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<DIAGN:3TICS>IMPBBN.A;3

;RaUTINE TO TYPE A CHARACTER

IFE SYSTUi-BAflE,

<TTYCKR:~:~?M 0, CHAR

D j~ T A I APR, ;.

T F: tal 0, 3

J!.ts,= DaCHAR TJNI 0, 2 C :: H saT T Y, '1 .:'

P PJ CP,

D~,'IAO TTY, [7J

P:PJ CP,

DOCHAR: C~NSO TTl, 1.'

JrST .-1

DJ. T AO TTY, CHid<

p',PJ CP,

CHAE:

z.

TTYOUT: HrLI 1, (POINT 7,~)

Jr~ST TTY NIP. TTYLOP: ourCHR

T'l'YlCIR: ILDB 1

Jur"'PN T',LYLOF

f,PJ CP,>

IFE SYSTE~-TEVEX,

<TTYCHR: EICH 0,1

pEOUT tXCH 21,1

r

PJ CP,>

WED 22-NOV-72 ,,:58FM

;ROUTINE TO ADD ~N E~TRY TO THE OUTGOING YUEUE

PUTONQ: ,i,-BJN QP, .+2

~:V~ QP, «lOWD OUESIZ, QUEUE>+<1,,1>J

E' V:::' M (Q P )

I PJ CP,

;BOUTINE TO PRINT OCTAL NUMBEB

PRNUM: LShC 0, -3

PRE!1:

'1.

JUIP, PE PRFN

PUSH CP, 1

pUSH,J CP, PRNUN

P(P CP,I

IMP 10 Special Interface Manual Oct73 pdf

BERANEK

Manual for the

INTERFACE OPERATION .

INTRODUCTION

systems, etc.

by the telephone company.

the message to the destination Host.*

PDP-10 Host computer.

the special Host/IMP interface unit and describes the standard

Bolt· Beranek and Newman Inc.

Host/IMP interface unit in the IMP.

more than 30 feet from the interface.

interface deals with the PDP-lO I/O BUS

turn-off.

power controller.

remote control relays in the 844.

The device selection code is determined by jumpers on the

Bolt Beranek and Newman Inc.

3 • I N T E R FA CEO P

!I'III!I."

S DEVSEL

tlI,o' or

\ 0 Y PI OUT

~C~JERS

CONNECTORS 1/0 BUS DRIVERS _ _ - _ - B1 G]!:::=P35

FIGURE 1 - I/O BUS CONNECTIONS

P I OUT

Error Detection Logic

Operation of the Host-to-IMP Section

RESET

fIIIIII!I

Bolt· Beranek and Newman Inc.

0

at ion

DATAl

RFNIB"~---I

CONO CLR

Figure

Figure 15

PIE29-PIE29 E ~17

PIOUT-o

RMYCOC

FIGURE 7 - PI OUT CHANNEL ASSIGNMENT

FULLO

FIGURE 8 - PI IN CHANNEL ASSIGNMENT

PIE25-PIE25

fIIIIIIIII

ENOIN-

FIGURE 9 - PI END IN CHANNEL ASSIGNMENT

[1IIIIIIII

IIIIIJ

832 821 PWCLR

~MYCOC

10COC L N MYCOC- 0

.... • . . fIIIIII

L ~ N MYCNI R002 P ... S MYOIA

FIGURE 12 - DEVICE

CI) % XCI)

+£ISIHr--~~l

III ... '" C\I

e':'::!~f;;'~~~~''''::'-=~~'~~;' ~';*,~tstiH"Hw;W8'

RFNNB 0

PUlSH~M V~T

PWCLR

IIIII!I

MYOIA

SFIHS J I

fIIIIIII

1.11 R202 ICII

fIIIIIIJ

MI R202 ICII

filii

III III

N TYINN

fIIIII!I!'

H RFNNB

aZZ resistors Z/4 watt

ARFNB- 01 IF

0

e':'::!~f;;'''''::'-=';' ~';*,~tstiH"Hw;W8'