1
FN561.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
FM IF System
Description
Intersil CA3089 is a monolithic integrated circuit that
pro-vides all the functions of a comprehensive FM-IF system.
The block diagram shows the CA3089 features, which
include a three-stage FM-IF amplifier/limiter configuration
with level detectors for each stage, a doubly-balanced
quadrature FM detector and an audio amplifier that features
the optional use of a muting (squelch) circuit.
The advanced circuit design of the IF system includes
desir-able deluxe features such as delayed AGC for the RF tuner,
and AFC drive circuit, and an output signal to drive a tuning
meter and/or provide stereo switching logic. In addition,
inter-nal power supply regulators maintain a nearly constant
cur-rent drain over the voltage supply range of +8.5V to +16V.
The CA3089 is ideal for high-fidelity operation. Distortion in a
CA3089 FM-IF System is primarily a function of the phase
linearity characteristic of the outboard detector coil.
Features
.• For FM IF Amplifier Applications in High-Fidelity,
Automotive, and Communications Receivers
• Includes: IF Amplifier, Quadrature Detector, AF
Preamplifier, and Specific Circuits for AGC, AFC, Muting
(Squelch), and Tuning Meter
• Exceptional Limiting Sensitivity
at -3dB Point . . . 12
µ
V (Typ)
• Low Distortion:
(with Double-Tuned Coil) . . . 0.1% (Typ)
• Single-Coil Tuning Capability
• High Recovered Audio . . . 400mV (Typ)
• Provides Specific Signal for Control of Interchannel Muting
(Squelch)
• Provides Specific Signal for Direct Drive of a Tuning Meter
• Provides Delayed AGC Voltage for RF Amplifier
• Provides a Specific Circuit for Flexible AFC
• Internal Supply-Voltage Regulators
Pinouts
Part Number Information
PART NUMBER
TEMP. RANGE
(oC) PACKAGE PKG. NO.
CA3089E -40 to 85 16 Ld PDIP E16.3
CA3089M1 (3089M) -40 to 85 20 Ld SOIC M20.3 CA3089 (PDIP) TOP VIEW CA3089 (SOIC) TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 IF IN INPUT BYPASS DC FB BYPASS FRAME GND MUTE CONTROL AUDIO OUT IF OUT AFC OUT NC SUBSTRATE (GND) TUNING METER OUT MUTE LOGIC V+ REF BIAS QUADRATURE INPUT DELAYED AGC 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 GND IF IN INPUT BYPASS DC FB BYPASS FRAME GND MUTE CONTROL AFC OUT AUDIO OUT IF OUT GND GND GND SUBSTRATE (GND) TUNING METER OUT DELAYED AGC MUTE LOGIC V+ REF BIAS QUADRATURE INPUT NC
Data Sheet
October 2002
OBSO
LETE
PROD
UCT
NO RE
COMM
ENDE
D REP
Absolute Maximum Ratings
Thermal Information
Supply Voltage
Between V+ and Frame GND . . . .16V Between V+ and Substrate GND . . . .16V DC Current (Out of Delayed AGC). . . 2mA
Operating Conditions
Temperature Range. . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θ
JA (oC/W) PDIP Package . . . 90 SOIC Package. . . 95 Maximum Junction Temperature (Plastic Package) . . . 150oC Maximum Storage Temperature Range . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . 300oC(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = 12V (See Figures 3 and 4) (NOTE 3)PARAMETER TEST CONDITIONS
TEMP.
(oC) MIN TYP MAX UNITS DC CHARACTERISTICS
Quiescent Circuit Current No signal input, Non muted 25 16 23 30 mA
DC Voltages Terminal 1 (IF Input) 25 1.2 1.9 2.4 V
Terminal 2 (AC Return to Input) 25 1.2 1.9 2.4 V
Terminal 3 (DC Bias to Input) 25 1.2 1.9 2.4 V
Terminal 6 (Audio Output) 25 5.0 5.6 6.0 V
Terminal 10 (DC Reference) 25 5.0 5.6 6.0 V
DYNAMIC CHARACTERISTICS
Input Limiting Voltage (-3dB point), V1 (lim) - fO = 10.7MHz, fMOD = 400Hz, Deviation = ±75kHz
25 - 12 25 µV
AM Rejection (Terminal 6), AMR VIN = 0.1V, AM Mod. = 30%
25 45 55 - dB
Recovered AF Voltage (Terminal 6) VO (AF) VIN = 0.1V 25 300 400 500 mV
Total Harmonic Distortion, THD (Note 2)
Single Tuned (Terminal 6) 25 - 0.5 1.0 %
Double Tuned (Terminal 6) 25 - 0.1 - %
Signal Plus Noise to Noise Ratio (Terminal 6) 25 60 67 - dB
NOTES:
2. THD characteristics are essentially a function of the phase characteristics of the network connected between Terminals 8, 9, and 10. 3. Terminal numbers refer to 16 Lead PDIP.
Application Information
FIGURE 1. AFC CHARACTERISTICS (CURRENT AT TERMINAL 7) vs CHANGE IN FREQUENCY. (SEE TEST CIRCUIT FIGURE 3)
FIGURE 2. MUTING ACTION, TUNER AGC, AND TUNING METER OUTPUT vs INPUT SIGNAL VOLTAGE. (SEE TEST CIRCUIT FIGURE 3)
-100 CHANGE IN FREQUENCY (kHz) -50 0 50 100 -125 -100 -75 -50 -25 0 25 50 75 100 125 µA 5kΩ V+ = 12V, TA 25oC 10 7 CURRE NT INT O T E RM IN AL 7 ( µ A) 100K 10K 1K 100 10 1 INPUT SIGNAL (µV) RE COVE RED AUD IO ( d B) M U T ING C O N T R O L AT M A XIM U M R ESIS T ANCE DC ( V ) 0 -10 -20 -30 -40 -50 -60 6 5 4 3 2 1 V+ = 12V, TA = 25oC
RECOVERED AUDIO FROM FULL OUTPUT (LEFT COORDINATE)
TUNER AGC DC VOLTAGE AT TERM. 15 (RIGHT COORDINATE) VOLTAGE AT TERMINAL 13 METER CIRCUIT (33kΩ TO GND) (RIGHT COORDINATE)
Test Circuits
NOTES:
4. All resistance values are in ohms. 5. L tunes with 100pF (C) at 10.7MHz.
6. Q0 (unloaded)
≅
75 (G.I. Automatic Mfg. Div. EX22741 or equivalent)NOTES:
7. All resistance values are in ohms.
8. T PRI. - Q0 (unloaded)
≅
75 (tunes with 100pF (C1) 20↑ of 34e on 7/32” dia. form).
9. SEC. - Q0 (unloaded)
≅
75 (tunes with 100pF (C2) 20↑ of 34e on 7/32” dia. form).
10. kQ (percent of critical coupling)
≅
70%. (Adjusted for coil voltage VC) = 150mV.Above values permit proper operation of mute (squelch) circuit “E” type slugs, spacing 4mm.
FIGURE 3. TEST CIRCUIT FOR CA3089E USING A SINGLE-TUNED DETECTOR COIL
FIGURE 4. TEST CIRCUIT FOR CA3089E USING A DOUBLE-TUNED DETECTOR COIL
AUDIO OUT SIGNAL INPUT VOLTAGE 14 4 15 13 5 12 0.001 µF 10 K 33K 0.001 µF 0.01 µF 6 FULL SCALE 150µA 2 3 0.01 µF 0.33µF 0.5M 120K 470 TUNING METER 2.7K 0.02 µF 51 1 0.01µF 11 0.05µF 8 7 9 10 3.9K 100 C L 5K 22µH AFC OUTPUT V+ = 12V pF CA3089E (NOTE 5) AUDIO OUT SIGNAL INPUT VOLTAGE 14 4 15 13 5 12 0.001 µF 10 K 33K 0.001 µF 0.01 µF 6 FULL SCALE 150µA 2 3 0.01 µF 0.33µF 0.5M 120K 470 TUNING METER 2.7K 0.02 µF 51 1 0.01µF 11 0.05µF 8 7 9 10 8.2K 100 C2 T (NOTE 8) 5K 22µH AFC OUTPUT V+ = 12V pF CA3089E C1 100 pF 3K
Test Applications
FIGURE 5. TYPICAL FM TUNER USING THE CA3089E WITH A SINGLE TUNED DETECTOR COIL
AUDIO OUT 0.01µF 6 3.9K 2.7K CA3089E 2 14 4 9 8 11 10 22 µH 250pF 220pF 1 3 300Ω
INPUT TUNERFM IF OUT
100 CERAMIC FILTER 0.01µF 0.05µF 330 V+ = 12V C 100pF L (NOTE 14) CA3089E
Performance Data at fO = 98MHz, fMOD = 400Hz, Deviation = ±75kHz: -3dB Limiting Sensitivity . . . 2µV (Antenna Level) 20dB Quieting Sensitivity . . . 1µV (Antenna Level) 30dB Quieting Sensitivity . . . .1.5µV (Antenna Level) NOTES:
11. All resistance values are in ohms. 12. Waller 4SN3FIC or equivalent. 13. Murata SFG 10.7mA or equivalent.
14. L tunes with 100pF (C) at 10.7MHz Q0 unloaded
≅
75 (G.I. EX22741 or equivalent).(NOTE 13) (NOTE 12)
Block Diagram
NOTES:
15. All resistance values are in ohms. 16. L Tunes with 100pF (C) at 10.7MHz. 17. QO @ 75 (G.I. EX22741 or equivalent). 18. Pin numbers refer to 16 lead DIP.
FIGURE 6A. BOTTOM VIEW OF PRINTED CIRCUIT BOARD FIGURE 6B. COMPONENT SIDE - TOP VIEW FIGURE 6. ACTUAL SIZE PHOTOGRAPHS OF THE CA3089E AND OUTBOARD COMPONENTS MOUNTED ON A PRINTED-CIRCUIT BOARD
Test Applications
(Continued)14 13 15 2 3 1 11 8 9 10 5 6 7 4 LEVEL DETECTOR 12 LEVEL DETECTOR LEVEL DETECTOR LEVEL DETECTOR 1ST IF AMPL. 2ND IF AMPL. 3RD IF AMPL. MUTE (SQUELCH) DRIVE CIRCUIT QUADRATURE DETECTOR TUNING METER CIRCUIT AFC AMPL. AUDIO AMPL. AUDIO MUTE (SQUELCH) CONTROL AMPL. V+ FRAME SUBSTRATE 150µA METER
33K TUNING METER OUTPUT
TO STEREO THRESHOLD LOGIC CIRCUITS 10K DELAYED AGC FOR RF AMPL 0.02µF 0.02 µF IF INPUT TO INTERNAL REGULATORS IF OUT REFERENCE BIAS AFC OUTPUT AUDIO OUTPUT MUTING SENSITIVITY 0.33µF 500K 120K 470 QUADRATURE INPUT 22µH C = 100pF L IF AMPLIFIER (NOTE 16)
Schematic Diagram
A Q9 Q15 R6 2K R7 2K R10 2K R11 2K C12 1 C11 1 C13 1 1 13 2 3 C14 1 C R2K18 R19 2K R23 2K Q21 Q22 R27 750 R24 480 R25 1.5K V+ V+ V+ B Q3 Q4 C2 1 Q8 Q8A Q10Q11 Q7A Q7 R12A 2K R16A 2K R13A 2K Q1 Q2 IF INPUT INPUT BYPASSING R2 30K Q6 R3 360 R1 30K C4 0.2 R13 2.7K Q12 R14 360 R12 2.7K C1 1 C3 0.2 R16 2.7K Q14 Q14A Q16Q17 Q18 Q13A Q13 R15 2.7K R15A 2K R21 480 R22 1.5K R20 2K Q19 Q20 R28 750 15 R50 500 Q58 V+ V+ R51 5K C5 2 Q59 R52 400 R53 600 R56 600 R61 4K C6 3 Q60 Q61 Q62 Q70 Q75 Q77 Q76 Q74 R59 150 R60 300 Q84 TUNING METER AGC FOR RF AMPL. IF AMPLIFIERLEVEL DETECTOR AND METER CIRCUIT
R17 360 C7 3 Q63 Q64 C8 3 Q69 Q68 SEE NEXT PAGE
Schematic Diagram
(Continued) R29 200 R31 390 Q23 R33 500 R36 200 Q24Q25 Q32Q33 Q35 Q26 Q34 R34 10K R26 10K Q38 Q39 Q40 Q27 D3 D2 R35 2.2K Q41 DETECTOR QUADRATURE INPUT REF BIAS IF OUT 9 10 8 R37 166 Q44 Q46 Q79 Q45 R38 500 R42 166 Q51 Q53 Q54 R44 500 R63 300 R64 300 Q80 Q81 R40 500 R41 500 Q82 11 6 5 Q49 Q48 Q50 R49 5K Q83 AUDIO AMPLIFIER A V+ V+ R65 50K R39 500 R43 500 Q47 Q52 Q56 Q55 R47 500 R48 500 Q57 AUDIO OUT MUTE CONTROL 7 AFC OUTPUT AFC AMPLIFIER 4 FRAME 14 SUBSTRATE Z1 Q28 Q30 D4 D5 Z2 Q43 R45 500 R54 5K R55 13K R46 4.2K Q29 R8 2K R5 4K R30 480 R9 10K V+ Q42 Q31 R4 480 D1 A Q5 C B Q65 Q66 Q67 BIAS SUPPLY 12 R57 10K R58 50 Q73 Q78 V+ Q72 Q71 C10 10 C9 10 MUTE DRIVE MUTE LOGIC R32 500 R62 500 NOTES:19. All resistance values are in ohms. 20. All capacitance values are in pF. 21. Pin numbers refer to 16 lead PDIP.
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be
perpendic-ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA -C-CL E eA C eB eC -B-E1 INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C-D1 B1 B e D D1 A A2 L A1 -A-0.010 (0.25)M C A B S
E16.3
(JEDEC MS-001-BB ISSUE D)16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTES
MIN MAX MIN MAX
A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 -B 0.014 0.022 0.356 0.558 -B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 -D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC -eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N 16 16 9 Rev. 0 12/93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
INDEX AREA E D N 1 2 3 -B-0.25(0.010) M C A B S e -A-L B M -C-A1 A SEATING PLANE 0.10(0.004) h x 45o C H µ 0.25(0.010) M B M
α
M20.3
(JEDEC MS-013-AC ISSUE C)20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTES
MIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -A1 0.0040 0.0118 0.10 0.30 -B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 -D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 e 0.050 BSC 1.27 BSC -H 0.394 0.419 10.00 10.65 -h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N 20 20 7
