Cascaded Counters. Page 1 BYU

Mod-N Counters

• Generally we are interested in counters that count up to specific count values

– Not just powers of 2

• A mod-N counter has N states

– Counts from 0 to N-1 then rolls over – Requires flip flops

• For example…

– A 4-bit binary counter is a mod-16 counter – A counter that counts from 0-9 is a mod-10

A Mod-4 Counter

A.K.A. 2-bit counter

CLR INC Q1 Q0 N1 N0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 - - - 0 0 00 10 01 11 CLR’•INC CLR’•INC’ CLR CLR’•INC CLR’•INC CLR’•INC CLR’•INC’ CLR’•INC’

A Mod-4 Counter With Rollover Signal

CLR INC Q1 Q0 N1 N0 RO 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 1 1 - - - 0 0 0 00 10 01 11 CLR’•INC CLR’•INC’ CLR’•INC CLR’•INC CLR’•INC / RO CLR’•INC’

The ROLL signal is used to tell other circuitry that the counter

Cascaded Counters

• Larger counters can be built by combining smaller counters together

• The rollover signal is used to communicate when the upper counters should roll over • Two types of counters

– Asynchronous – Synchronous

Mod-4 Counter 2 inc roll0 digit0 clr Mod-4 Counter 2 roll1 digit1 clr clk1 clk ‘1’

Sequence should be:

00-01-02-03-10-11-12-… clk digit0 2 3 0 digit1 0 1 1 2 But we get: 00-01-02-13-10-11-12-… As a general rule….

DO NOT tie the clock inputs on modules to anything but the clock!

clr clk digit0 digit1 roll0 / clk1 digit1 increments too early

Cascaded Asynchronous Counter

Mod-4 Counter 2 inc roll0 digit0 clr Mod-4 Counter 2 roll1 digit1 clr clk1 clk ‘1’

Cascaded Asynchronous Counter

• The more stages we add to the counter, the bigger the discrepancy between asynchronous counters and what we expect

Stage 1 Stage 2 Stage 3 Async Async Expected Expected

clk digit0 _{2 0} roll0 / clk1 3 digit1 0 1 1 2 It is possible to modify the circuit to get the correct count sequence, but the roll signal must be glitch free!

The transition from the value 1 to 2 (01₂ to 10₂) makes it difficult, if not impossible to eliminate glitches. Possible hazard Mod4 Counter 2 inc roll0 digit0 clr Mod4 Counter 2 roll1 digit1 clr clk1 clk ‘1’ 2

Ripple Counters

• When you tie a rollover-like signal to a clock

on the next higher digit

ripple counter

• A ripple counter is an

asynchronous

counter

– Transitions are not all synchronized to the clock – Different flip flops change at different times – Similar to gated clocks (seen earlier)

Another Common Ripple Counter

CLK T Q Q’ ‘1’ T Q Q’ ‘1’ T Q Q’ ‘1’ T Q Q’ ‘1’ Q3 Q2 Q1 Q0

Counts in normal binary:

0000 0001 0010 0011 0100 0101 0110 0111 1000 … …

Timing Diagram

clk Q0 Q1 Q2 Q3

Q0 changes in response to clock edge

Only after Q0 changes does Q1’s FF get a clock

Only after that does Q2’s FF get a clock

Logic depending on Q3 has very little time to react before next clock edge

Net effect is that all the FF’s change at different times!

Asynchronous and Ripple Counters

• Because asynchronous and ripple counters are difficult to use correctly, they are avoided

• Do not use them in your designs!

– Violates globally synchronous design principle

Synchronous Counters

• In a synchronous counter, all flip flops are clocked by the same clock signal

– They all change at the same time

• Synchronous counters can be cascaded to

create larger counters that are also globally synchronous

D Q D Q IFL inc Terminal Count Roll Over

A Mod-4 Counter

Count Value clr CLR INC Q1 Q0 N1 N0 RO 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 1 1 - - - 0 0 0 clk clk

D Q D Q IFL Terminal Count Roll Over

A Mod-4 Counter

Count Value

We could make a mod-4 counter

CLR INC Q1 Q0 N1 N0 RO 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 1 1 - - - 0 0 0 inc clr clk clk

Cascaded Counters

MOD4 inc TC MOD4 inc TC MOD4 inc TC CV CV CV inc clk clr clr clr clr

Cascaded Counters

MOD4 inc TC MOD4 inc TC MOD4 inc TC CV CV CV inc clk clr clr clr clr Terminal Count Rollover Count Value

Cascaded Counters

MOD4 inc TC MOD4 inc TC MOD4 inc TC CV CV CV inc clk clr clr clr clr

Assume that the second timer is already at the terminal count.

Cascaded Counters

MOD4 inc TC MOD4 inc TC MOD4 inc TC CV CV CV inc clk clr clr clr clr

Cascaded Counters

MOD4 inc TC MOD4 inc TC MOD4 inc TC CV CV CV inc clk clr clr clr clr

Cascaded Counters

MOD4 inc TC MOD4 inc TC MOD4 inc TC CV CV CV inc clk clr clr clr clr

Cascaded Counters

MOD4 inc TC MOD4 inc TC MOD4 inc TC CV CV CV inc clk clr clr clr clr

Cascaded Counters

MOD4 inc TC MOD4 inc TC MOD4 inc TC CV CV CV inc clk clr clr clr clr

Cascaded Counters

MOD4 inc TC MOD4 inc TC MOD4 inc TC CV CV CV inc clk clr clr clr clr

It looks like the inc signal ripples from counter to counter.

How is this different from the ripple counter examples?

10 11 00 01 digit0 roll digit1 00

Cascaded Synchronous Counter

Cascaded Synchronous Counter

• Notice that all signals are synchronized with the system clock

clk digit0 digit1 digit2 roll0 roll1 Signals:

D Q D Q IFL inc Terminal Count Roll Over

A Mod-4 Counter

With consolidated rollover logic

Count Value

clr

clk

A Mod-4 Counter

MOD4 dout roll clk clr inc

Cascading two Mod-4 Counters

00 01 02 03 10 11 12 13 20 21 22 23 30 31 Count Sequence: MOD4 2 inc roll0 digit0

Increment higher digit’s counter when lower digit’s

counter is rolling over

digit1 digit0 clr MOD4 2 roll1 digit1 clr clk clk inc inc roll roll dout dout clr clr

Three-digit Mod-4 Counter

• Can combine any counters that have a rollover signal to make larger counters

– Combine two 16-bit counters to make a 32-bit counter – Combine three mod-4 counters to make a three-digit

mod-4 counter MOD4 2 inc roll0 digit0 clr MOD4 2 roll1 digit1 clr clk clk inc inc roll roll dout dout clr clr MOD4 2 roll1 digit2 clr clk inc roll dout clr

BCD Counter

• Combine to create non-binary counters

– BCD counter MOD10 4 inc roll0 digit0 clr MOD10 4 roll1 digit1 clr clk clk inc inc roll roll dout dout clr clr MOD10 4 roll1 digit2 clr clk inc roll dout clr

Hybrid Counters

• Can combine different kinds of mod counters

– Combine an 8-bit counter with a 16-bit counter to create a 24-bit counter

– Combine mod-24 and mod-60 counters to create a digital H:M:S clock

MOD60 6 sec min Seconds clr MOD60 6 hour Minutes clr clk clk inc inc roll roll dout dout clr clr MOD24 5 day Hours clr clk inc roll dout clr

D Flip Flop with Asynchronous Clear and Clock Enable

Clock Enable (a.k.a. Load)

Clear (a.k.a. Reset)

Mod-4 Counter

D0 D1 CEO CLK CE CE

Reset CLK

Digit0 CEO

Cascaded Synchronous Counter

Digit1

Digit0

CEO

Library Counters

• Component libraries often have several cascadable counters available

Summary

• Mod-N counters are counters that count from 0 to N-1 then roll over

• Adding rollover logic to counters allows us to

cascade

counters

– We can build large counters from smaller ones – We can easily build non-binary counters

• BCD counter

• HMS clock counter