Lab-Volt 32 Bit Microprocessor Instructors Guide

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Digital and Microprocessor Electricity

32-Bit Microprocessor

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SECOND EDITION

First Printing, July 2003

Copyright July, 2003 Lab-Volt Systems, Inc.

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form by any means, electronic, mechanical, photocopied, recorded, or otherwise, without prior written permission from Lab-Volt Systems, Inc.

Information in this document is subject to change without notice and does not represent a commitment on the part of Lab-Volt Systems, Inc. The Lab-Volt F.A.C.E.T.® software and other materials described in this document are furnished under a license agreement or a nondisclosure agreement. The software may be used or copied only in accordance with the terms of the agreement.

ISBN 0-86657-239-2

Lab-Volt and F.A.C.E.T.® logos are trademarks of Lab-Volt Systems, Inc.

All other trademarks are the property of their respective owners. Other trademarks and trade names may be used in this document to refer to either the entity claiming the marks and names or their products. Lab-Volt System, Inc. disclaims any proprietary interest in trademarks and trade names other than its own.

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become bound by the terms of this License Agreement, Limited Warranty, and Disclaimer.

This License Agreement constitutes the complete agreement between you and Lab-Volt. If you do not agree to the terms of this agreement, do not use the software. Promptly return the F.A.C.E.T. Resources on Multimedia (CD-ROM) compact discs and all other materials that are part of Lab-Volt's F.A.C.E.T. product within ten days to Lab-Volt for a full refund or credit.

1. License Grant. In consideration of payment of the license fee, which is part of the price you paid for this Lab-Volt product, Lab-Volt, as Licensor, grants to you, the Licensee, a nonexclusive, nontransferable license to use this copy of the CD-ROM software with the corresponding F.A.C.E.T. Lab-Volt reserves all rights not expressly granted to the Licensee. 2. Ownership. As the Licensee, you own the physical media on which the CD-ROM is originally or subsequently recorded or fixed, but Lab-Volt retains title to and ownership of the software programs recorded on the original compact disc and any subsequent copies of the CD-ROM, regardless of the form or media in or on which the original and other copies may exist. This license is not a sale of the original software program of Lab-Volt's CD-ROM or any portion or copy of it. 3. Copy Restrictions. The CD-ROM software and the accompanying materials are copyrighted and contain proprietary information and trade secrets of Lab-Volt. Unauthorized copying of the CD-ROM even if modified, merged, or included with other software or with written materials is expressly forbidden. You may be held legally responsible for any infringement of Lab-Volt's intellectual property rights that is caused or encouraged by your failure to abide by the terms of this agreement. You may make copies of the CD-ROM solely for backup purposes provided the copyright notice is reproduced in its entirety on the backup copy.

4. Permitted Uses. This CD-ROM, Instructor's Guide, and all accompanying documentation is licensed to you, the Licensee, and may not be transferred to any third party for any length of time without the prior written consent of Lab-Volt. You may not modify, adapt, translate, reverse engineer, decompile, disassemble, or create derivative works based on the Lab-Volt product without the prior written permission of Lab-Volt. Written materials provided to you may not be modified, adapted, translated, or used to create derivative works without the prior written consent of Lab-Volt.

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Limited Warranty and Disclaimer

This CD-ROM software has been designed to assure correct operation when used in the manner and within the limits described in this Instructor's Guide. As a highly advanced software product, it is quite complex; thus, it is possible that if it is used in hardware configurations with characteristics other than those specified in this Instructor's Guide or in environments with nonspecified, unusual, or extensive other software products, problems may be encountered by a user. In such cases, Lab-Volt will make reasonable efforts to assist the user to properly operate the CD-ROM but without guaranteeing its proper performance in any hardware or software environment other than as described in this Instructor's Guide.

This CD-ROM software is warranted to conform to the descriptions of its functions and performance as outlined in this Instructor's Guide. Upon proper notification and within a period of one year from the date of installation and/or customer acceptance, Lab-Volt, at its sole and exclusive option, will remedy any nonconformity or replace any defective compact disc free of charge. Any substantial revisions of this product, made for purposes of correcting software deficiencies within the warranty period, will be made available, also on a licensed basis, to registered owners free of charge. Warranty support for this product is limited, in all cases, to software errors. Errors caused by hardware malfunctions or the use of nonspecified hardware or other software are not covered.

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Questions concerning this agreement and warranty and all requests for product repairs should be directed to the Lab-Volt field representative in your area.

LAB-VOLT SYSTEMS, INC. P.O. Box 686

Farmingdale, NJ 07727

Attention: Program Development

Phone: (732) 938-2000 or (800) LAB-VOLT Fax: (732) 774-8573

Technical Support: (800) 522-4436

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Section 1 – Workstation Inventory and Installation... 1-1 Inventory of Workstation ... 1-1 Minimum Computer Requirements... 1-1 Equipment and Supplies... 1-1 Equipment Installation ... 1-1 Software Installation ... 1-1 Section 2 – Introduction to FACET Curriculum ... 2-1 Getting Started ... 2-2 Screen Buttons ... 2-3 FACET Help Screens and Resources... 2-4 Internet Access ... 2-5 Instructor Annotation Tool... 2-5 Student Journal... 2-5 Assessing Progress ... 2-6 Real-Number Questions and Answers ... 2-8 Recall Values in Text ... 2-10 Safety ... 2-10 Safety ... 2-11 Section 3 – Courseware ... 3-1 Unit 1 – Trainer Familiarization ... 3-1 Exercise 1 – Introduction to the Trainer ... 3-4 Exercise 2 – Operating the Trainer ... 3-12 Unit 2 – Bus Operations ... 3-21 Exercise 1 – Bus States ... 3-24 Exercise 2 – 32-Bit Bus Transfers ... 3-30 Exercise 3 – Read and Write Cycles ... 3-37 Exercise – CPU Initialization... 3-42 Unit 3 – Memory Interfacing ... 3-51 Exercise 1 – Memory Control Signals ... 3-54 Exercise 2 – Memory Address Decoding... 3-64 Exercise 3 – Memory Data Transfers... 3-73

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Unit 4 – I/O Interfacing ... 3-81 Exercise 1 – DAC and ADC Ports ... 3-82 Exercise 2 – PPI and Keypad Interface... 3-88 Exercise 3 – Display and Serial Port... 3-95 Unit 5 – Interrupt Processing... 3-103 Exercise 1 – Non-Maskable Interrupts... 3-107 Exercise 2 – Maskable Interrupts... 3-115 Exercise 3 – Exceptions ... 3-124 Unit 6 – Programming: Addressing Modes ... 3-135 Exercise 1 – Immediate and Register Addressing Modes... 3-137 Exercise 2 – Memory Addressing Modes - I ... 3-144 Exercise 3 – Memory Addressing Modes - II ... 3-152 Unit 7 – Programming: 80386 CPU Instructions... 3-159 Exercise 1 – Instruction Formats - I... 3-160 Exercise 2 – Instruction Formats - II... 3-169 Exercise 3 – Using the 80386 CPU Instructions - I ... 3-178 Exercise 4 – Using the 80386 CPU Instructions - II... 3-186 Unit 8 – Troubleshooting... 3-195 Unit 9 – Microprocessor Applications (Optional)... 3-199 Exercise 1 – Application Board Familiarization... 3-201 Exercise 2 – DC Motor Control ... 3-206 Exercise 3 – Temperature Control ... 3-213 Appendix A – Pretest and Posttest Questions and Answers ... A-1 Appendix B – Faults and Circuit Modifications (CMs) ...B-1 Appendix C – Board and Courseware Troubleshooting ... C-1

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Introduction

This Instructor Guide is divided into three sections and the appendices. It provides a unit-by-unit outline of the Fault Assisted Circuits for Electronics Training (FACET) curriculum.

Section 1 – Workstation Inventory and Installation contains a list and description of equipment and materials required for all units in this course of study as well as installation instructions.

Section 2 – Introduction to FACET Curriculum provides a description of the courseware structure, instructions on getting started with the multimedia presentation, and an explanation of student-progress assessment methods.

Section 3 – Courseware includes information that enables the instructor to gain a general understanding of the units within the course.

♦ The unit objective

♦ Unit Fundamentals questions and answers

♦ A list of new terms and words for the unit

♦ Equipment required for the unit

♦ The exercise objectives

♦ Exercise Discussion questions and answers

♦ Exercise Procedure questions and answers

♦ Review questions and answers

♦ CMs and Faults available

♦ Unit Test questions and answers

♦ Troubleshooting questions and answers (where applicable)

Appendices include the questions and answers to the Pretest and Posttest plus additional specific information on faults and circuit modifications (CMs).

Please complete and return the OWNER REGISTRATION CARD included with the CD-ROM. This will assist Lab-Volt in ensuring that our customers receive maximum support.

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Inventory of Workstation

Use this section to identify and inventory the items needed. Minimum Computer Requirements

100% compatible Windows®PC with Windows98 second edition or newer, NT, 2000, Me or XP; Pentium class CPU, (Pentium II or newer); 126 MB RAM; 10 GB HDD; CD-ROM drive; SVGA monitor and video card capable of 32-bit color display at 1024 x 768 resolution and sound

capabilities.

Equipment and Supplies

The following equipment and supplies are needed for 32 Bit Microprocessor:

Quantity Description 1 F.A.C.E.T. base unit

1 Multimeter 1 Oscilloscope, dual trace

1 32-BIT MICROPROCESSOR circuit board

1 Student Workbook

Instructor Guide

MICROPROCESSOR APPLICATION BOARD (optional)

Equipment Installation

To install the hardware, refer to the Tech-Lab (minimum version 6.x) Installation Guide..

Software Installation

Third Party Application Installation

All applications and files that the courseware launches, or that are required for the course should be installed before the courseware. Load all third party software according to the manufacturers' directions. Install this software to the default location and note that location. (Alternatively, you can install this software to a different location that you designate.) Remember to register all software as required.

No third-party software is required for this course.

Installation of Courseware and Resources

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Overview

FACET curriculum is multimedia-based courseware. The curriculum gives students hands-on experience using equipment and software closely associated with industry standards. It provides students with opportunities for instruction in academic and technical skills.

All courses are activity-driven curricula. Each course consists of several units containing two or more exercises. Each unit begins with a statement explaining the overall goal of the unit (Unit Objective). This is followed by Unit Fundamentals. Next is a list of new terms and words then the equipment required for the unit. The exercises follow the unit material. When students complete all the exercises, they complete the Troubleshooting section and take the Unit Test. The exercises consist of an exercise objective, exercise discussion, and exercise procedures. The Exercise Conclusions section provides the students with a list of their achievements. Every exercise concludes with Review Questions. Available circuit modifications (CMs) and faults are listed after the review questions. Additional specific information on CMs and faults is available in Appendix B.

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Getting Started

Desktop

After the Tech-Lab System is installed, the TechLab icon appears on the desktop. 1. Click on the TechLab icon.

2._{The student clicks on LOGON and selects his or her name.}

3. The student enters his or her password and clicks on OK. (If he or she is creating a password, four alphanumeric characters must be entered. The system will ask for the password to be entered again for verification. Keep a record of the students' passwords.)

4._{The previous two steps are repeated until all members of the student team have logged on.} Click on Complete and then Yes.

5._{When the Available Courses menu appears, students click on the course name.}

6._{A window with the name of the course and a list of units for that course appears. Students} click on the unit name. The unit title page appears and the students are ready to begin.

Selecting Other Courses and Exiting the Courseware

1._{Clicking on Exit when in a unit returns the student to the list of units for that course.} 2. If students wish to select another unit, they click on it.

3._{If students wish to exit FACET, they click on the X symbol in the upper right corner.}

4._{If students wish to exit another course, they click on the Course Menu button. The Available} Courses menu screen appears. They may also exit FACET from this screen by clicking on the LOGOFF button.

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Screen Buttons

If you click on the FACET logo on the top right of the unit title page the About screen appears. It acknowledges the copyright holder(s) of video and/or screen-capture material used in the topic. The Menu button calls these menus:

when on an exercise menu screen, it calls the Unit Menu. when on an exercise screen, it calls the Exercise Menu. when on a unit screen, it calls the Unit Menu.

The Bookmark button marks the current screen. A student can click on the button at any time in the lesson. The second time the student clicks on the button, the page displayed when the button was first clicked will return to the screen. Any bookmarks used during a lesson are not saved when the student logs out of the lesson.

The Application Launch button opens third-party software.

Click on the Resources button to view a pop-up menu. The pop-up menu includes access to a calculator, a student journal, new terms and words, a print current screen option, the Lab-Volt authored Internet Website, and a variety of FACET help screens.

The Help button aids students with system information. On certain screens the Help button appears to be depressed. On these screens, clicking on the Help button will access Screen Help windows (context-sensitive help).

The Internet button opens an Internet browser. Students will have unrestricted access to all search engines and web sites unless the school administration has restricted this usage. Use the Exit button to exit the course.

The right arrow ⇒ button moves you forward to the next screen. The left arrow ⇐ button moves you backward to the previous screen.

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FACET Help Screens and Resources

There are three ways to access FACET help screens and other resources. System Help

Students access System Help by clicking on the Help button at the bottom of the screen when the button does not appear to be depressed. The menu selections access a variety of system help, navigation, and information windows.

Screen Help

On certain screens, the Help button appears to be depressed. On these screens, clicking on the Help button will access Screen Help windows. This is information specific to the content of that particular screen.

Resources

Students click on the Resources button to access the following windows. Calculator

FACET 32-Bit Microprocessor Help

FACET Analog Communications Setup Procedure FACET Digital Communications Help

FACET Electronics and Troubleshooting Help FACET Fiber Optic Communications Help FACET Math Help

Internet Link

New Terms and Words Print Current Page Student Journal

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Internet Access

There are two ways for students to access the Internet:

The Internet button opens an Internet browser. Students have unrestricted access to all search engines and websites unless the school administration has restricted this usage.

The Resources button pops up a menu that includes access to the Lab-Volt

authored Internet website. If students wish to access this site when they are not in the lesson, then they must go to http://learning.labvolt.com.

NOTE: The Lab-Volt Internet site does not have content-filtering software to block access to objectionable or inappropriate

websites.

Instructor Annotation Tool

The annotation tool gives the instructor the ability to add comments or additional information onscreen. Refer to the Tech-Lab and GradePoint 2020 Installation Guide for detailed

information.

Student Journal

The student journal is an online notebook that each student can access while they are logged into TechLab. The journal allows students to share notes with other students in their workgroups. When used in conjunction with GradePoint 2020, the instructor may post messages, review, edit, or delete any journal note.

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Assessing Progress

Assessment Tools

Student assessment is achieved in several ways:

♦ Exercise questions

♦ Unit tests

♦ Pretest and Posttest

♦ Troubleshooting questions

Exercise and Troubleshooting Questions

Throughout the unit material, exercise discussion, exercise procedure, and troubleshooting sections there are several types of questions with instant feedback. These questions occur in the following formats:

♦ Multiple choice

♦ True-false

♦ Real-number entry

In most cases, when your students encounter a question set, they must answer these questions before continuing. However, there are cases where students may progress to the next screen without answering the questions. Lab-Volt recommends that you encourage your students to complete all questions. In this way, students reinforce the material that's presented, verify that they understand this material, and are empowered to decide if a review of this material is required.

Review Questions

At the end of each exercise, there are review questions. The student receives feedback with each entry. Feedback guides the student toward the correct answer.

Unit Tests

A unit test appears at the end of each unit. The test consists of 10 multiple-choice questions with the option of having feedback. The Tech-Lab System defaults to no feedback, but the instructor

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Pretest and Posttest

Every course includes a pretest and a posttest. These are multiple choice tests. Refer to the Tech Lab Quick-Start Guide for detailed information on how to record student competency gains.

Grading

Student grades are based on exercise questions, troubleshooting questions, a unit test, and a posttest. The default weighting value of the unit test and the threshold for passing the unit test can be adjusted by using the Global Configurator of the Tech-Lab System. Refer to the Tech Lab Quick-Start Guide for detailed information.

Student Progress and Instructor Feedback

Unit progress is available through the Unit menu. The Progress window allows the instructor and student to view the percentage of the unit completed, number of sessions, and time spent on that unit. The Progress window shows whether the Unit Test was completed. If the test was

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Real-Number Questions and Answers

Throughout FACET courses students may encounter real-number questions such as the one shown below. Answers to real-number questions are graded correct if they fall within an acceptable tolerance range.

The answer to the question posed in the illustration above does not involve a recall value from a previous question. It appears in the Instructor Guide (IG) as shown in the box below.

The information in the IG tells you where the question is located and the range of acceptable answers. In this case, the acceptable answers fall within the range of the nominal answer plus or minus 5 percent tolerance: (15 ± 5%).

Location: Exercise Procedure page: se1p1, Question ID: e1p1a

VS = Vdc

Recall Label for this Question: V1 Nominal Answer: 15.0

Min/Max Value: (14.25) to (15.75) Value Calculation: 15.000

This is the name the computer uses internally to identify the input value. In this case, 14.5 will be stored under the name V1.

NOTE: The recall value V1 is not the same as the voltage V₁. The recall label does not appear onscreen.

In this case, the answer to this question is not based on a value recalled from a previous e1p1 stands for

Exercise 1 Procedure screen 1 The computer

saves this input value so that it can be recalled for use in later questions.

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A second example (shown below) illustrates an answer that the computer grades using a value recalled from a previous question.

When a real-number question is based on a recall value from a previous question, the Min/Max Value shown in the Instructor Guide is based upon a calculation using the lowest and highest possible recall value. It represents the theoretical range of answers that could be accepted by the computer. (It is not the nominal answer plus or minus the tolerance.)

To find the actual range of answers that the computer will accept onscreen, you must use the actual recall value (14.5 in this example) in your calculations; see below.

NOTE: After four incorrect answers, students will be prompted to press <Ins> to insert the correct answer if this feature has been enabled in the configuration settings. When the question is based on a value recalled from a previous question, answers obtained using the Insert key may not match the nominal answers in this guide.

Location: Exercise Procedure page: se1p5, Question ID: e1p5c

IT = mA

Recall Label for this Question: I1 Nominal Answer: 9.091

*_{Min/Max Value: (6.477) to (11.93)} Value Calculation: #V1#/1650*1000 Correct Tolerance Percent = true Correct Minus Tolerance = 25 Correct Plus Tolerance = 25

Since the value for #V1# is 14.5, the computer will accept answers in the following range as correct:

14.5/1650*1000 ± 25% or 8.79 ± 25% or

6.59 to 10.99

This calculated range is different from the Min/Max Value shown in the IG, which was based upon a calculation using the lowest and highest possible recall value. Any letter enclosed in "#" signs refers to a recall value from a previous question.

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Recall Values in Text

Sometimes numbers displayed on screen are values recalled from input on previous screens. Because these numbers are recall values, they will change for each student.

The Instructor Guide lists the recall label in place of a number in this question. The value of 10

wasrecalled from a previous screen.

Location:Exercise Procedure page: se1p11, Question ID: e1p11c IR2 = VR2/R2

= #V4#/3.3 kΩ = mA

Recall Label for this Question: I1 Nominal Answer: 2.818

Min/Max Value: (2.489) to (3.164) Value Calculation: #V4#/3.3 Correct Tolerance Percent = true Correct Minus Tolerance = 4 Correct Plus Tolerance = 4 This is a recall label for a value recorded in a previous question. The correct answer will depend on the value the student recorded in the previous question.

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Safety

Safety is everyone’s responsibility. All must cooperate to create the safest possible working environment. Students must be reminded of the potential for harm, given common sense safety rules, and instructed to follow the electrical safety rules.

Any environment can be hazardous when it is unfamiliar. The FACET computer-based

laboratory may be a new environment to some students. Instruct students in the proper use of the FACET equipment and explain what behavior is expected of them in this laboratory. It is up to the instructor to provide the necessary introduction to the learning environment and the

equipment. This task will prevent injury to both student and equipment.

The voltage and current used in the FACET Computer-Based Laboratory are, in themselves, harmless to the normal, healthy person. However, an electrical shock coming as a surprise will be uncomfortable and may cause a reaction that could create injury. The students should be made aware of the following electrical safety rules.

1. Turn off the power before working on a circuit.

2._{Always confirm that the circuit is wired correctly before turning on the power. If required,} have your instructor check your circuit wiring.

3. Perform the experiments as you are instructed: do not deviate from the documentation. 4._{Never touch “live” wires with your bare hands or with tools.}

5._{Always hold test leads by their insulated areas.}

6._{Be aware that some components can become very hot during operation. (However, this is not} a normal condition for your F.A.C.E.T. course equipment.) Always allow time for the

components to cool before proceeding to touch or remove them from the circuit. 7._{Do not work without supervision. Be sure someone is nearby to shut off the power and}

provide first aid in case of an accident.

8._{Remove power cords by the plug, not by pulling on the cord. Check for cracked or broken} insulation on the cord.

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UNIT OBJECTIVE

Locate and describe the various components on your circuit board, and demonstrate basic trainer functions.

UNIT FUNDAMENTALS

Location: Unit Fundamentals page: sf3, Question ID: f3a

What other system components can communicate with the CPU in your computer via I/O devices?

a. printer b. mouse c. disk drive

d. all of the above.

Location: Unit Fundamentals page: sf5, Question ID: f5a maximum # =

Recall Label for this Question: None Nominal Answer: 65536.0 Min/Max Value: (65536) to (65536) Value Calculation: 65536.000 Correct Tolerance Percent = true Correct Minus Tolerance = 0 Correct Plus Tolerance = 0

Location: Unit Fundamentals page: sf7, Question ID: f7a Which of these is an input device?

a. keypad b. LCD display c. LEDs CMS AVAILABLE None FAULTS AVAILABLE None

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NEW TERMS AND WORDS

data bus - a group of bidirectional lines used for transferring data between a microprocessor and memory or I/O devices.

address bus - a group of output signals from a microprocessor used for specifying a location in which data is to be read or written.

registers - a temporary storage area inside a microprocessor that holds system status information, results of calculations, and other values.

monitor - a program that performs system initialization functions and allows interaction between the CPU and the user.

Programmable Peripheral Interface (PPI) - a support IC that manages data transfers between the CPU and several external devices.

interrupt - an operation in which the CPU stops what it is doing and saves its place in the program to perform another task. When the task is completed, the CPU returns to its former place in the program.

Programmable Interrupt Controller - a support IC that manages interrupt signals from several external devices.

bus cycle - a complete data transfer cycle, including a bus request from the microprocessor and a response from an external device.

physical address - the address that the CPU places on the address bus.

logical address - an eight-digit representation of the physical address, written in the form AAAA:BBBB (segment:offset).

segment - a 64 Kbyte section of memory.

offset - the distance (in bytes) of a given location from the segment base. segment base - the first address in a segment.

function mode - a keypad operating mode that exists when you reset the CPU.

memory mode - a keypad operating mode that allows you to view or change memory bytes. Mnemonic - an abbreviated form of an instruction that is written in a way that makes it easy to recall the function.

assembly language - a programming language that uses words, statements, and phrases to produce CPU instructions.

loop - a series of instructions that repeats itself continuously or for a specific number of times. microprocessor - a computer element that contains the control unit, central processing circuitry, and arithmetic and logic functions; also called the Central Processing Unit (CPU).

logic probe - a device for digital troubleshooting and signal tracing that has LEDs to indicate logic levels and pulse activity.

programs - a series of instructions stored in memory to be executed or carried out by a microprocessor.

byte - a group of eight bits transferred or operated on as a unit.

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EQUIPMENT REQUIRED F.A.C.E.T. base unit

Multimeter

Oscilloscope, dual trace

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Exercise 1 – Introduction to the Trainer

EXERCISE OBJECTIVE

Locate and describe the various components and circuit blocks on the 32-BIT MICROPROCESSOR circuit board.

EXERCISE DISCUSSION

Location: Exercise Discussion page: se1d4, Question ID: e1d4a

There are three headers in the CPU block: JP1, JP2, and JP3. Which header has the fewest pins? a. JP1

b. JP2 c. JP3

d. All have the same number of pins.

Although JP1 and JP2 both have 32 signal connections, there are 34 pins on each header. By looking at the CPU circuit block, you can determine that two pins on each header are

a. ground connections. b. VCC connections. c. not used.

Memory/Input-Output# (M/IO#) distinguishes between memory and I/O operations. What logic level indicates a memory operation?

a. 0 b. 1

Location: Exercise Discussion page: se1d9, Question ID: e1d9a Which memory block does not have headers?

a. MONITOR ROM b. USER ROM

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Location: Exercise Discussion page: se1d12, Question ID: e1d12a What other circuit block has a clock oscillator?

a. CPU

b. MONITOR ROM c. BUS CONTROL

Location: Exercise Discussion page: se1d14, Question ID: e1d14a number of codes =

Recall Label for this Question: None Nominal Answer: 16.0

Min/Max Value: (16) to (16) Value Calculation: 16.000 Correct Tolerance Percent = true Correct Minus Tolerance = 0 Correct Plus Tolerance = 0

Location: Exercise Discussion page: se1d15, Question ID: e1d15a Which of these ports can be used as an output port?

a. Port B b. Port C

c. Both of the above.

You can use a shunt on the 3-pin header to select an output voltage range of 0 - 10 Vdc or 0 - 2.56 Vdc. Which range is selected in the figure?

a. 0 - 10 Vdc b. 0 - 2.56 Vdc

Both the ADC and DAC blocks have jacks for an external analog connection (ADC IN and DAC OUT). In which other circuit block are these signals available?

a. SERIAL PORT b. PARALLEL PORT c. CPU

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You can use a shunt to connect one of the top pins to the interrupt input directly below it to allow the other circuit block(s) to interrupt the CPU. Which signal can be shunted to IR4?

a. INTRA b. INTRB c. RXC d. DR#

Which circuit block loses power when the PWR switch is in its down position? a. only the CPU block

b. only the POWER SUPPLY block c. all circuit blocks

Location: Exercise Discussion page: se1d24, Question ID: e1d24a Which hexadecimal key can also be used for the READ function? a. 1

b. 7 c. C d. F

Location: Exercise Discussion page: se1d28, Question ID: e1d28a What binary number is shown on address LEDs A0-A7?

a. 1010 0110 b. 1110 0111 c. 0001 1000

Location: Exercise Discussion page: se1d28, Question ID: e1d28c The LEDs are arranged in groups of four because

a. the CPU transfers four bits at a time.

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How many digits of hexadecimal information can you view in each LED block? a. 4

b. 8 c. 16

Location: Exercise Discussion page: se1d31, Question ID: e1d31a What is the complete hex value shown on the data LEDs?

a. E098 D26A b. D26A E098 c. A62D 890E

EXERCISE PROCEDURE

What message does the CPU display on the LCD to let you know it is ready for operation? a. "Read Address?"

b. "Lab-Volt 32 bit µPROC. Trainer"

1. Aside from the PWR LED, what indication(s) tell you that power is applied to your circuit board?

a. address and data LEDs on b. logic probe LED on c. Both of the above.

Location: Exercise Procedure page: se1p9, Question ID: e1p9c What message appears in the LCD display?

a. "Lab-Volt 32 bit µPROC. Trainer" b. "Read Address?"

c. Neither of the above.

Location: Exercise Procedure page: se1p9, Question ID: e1p9e

Why hasn't the startup message "Lab-Volt 32 bit µPROC. Trainer" appeared? a. The CPU is in single cycle mode.

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Location: Exercise Procedure page: se1p12, Question ID: e1p12a In which circuit block is JP3 located?

a. PARALLEL PORT b. CPU

c. IR CONTROLLER

Does the waveform on the scope match the top waveform (BS16#) shown in the figure? a. yes

b. no

Location: Exercise Procedure page: se1p14, Question ID: e1p14a Which CH 2 connection results in the bottom waveform shown in the figure? a. BE0#

b. BE1# c. BE2# d. BE3#

If a pulsing waveform is not symmetrical, the HIGH and LOW LED brightness levels are different. For which type of waveform is the HIGH LED brighter than the LOW LED? a. repeating high pulse

b. repeating low pulse

Location: Exercise Procedure page: se1p19, Question ID: e1p19a According to the logic probe, what type of signal is UROMS#?

a. high level b. low level c. square wave

Location: Exercise Procedure page: se1p20, Question ID: e1p20a Which signal is a repeating low pulse?

a. L0 b. L1 c. L2

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Location: Exercise Procedure page: se1p21, Question ID: e1p21a What can you conclude from the waveform and the logic probe indications? a. The LEDs indicate a different waveform type than the one shown on the scope. b. The LEDs indicate the same waveform type as the one shown on the scope. Location: Exercise Procedure page: se1p23, Question ID: e1p23a

The logic probe indicates that ADS# is a. at a high level.

b. at a low level. c. pulsing.

23. Turn on the SINGLE CYCLE switch. What indications show that the CPU is now in the single cycle mode?

a. ADS# has stopped pulsing.

b. The address and data LEDs have all assumed a steady on or off level. c. Both of the above.

24. Observe the logic probe LEDs as you press STEP several times. What happens as you press STEP?

a. The ADS# level alternates between high and low with each step. b. A short pulse appears on the PULSE LED with each step. c. Both of the above.

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REVIEW QUESTIONS

Location: Review Questions page: se1r1, Question ID: e1r1

1. What step(s) must you perform to start up the 32-BIT MICROPROCESSOR circuit board? a. Set the control switches to their correct initial conditions.

b. Make sure the CPU is in the run mode.

c. Set some of shunts to their correct initial conditions. d. All of the above.

Location: Review Questions page: se1r2, Question ID: e1r2 2. What type of waveform is indicated by the logic probe LEDs? a. high level

b. low level

c. repeating high pulse d. repeating low pulse

Location: Review Questions page: se1r3, Question ID: e1r3 3. In which circuit block can you monitor the signal INTRA? a. IR CONTROLLER

b. CPU

c. PARALLEL PORT d. SERIAL PORT

4. When the CPU starts up in the run mode, you cannot read the address and data LEDs because a. the wrong information is displayed.

b. the information is constantly changing. c. the STEP switch has not been pressed. d. the LEDs are turned off.

5. Which circuit block synchronizes control signals between the CPU and its support circuitry? a. DAC

b. ADC

c. BUS CONTROL d. PARALLEL PORT

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CMS AVAILABLE None

FAULTS AVAILABLE None

(40)

Exercise 2 – Operating the Trainer

EXERCISE OBJECTIVE

Perform the basic keypad functions of the 32-BIT MICROPROCESSOR circuit board. Verify results by reading the data and prompts on the LCD display.

EXERCISE DISCUSSION

Location: Exercise Discussion page: se2d1, Question ID: e2d1a How many hexadecimal digits correspond to 20 binary bits?

a. 4 b. 5 c. 8

Location: Exercise Discussion page: se2d4, Question ID: e2d4a What other logical address also equals the physical address 04050? a. 0402:0030

b. 0403:0020 c. 0200:2050 d. All of the above.

Location: Exercise Discussion page: se2d5, Question ID: e2d5a Which hexadecimal keys correspond to these functions?

a. 1,2,3,4 b. C,D,E,F c. 3,A,9,C

Location: Exercise Discussion page: se2d7, Question ID: e2d7a In which form should you enter the address?

a. physical b. logical

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Location: Exercise Discussion page: se2d8, Question ID: e2d8a What is the physical address of the byte AA?

a. FFC04 b. FFC05 c. FFC06 d. FFC07

Location: Exercise Discussion page: se2d10, Question ID: e2d10a How many registers can you select?

a. 8 b. 16

Location: Exercise Discussion page: se2d14, Question ID: e2d14a How many bits do the CS and IP registers contain?

a. 8 b. 16 c. 32

Location: Exercise Discussion page: se2d15, Question ID: e2d15a Which of these registers contains 32 bits of information?

a. SS b. ESP

Location: Exercise Discussion page: se2d17, Question ID: e2d17a What other function is associated with this key?

a. auto b. read c. step

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EXERCISE PROCEDURE

Location: Exercise Procedure page: se2p2, Question ID: e2p2a 2. Press <READ>. What message appears in the LCD display? a. Lab-Volt 32 bit µProc. Trainer

b. Read Address? c. Goto Address?

The display shows the address as 04000 instead of 00004000 because you entered a a. logical address and the display shows a physical address.

b. physical address and the display shows a logical address.

The 11 appears in the first byte position. The second byte did not change because a. you can enter only one byte at a time by using the WRT key.

b. RESET must be pressed before another byte is entered.

Location: Exercise Procedure page: se2p5, Question ID: e2p5a What happens when you enter the last digit?

a. All the bytes you entered are shown in the display.

b. The display shows eight different bytes beginning at address 04008. Location: Exercise Procedure page: se2p5, Question ID: e2p5c 5. Which key is more efficient to use if you need to enter a long program? a. AUTO

b. WRT

Location: Exercise Procedure page: se2p10, Question ID: e2p10a What instruction byte is located at address FFC14?

a. A3 b. 04 c. 50

(43)

Location: Exercise Procedure page: se2p12, Question ID: e2p12a What instruction code has the mnemonic, mov ebx ds:[5004H]

a. 66 8B 1E 00 50 b. 66 8B 1E 04 50 c. EB E9

Location: Exercise Procedure page: se2p15, Question ID: e2p15a What key can you press to view the next eight bytes?

a. FFWD b. FWD c. FBACK

You have stepped to address FFC0B in the single instruction mode. What address will be displayed if you press the STEP key once?

a. FFC0C b. FFC0F c. FFC0E

The CS-IP register pair forms a logical address consisting of a segment base (CS) and an offset (IP). What is the physical address for the register contents shown?

a. FFF00 b. FFFF0 c. FFFFF

Location: Exercise Procedure page: se2p26, Question ID: e2p26a What information is contained in the CS-IP register pair?

a. the logical address FFC0:000B

b. the address of the next instruction to be fetched c. Both of the above.

21. Press <EXIT> to cancel the register mode. What address now appears in the display? a. FFC0B

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You can verify this by checking the register contents. Which register key should you use to view the contents of EAX?

a. (BP-FL) b. (CS-IP) c. (A-B)

Location: Exercise Procedure page: se2p35, Question ID: e2p35a Which figure matches the contents of the LCD display?

a. A b. B c. C

Which mode can you use to verify that the CPU has copied the EAX register contents to the memory location?

a. register mode b. memory mode

Location: Exercise Procedure page: se2p37, Question ID: e2p37c 31. Press <READ> and enter the memory address 0000:5000.

a. The contents of EAX have been copied to memory address 05000H. b. The contents of EAX have not been copied to memory address 05000H.

(45)

REVIEW QUESTIONS

Location: Review Questions page: se2r1, Question ID: e2r1 1. Which key(s) can you use to enter data into memory?

a. WRT b. AUTO

c. Both of the above. d. None of the above.

2. Which register pair always contains the address of the next instruction that the CPU will fetch?

a. A-B b. C-D c. SI-DI d. CS-IP

Location: Review Questions page: se2r3, Question ID: e2r3 3. Press <REG> and select <(A-B)>. What number does EAX contain? a. 33333333H

b. CCCCCCCCH c. 00000000H d. FFFFFFFFH

4. Each time you press the FFWD key, the first byte in the display (after the address) represents a. the first byte of the next instruction.

b. the contents of the CS-IP registers.

c. every eighth byte in the program listing. d. None of the above.

5. Which key would not be used to change the contents of a CPU register? a. REG

b. FWD c. WRT d. STEP

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CMS AVAILABLE CM 2

FAULTS AVAILABLE FAULT 1

(47)

UNIT TEST

Location: Unit Test Question page: sut1, Question ID: ut1 Which of the following is not used to view memory addresses? a. HIGH/LOW data LED switch

b. HIGH/LOW address LED switch c. address LEDs

d. LCD display

Location: Unit Test Question page: sut2, Question ID: ut2 Which circuit block accepts an analog input?

a. SERIAL PORT b. PARALLEL PORT c. ADC

d. DAC

Location: Unit Test Question page: sut3, Question ID: ut3 The IR CONTROLLER circuit block manages the CPU's a. internal registers.

b. internal ROM. c. interrupt signals. d. input rate.

Location: Unit Test Question page: sut4, Question ID: ut4 Which circuit block(s) can contain memory devices?

a. RAM

b. USER ROM c. MONITOR ROM d. All of the above.

Location: Unit Test Question page: sut5, Question ID: ut5

What indication would appear on the logic probe LEDs each time you press the STEP switch? a. constant high level

b. constant low level c. constant pulsing d. single pulse

(48)

Location: Unit Test Question page: sut6, Question ID: ut6 Which key can you use to execute a program stored in memory? a. READ

b. GO c. STEP d. REG

Location: Unit Test Question page: sut7, Question ID: ut7 When the CPU in the trainer operates in the real mode,

a. the addressable memory space is 1 Mbyte. b. only 20 of the 32 address lines are used.

c. any memory location can be represented by its five-digit physical address. d. All of the above.

Which of the following logical addresses has a physical address of 12345H? a. 1234:0005

b. 1234:0050 c. 1234:0500 d. 1234:5000

Which of the following physical addresses has a logical address of 1122:3344? a. 14564H

b. 11223H c. 11224H d. 44660H

Location: Unit Test Question page: sut10, Question ID: ut10 Which key is used to leave the register mode?

a. GO b. READ c. EXIT d. STEP

(49)

U

NIT

2 –

B

US

O

PERATIONS

UNIT OBJECTIVE

Understand the basic data transfer operations of the 80386 microprocessor.

UNIT FUNDAMENTALS

Location: Unit Fundamentals page: sf1, Question ID: f1a Which bus is bidirectional?

a. data bus b. address bus

First, the CPU activates the address bus. What information appears on the address lines? a. data to be read

b. data to be written

c. the location for which data is to be written or read Location: Unit Fundamentals page: sf3, Question ID: f3a

The CPU then looks for a response from the external device. According to the flow diagram, what does the CPU do if a response is not received?

a. proceeds to the next step b. waits for a response

Location: Unit Fundamentals page: sf3, Question ID: f3c What is the direction of data flow for a read cycle?

a. from the CPU to an external device. b. from an external device to the CPU.

Instructions from memory are continuously transferred to the CPU. Each transfer requires a a. read cycle.

(50)

Location: Unit Fundamentals page: sf5, Question ID: f3c

Instructions for the 80386 microprocessor may be up to 32 bits wide. How many hex digits are needed to represent 32 binary bits?

a. 4. b. 8. c. 16. CMS AVAILABLE None FAULTS AVAILABLE None

(51)

NEW TERMS AND WORDS

microprocessor - a computer element that contains the control unit, central processing circuitry, and arithmetic and logic functions; also called Central Processing Unit (CPU).

bus cycle - a complete data transfer cycle including a bus request from the micropocessor and a response from an external device.

read cycle - a bus cycle during which a memory or I/O device transfers data to the microprocessor.

data bus - a group of bidirectional lines used for transferring data between a microprocessor and memory or I/O devices.

address bus - a group of output signals from a microprocessor used for specifying a device and location where data is to be read or written.

write cycle - a bus cycle during which the microprocessor transfers data to a memory or Input/Output (I/0) device.

programs - series of instructions stored in memory to be executed or carried out by the microprocessor.

idle state - a period during which a microprocessor is not requesting a bus cycle. byte - a group of eight bits transferred or operated on as a unit.

word - a group of bits transferred or operated on as a unit; often specifically refers to a group of 16 bits.

doubleword - a group of 32 bits transferred or operated on as a unit.

doubleword boundaries - the starting addresses of 32-bit memory locations. The starting address must be an integral multiple of four.

aligned transfers - transfers involving data that does not overlap a doubleword boundry. misaligned transfer - a 16-, 24-, or 32-bit transfer that overlaps a doubleword boundry. wait state - a period during which a microprocessor is waiting for a response from a slower device.

EQUIPMENT REQUIRED F.A.C.E.T. base unit

Oscilloscope, dual trace

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Exercise 1 – Bus States

EXERCISE OBJECTIVE

Understand the bus states that allow the 80386 microprocessor to communicate with memory and Input/Output (I/O) devices. Verify results by using an oscilloscope and by loading and executing a simple program in the 32-BIT MICROPROCESSOR circuit board.

EXERCISE DISCUSSION

Location: Exercise Discussion page: se1d1, Question ID: e1d1a How many CLK2 cycles occur within one cycle of CLK?

a. 1 b. 2 c. 1/2

Location: Exercise Discussion page: se1d3, Question ID: e1d3a Which of these lines are inputs to the CPU?

a. status b. control

When the microprocessor issues valid address information, it activates ADS#. The ADS# line is active for the

a. entire bus cycle. b. T1 state only. c. T2 state only.

Location: Exercise Discussion page: se1d7, Question ID: e1d7a RDY# is shown as a don't care condition during T1 because

a. ADS# is inactive.

b. the CPU has not yet sampled RDY#. c. READY# has not yet become active.

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Compare the timing diagram to the flow diagram. Which path is taken out of the decision box? a. NO path

b. YES path

The 80386 microprocessor's wait states allow it to interface with external devices that are a. faster than the CPU.

b. slower than the CPU.

c. either faster or slower than the CPU.

Location: Exercise Discussion page: se1d10, Question ID: e1d10a Which path out of the decision box corresponds to a wait state?

a. YES path b. NO path

Location: Exercise Discussion page: se1d11, Question ID: e1d11a What causes a wait state to terminate?

a. three consecutive T2 states

b. a RDY# input from memory or I/O c. a RDY# output from the microprocessor

If RDY# is inactive during the T2 state, the CPU executes another T2. This condition is a(n) a. idle state.

b. wait state.

Location: Exercise Discussion page: se1d12, Question ID: e1d12c

What state occurs after T2 if RDY# is active and a bus request is not pending? a. T1

b. T2 c. Ti

Location: Exercise Discussion page: se1d13, Question ID: e1d13a Which sequence is valid according to the state diagram?

a. T1-T2-T2-Ti b. T1-T2-T1-Ti c. T1-T1-T2-Ti d. All of the above.

(54)

EXERCISE PROCEDURE

2. Does the message shown appear in the circuit board's Liquid Crystal Display (LCD)? a. yes

b. no

Location: Exercise Procedure page: se1p5, Question ID: e1p5a 8. Does the prompt shown appear in the LCD?

a. yes b. no

Location: Exercise Procedure page: se1p6, Question ID: e1p6a 11. Does the data shown appear in the LCD?

a. yes b. no

15. Each transition of the ADS# waveform coincides with a clock transition because a. CLK is synchronized to ADS#.

b. ADS# is synchronized to CLK.

Location: Exercise Procedure page: se1p10, Question ID: e1p10a The falling edge of ADS# was chosen to trigger the oscilloscope because it a. occurs at the beginning of a bus cycle.

b. is synchronized to CLK.

c. represents the external device's response.

Location: Exercise Procedure page: se1p11, Question ID: e1p11a 17. Which part of the waveforms indicates the beginning of a bus cycle? a. a high pulse on ADS#

b. a low pulse on RDY# c. a low pulse on ADS#

(55)

Location: Exercise Procedure page: se1p11, Question ID: e1p11c 18. At which clock cycle does a bus cycle begin?

a. CLK cycle 1 b. CLK cycle 4 c. CLK cycle 7 d. All of the above.

Location: Exercise Procedure page: se1p11, Question ID: e1p11e

19. The low ADS# pulses are identified here as T1 states. When does a bus cycle terminate? a. immediately when RDY# goes low

b. when RDY# is sampled low at the end of T2

The CPU samples the RDY# line at the end of every T2. What is the state of RDY# during CLK cycle 2?

a. active b. inactive

Location: Exercise Procedure page: se1p16, Question ID: e1p16a 20. Where is the wait state in bus cycle 2?

a. CLK cycle 4 b. CLK cycle 5 c. CLK cycle 6

Location: Exercise Procedure page: se1p16, Question ID: e1p16c 21. Which CLK cycles in bus cycle 3 are wait states?

a. CLK cycle 9 b. CLK cycle 10 c. Both of the above.

(56)

REVIEW QUESTIONS

1. What can you use to identify all the types of CPU bus states (T1, T2, Ti, or wait)? a. address and data bus information

b. ADS# and RDY# c. ADS# only

d. RDY# only

2. You can cause additional wait states to be added to each bus cycle by pressing <CM> to toggle CM 12 on and off. How many total wait states are in the first bus cycle when CM 12 is on?

a. 1 b. 2 c. 3 d. 4

3. Which area highlighted on the state diagram represents a CPU wait state? a. A

b. B c. C

d. None of the above.

4. Which step in the flow diagram corresponds to the activation of ADS#? a. Send Address

b. Send Read Signal c. Signal Address Valid d. External Device Response

Location: Review Questions page: se1r5, Question ID: e1r5 5. Every bus cycle begins when ADS# goes low and ends

(57)

CMS AVAILABLE CM 12 TOGGLE

(58)

Exercise 2 – 32-Bit Bus Transfers

EXERCISE OBJECTIVE

Demonstrate data transfers on the 32-BIT MICROPROCESSOR circuit board. Verify results with an oscilloscope.

EXERCISE DISCUSSION

Location: Exercise Discussion page: se2d2, Question ID: e2d2a How many bytes make up a doubleword?

a. 2 b. 4 c. 8

What logic levels would be present at the byte enable outputs (BE3# through BE0#) if the CPU were to only output bytes 0 and 1?

a. 0011 b. 1100

Location: Exercise Discussion page: se2d4, Question ID: e2d4a Which data bits are transferred if only BE1# and BE2# are low? a. D0 through D15

b. D8 through D23 c. D16 through D31

Location: Exercise Discussion page: se2d5, Question ID: e2d5a What is the byte address of byte 3 at doubleword address 0008H? a. 0008H

b. 0011H c. 000BH

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Location: Exercise Discussion page: se2d6, Question ID: e2d6a Which combinations cannot be used for a 16-bit transfer?

a. 3-1 b. 3-0 c. 2-0

d. All of the above.

The CPU needs two bus cycles to complete a misaligned transfer. Why are two bus cycles required?

a. Twice as much data is transferred.

b. One bus cycle is needed for each doubleword address. c. The CPU must compensate for slower memory devices.

The D/C# (Data Control#) output is high for data transfers and low for instruction (control) transfers. For what type(s) of transfers can D/C# be low?

a. read cycles b. write cycles

c. read or write cycles

What size group of data bits cannot be transferred in one bus cycle in the 16-bit mode? a. byte

b. word

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EXERCISE PROCEDURE

Location: Exercise Procedure page: se2p2, Question ID: e2p2a 2. Does the prompt shown appear in the LCD?

a. yes b. no

6. To verify your data, press RESET, and then press <READ>. Enter address "0000:5000", and verify that the data is 66 C7 06 00 70 FF FF FF. Press <FFWD> to view the second field, and verify that the first line reads FF EB F5. Is all the data correct?

a. yes b. no

If the microprocessor were to transfer data from memory area 5000H to memory area 7000H, which address bit would change?

a. A12 b. A13 c. A14 d. A15

Location: Exercise Procedure page: se2p10, Question ID: e2p10a What do the falling edges of ADS# represent?

a. the end of a bus cycle

b. the beginning of a bus cycle

Location: Exercise Procedure page: se2p10, Question ID: e2p10c What can you conclude from the waveforms?

a. Bus cycles occur only when A13 is low. b. No data is transferred while A13 is high. c. One bus cycle occurs while A13 is high.

(61)

Since the transferred data does not overlap doubleword boundaries, this is an aligned transfer. This transfer requires

a. four bus cycles because there are four bytes. b. two bus cycles because there are two words.

c. one bus cycle because only one doubleword location is addressed. Location: Exercise Procedure page: se2p13, Question ID: e2p13a

12. Move the channel 2 probe to each of the other outputs, BE1#, BE2#, and BE3#. Which of these is high while A13 is high?

a. BE1# b. BE2# c. BE3# d. None

Location: Exercise Procedure page: se2p13, Question ID: e2p13c All four byte enables are low during the high portion of A13 because a. there is an aligned transfer.

b. there is a misaligned transfer.

c. the transfer involves all 32 data bits in one bus cycle.

Location: Exercise Procedure page: se2p18, Question ID: e2p18a Do the scope traces appear as shown?

a. yes b. no

Location: Exercise Procedure page: se2p18, Question ID: e2p18c What kind of transfer does this indicate?

a. aligned b. misaligned

Location: Exercise Procedure page: se2p20, Question ID: e2p20a Do the byte enables (BE0# and BE1#) appear as shown?

a. yes b. no

(62)

Location: Exercise Procedure page: se2p20, Question ID: e2p20c Which byte enable is active for the first bus cycle?

a. BE0# b. BE1#

A13 and ADS# are shown again for reference. Do the BE2# and BE3# signals appear as shown? a. yes

b. no

You can see that the same signal appears at BE2# and BE3#. During which bus cycle are these byte enables active?

a. first (A) b. second (B)

Based on your results, are the bytes in the higher or lower doubleword address transferred first in a misaligned transfer?

a. higher b. lower

Location: Exercise Procedure page: se2p28, Question ID: e2p28a Do the waveforms shown here appear on your oscilloscope?

a. yes b. no

The W/R# signal pulses high the same time A13 does because during the A13 pulse, a a. read operation occurs.

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You determined that while A13 is high, the data FF FF FF FF is being transferred. D/C# is high during this time because

a. FF FF FF FF is data and not an instruction. b. the transfer is misaligned.

The M/IO# output is high for the entire program loop because all transfers are between the CPU and

a. memory. b. I/O.

Location: Exercise Procedure page: se2p37, Question ID: e2p37a Output data is transferred at the highlighted time because of the

a. high level of W/R#. b. low level of M/IO#. c. Both of the above.

REVIEW QUESTIONS

1. Which signal does not provide information about the type of bus cycle? a. ADS#

b. M/IO# c. W/R# d. D/C#

Location: Review Questions page: se2r2, Question ID: e2r2 2. Which scope pattern shown here represents the byte enable signals? a. A

b. B c. C

(64)

3. The CPU is to load three bytes in an aligned transfer. Which starting address can it use? a. 7002H

b. 7003H c. 7004H

d. All of the above.

4. A three-byte misaligned transfer begins at byte address 7002H. Which byte enable is not active in either bus cycle?

a. BE0# b. BE1# c. BE2# d. BE3#

5. Which signal must be low while the CPU sends data to an I/O device? a. D/C#

b. M/IO# c. W/R#

d. All of the above. CMS AVAILABLE None

(65)

Exercise 3 – Read and Write Cycles

EXERCISE OBJECTIVE

Understand the functions of CPU read cycles and write cycles. Verify results with an oscilloscope.

EXERCISE DISCUSSION

Based on the level of the W/R# line in the timing diagram, what type of bus cycle is shown? a. read cycle

b. write cycle

c. cannot be determined

This is a timing diagram for a typical write cycle. Which signal allows you to tell a write cycle from a read cycle?

a. ADS# b. RDY# c. W/R#

Location: Exercise Discussion page: se3d3, Question ID: e3d3c According to the timing diagram, when is RDY# sampled?

a. before data becomes valid b. after data is no longer valid c. while data is valid

According to the table, what determines if a memory read cycle is a memory code read or a memory data read?

a. the direction of data flow b. the D/C# signal

(66)

EXERCISE PROCEDURE

Location: Exercise Procedure page: se3p3, Question ID: e3p3a Does the LCD appear as shown?

a. yes b. no

Location: Exercise Procedure page: se3p6, Question ID: e3p6a Do your waveforms appear as shown here?

a. yes b. no

Location: Exercise Procedure page: se3p6, Question ID: e3p6c The CPU is writing data for

a. one bus cycle. b. five bus cycles.

The ADS# and W/R# signals are shown in a different color for timing reference only. Do the M/IO# and D/C# waveforms appear on your scope as shown here?

a. yes b. no

Location: Exercise Procedure page: se3p8, Question ID: e3p8c Which section consists of I/O data read cycles?

a. B b. C

Location: Exercise Procedure page: se3p8, Question ID: e3p8e What cycle type is executed in section B?

a. memory code read b. memory data read c. memory data write

(67)

Location: Exercise Procedure page: se3p14, Question ID: e3p14a Are your waveforms similar to those shown here?

a. yes b. no

The transitions on ADS# represent all the bus cycles in a program loop. Are most of the bus cycles read or write cycles?

a. read b. write

The ADS# and W/R# signals are shown in a different color for reference. Do the M/IO# and D/C# waveforms on your scope appear as shown here?

a. yes b. no

Location: Exercise Procedure page: se3p16, Question ID: e3p16c The steady high level on M/IO# means that all the bus cycles are a. read cycles.

b. I/O cycles. c. memory cycles.

According to the figure and the table shown in the help window (click on Help), section A is a memory

a. code read. b. data read. c. data write.

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Location: Exercise Procedure page: se3p17, Question ID: e3p17c In which remaining section does the CPU fetch instructions?

a. B b. C

Location: Exercise Procedure page: se3p17, Question ID: e3p17e What type of cycle is executed in section C?

a. memory code read b. memory data read c. memory data write

REVIEW QUESTIONS

1. What signal can you use to distinguish a read cycle from a write cycle? a. M/IO#

b. D/C# c. W/R# d. Any of these

2. You can use this table to determine the nature of a bus cycle by reading the status signal levels a. within that cycle.

b. only during T1 states. c. only during T2 states. d. None of the above.

Location: Review Questions page: se3r3, Question ID: e3r3a Do the scope waveforms appear as shown here?

a. yes b. no

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Location: Review Questions page: se3r3, Question ID: e3r3 3. What type of cycle occurs in the highlighted area?

a. I/O data read b. memory data write c. memory data read d. cannot be determined

Location: Review Questions page: se3r4, Question ID: e3r4a Do the W/R# and M/IO# waveforms appear as shown?

a. yes b. no

Location: Review Questions page: se3r4, Question ID: e3r4 4. What type of cycle occurs in the highlighted area?

a. I/O data read b. memory code read c. memory data read d. memory data write

Location: Review Questions page: se3r5, Question ID: e3r5 5. An I/O code read cycle does not appear in the table because a. D/C# cannot be low in any write cycle.

b. instructions are fetched from memory, not from I/O. c. instructions are fetched from I/O, not from memory. d. None of the above.

CMS AVAILABLE None

Lab-Volt 32 Bit Microprocessor Instructors Guide

Digital and Microprocessor Electricity

32-Bit Microprocessor

Limited Warranty and Disclaimer

Table of Contents

Introduction

S

ECTION

1

–

W

ORKSTATION

I

NVENTORY

AND

I

NSTALLATION

S

1

–

W

I

I

Inventory of Workstation

Equipment Installation

Software Installation

S

ECTION

2

–

I

NTRODUCTION TO

FACET

S

2

–

I

FACET

C

Getting Started

Screen Buttons

FACET Help Screens and Resources

Internet Access

Instructor Annotation Tool

Student Journal

Assessing Progress

Real-Number Questions and Answers

Recall Values in Text

Safety

S

3

–

C

U

1

–

T

F

Exercise 1 – Introduction to the Trainer

Exercise 2 – Operating the Trainer

U

2

–

B

O

Exercise 1 – Bus States

Exercise 2 – 32-Bit Bus Transfers

Exercise 3 – Read and Write Cycles