Release Note Um180fdkmfc c02 Pb

(1)

UM180FDKMFC_C

UMC 0.18um Mixed Mode/RF CMOS

1.8V / 3.3V 1P6M Processes

Release Note

All information contained herein is subject to change without prior notice. No liability shall be incurred from its use or application.

(2)

UM180FDKMFC_C

Revision History

Revision Date Description

2.0 2002/11/29 _{Original Release}

2.1 2003/05/26 1. DFII Layer change (GT-RPT-000601-001 -> GT-RPT-030225-001) 2. Add auLvs Cellview

3. Add ivpcell Cellview

4. L_SLCR20K_RF PCell terminal bug fix 5. Modify Dynamic Link netlist for MM devices 6. Modify pin names "SUB" -> "B" for Assura 7. Modify MOS CAP pin names to "D G S B" 8. MIMCAPM_RF CSYMBOL modify for LPE issue 9. Add this layer for RFMOS source area

2.2 2003/06/18 _{Fix NCAP_MM and PCAP_MM layout}

2.3 2003/11/26 1. Add ADS, Eldo and HspiceS view on pcapacitor and presistor 2. Fix auLvs CDF settings of pcapacitor and presistor

3. MM MOS Callback supports variable input

4. Modify MM MOS terminal mapping for DC current annotation bug 5. Add IP tag information

6. Add Metal Pin Layer

7. Fixed Component description (Page 56) L_SLCR20K_RF part 8. Add in section 6.1

2.4 2004/03/17

MIMCAPS_MM bottom plate tap default value modified

2.5P1 2004/08/10 1. Fix CONT position for all MM MOS/MOSCAP for dog bone shape and the gate width equals to 0.01um multiplied by odd numbers

2. Add SEPGND layer 99(0) 3. Change VTXXX rule

4. Add hspice view on presistor and pcapacitor 5. MIMCAPM_RF pcell update to meet TLR change

6. MIMCAPM_RF, RNHR_RF, RNNPO_RF and RNPPO_RF support multiplier factor

2.6P1 2005/03/17

(3)

UM180FDKMFC_C

C01_PB 2006/12/25 1. Revision 0.18um CMOS Mixed Mode/RF FDK from

GT-DBT-021202-003 V2.6P1 to G-9FD-MIXED_MODE/RFCMOS18-1.8V/ 3.3V-1P6M-MMC/UM180FDKMFC-FDK VC01_PB.

2. Generator one signal package and include Model Files. 3. Update Interconnect Capacitance.

4. Update Calibre DRC/LVS/XRC command files. 5. Update Assura DRC/LVS/LPE command files. 6. Update technology file.

7. Modify MIMCAPM_RF callback for fix bug. 8. Update EDR.

9. Update Spice Model 10. Update TLR

11. Modify RM6 width minimum value to 1.2u for fix typo in this document. 12. Modify MIMCAPS_MM range to 1.28u ~ 100u.

C02_PB 2008/12/15 1. Removed Devices: RSND_MM RSPD_MM RSNWELL_MM RNND_MM RNPD_MM RM1_MM RM2_MM RM3_MM RM4_MM RM5_MM RM6_MM

2. Update Assura DRC & LVS command files. 3. Update Calibre DRC & LVS command files. 4. Update EDR.

5. Update TLR.

6. Updata Mask Tooling.

7. Update official layer mapping table. 8. Update Spice Model.

9. Update technology file.

10. Revised DIODE (DION_MM, DIOP_MM) for range scalable. 11. Added hspiceD view.

12. Fixed MIMCAPM_RF does not support “m=” in auCdl view. 13. Fixed bug of MIMCAPS_MM multiplier parameter in Spectre view.

(4)

UM180FDKMFC_C

14. Revised G-01 DSM number

G-01-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-DSM-8C to G-01-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-DSM

(5)

UM180FDKMFC_C

GENERAL DESCRIPTION ... 6

FDK CHECKLISTS ... 7

KNOWN PROBLEMS AND SOLUTIONS ... 13

(6)

UM180FDKMFC_C

General Description

In the front-end, we build fundamental components of UMC processes in the Cadence Composer library and simulate the circuit using Cadence Analog Design Environment. The back-end is done with the Cadence's Virtuoso custom layout editor by using parameterized cells (PCell), which includes a schematic driven layout to provide an automatic and complete design flow. Through the procedure, the designer can reduce the risk of errors.

This design flow provides excellent integration and links between process technology, device modeling, circuit front-end design and circuit back-end design. The implementation of the design flow helps the circuit designers much more efficiently designing their products. For the detailed information about FDK, please contact the customer engineers near you.

This version of FDK has passed the quality assurance checking, and the design verification has been made. It follows the information below.

(7)

UM180FDKMFC_C

FDK Checklists

Table 1. Foundry Process Documents DSM List

Classification Spec. No. Version Date Design Support Manual G-01-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-DSM 2.1_P1 2008/12/10

Electrical Design Rule G-02-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-EDR 2.1_P1 2008/10/30

Topological Layout Rule G-03-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-TLR 2.10_P1 2007/12/07

Interconnect Capacitance G-04-MIXED_MODE/RFCMOS18-1P6M-MMC-INTERCAP 1.2_P1 2006/05/10

G-05-MIXED_MODE/RFCMOS18-1.8V/3.3V-TRI_WELL/MMC-SPICE-8C 1.4_P2 2006/05/30

SPICE Modeling

G-05-MIXED_MODE/RFCMOS18-1.8V/3.3V-TWIN_WELL/MMC-SPICE-8C 1.6_P2 2008/11/20

Mask Tooling G-06-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-MASKTOOL-8C 2.6_P1 2007/03/15

G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/CALIBRE-DRC 2.10_P3 2008/09/25 DRC Rule Deck G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/ASSURA-DRC 2.10_P1 2008/05/02 G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/CALIBRE-LVS 2.1_P2 2008/12/01 LVS Rule Deck G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/ASSURA-LVS 2.1_P2 2008/12/09 G-DF-MIXED_MODE/RFCMOS18-1P6M-MMC/TOP_METAL20.6K/XRC-LPE 1.2_P1 2006/07/21

LPE Rule Deck

G-DF-MIXED_MODE/RFCMOS18-1P6M-MMC/TOP_METAL20.6K/ASSURA-LPE 1.2_P1 2006/08/24

Official Layer Mapping

Table G-DF-GENERATION18-VIRTUOSO-TF 2.10_P1 2008/01/29 NOTE:

1. The DRC rule decks included in this Design Kit are not covering all the Topological Layout Rules. Please consult your Account Manager to obtain the complete set and the latest versions of DRC rule decks before the tape-out phase.

2. The model files and rule decks included in this release Design Kit were available at the time of this revision. The user needs to obtain the latest model files and rule decks through your Account Manager.

Table 2. EDA Tools Supported and Verified for Use with this FDK

Classification EDA Tools Version

Schematic Entry Cadence Composer 5.1.41_ISR

Simulation Interface Cadence Analog Design Environment 5.1.41_ISR

Cadence Spectre 5.1.41_ISR

Simulation Tool

Synopsys Hspice 2008.03

Layout Editor Cadence Virtuoso 5.1.41_ISR

Mentor Calibre 2007.4-44.36 DRC Tool Cadence Assura 3.2.0 Mentor Calibre 2007.4-44.36 LVS Tool Cadence Assura 3.2.0 Mentor XRC 2007.4-44.36 Parasitic RC Extractor Cadence Assura 3.2.0

(8)

UM180FDKMFC_C

Table 3. Component List

Devic e T y p e Devic e Na me T e rm inals Symbol V ie w Model T y p e S pectre Netlist Hspic e Ne tlist CD L Ne tlist Layou t V iew * SDL Che ck S pectr e Sim. Hspic e Sim. DR C C h ec k L VS Chec k MOS N_18_MM 4 _V *C _{V V V V V V V V V} MOS N_33_MM 4 V *C V V V V V V V V V MOS P_18_MM 4 V *C V V V V V V V V V MOS P_33_MM 4 _V *C _{V V V V V V V V V} MOS N_BPW_18_MM 4 _V *C _{V V V V V V V V V} MOS N_BPW_33_MM 4 _V *C _{V V V V V V V V V} MOS N_LV_18_MM 4 _V *C _{V V V V V V V V V} MOS N_LV_33_MM 4 _V *C _{V V V V V V V V V} MOS P_LV_18_MM 4 _V *C _{V V V V V V V V V} MOS P_LV_33_MM 4 _V *C _{V V V V V V V V V} MOS N_ZERO_18_MM 4 V *C V V V V V V V V V MOS N_ZERO_33_MM 4 _V *C _{V V V V V V V V V} MOS N_L18W500_18_RF 4 _V *S _{V V V V V V V V V} MOS N_L34W500_33_RF 4 _V *S _{V V V V V V V V V} MOS N_PO7W500_18_RF 4 _V *S _{V V V V V V V V V} MOS N_PO7W500_33_RF 4 _V *S _{V V V V V V V V V} MOS P_L18W500_18_RF 4 _V *S _{V V V V V V V V V} MOS P_L34W500_33_RF 4 V *S V V V V V V V V V MOS P_PO7W500_18_RF 4 V *S V V V V V V V V V MOS P_PO7W500_33_RF 4 _V *S _{V V V V V V V V V} BJT _{PNP_V50X50_MM} 3 _V *C _{V V V V V V V V V} BJT _{PNP_V100X100_MM} 3 _V *C _{V V V V V V V V V} Diode DION_MM 2 _V *C _{V V V V V V V V V} Diode DIOP_MM 2 _V *C _{V V V V V V V V V} Diode DIONW_MM 2 _V *C _{V V V V V V V V V} RES RNHR1000_MM 3 V *S V V V V V V V V V RES RNNPO_MM 3 V *S V V V V V V V V V RES RNPPO_MM 3 _V *S _{V V V V V V V V V} RES RNNPO_RF 3 _V *S _{V V V V V V V V V} RES RNPPO_RF 3 _V *S _{V V V V V V V V V} RES RNHR_RF 3 _V *S _{V V V V V V V V V} CAP VARDIOP_RF 2 _V *S _{V V V V V V V V V}

(9)

UM180FDKMFC_C

CAP VARMIS_18_RF 3 _V *S _{V V V V V V V V V} CAP MIMCAPM_RF 3 _V *S _{V V V V V V V V V} CAP MIMCAPS_MM 2 _V *S _{V V V V V V V V V} CAP NCAP_MM 3 _V *S _{V V V V V V V V V} CAP PCAP_MM 3 _V *S _{V V V V V V V V V} IND L_SLCR20K_RF 3 V *S V V V V V V V V V PAD PAD_RF 2 V *S V V V V V V V V V

(10)

UM180FDKMFC_C

Table 4. FDK Component Table

Cell view Device model file UMC_DSM

Device CELL name No of symbol

terminal Name of terminals

No of model

file terminals Model range 1.8V PMOS P_18_MM 4 D, G, S, B 4 0.24u<=W<=100u 0.18u<=L<=50u 1<=Nf<=10000 1.8V NMOS N_18_MM 4 D, G, S, B 4 0.24u<=W<=100u 0.18u<=L<=50u 1<=Nf<=10000 1.8V TWELL NMOS N_BPW_18_MM 4 D, G, S, B 4 0.24u<=W<=100u 0.18u<=L<=50u 1<=Nf<=10000 1.8V Low Vt PMOS P_LV_18_MM 4 D, G, S, B 4 0.24u<=W<=100u 0.24u<=L<=50u 1<=Nf<=10000 1.8V Low Vt NMOS N_LV_18_MM 4 D, G, S, B 4 0.24u<=W<=100u 0.24u<=L<=50u 1<=Nf<=10000 1.8V Zero Vt NMOS N_ZERO_18_MM 4 D, G, S, B 4 0.24u<=W<=100u 0.3u<=L<=50u 1<=Nf<=10000 1.8V RF NMOS

(Length scalable) N_PO7W500_18_RF 4 D, G, S, B 4

W=5.0u 0.2u<=L<=0.5u

Nf=7 1.8V RF PMOS

(Length scalable) P_PO7W500_18_RF 4 D, G, S, B 4

W=5.0u 0.2u<=L<=0.5u

Nf=7 3.3V RF NMOS

(Length scalable) N_PO7W500_33_RF 4 D, G, S, B 4

W=5.0u 0.34u<=L<=0.8u

Nf=7 3.3V RF PMOS

(Length scalable) P_PO7W500_33_RF 4 D, G, S, B 4

W=5.0u 0.34u<=L<=0.8u Nf=7 1.8V RF NMOS (Nf scalable) N_L18W500_18_RF 4 D, G, S, B 4 W=5.0u L=0.18u 5<=Nf<=21 1.8V RF PMOS (Nf scalable) P_L18W500_18_RF 4 D, G, S, B 4 W=5.0u L=0.18u 5<=Nf<=21 3.3V RF NMOS (Nf scalable) N_L34W500_33_RF 4 D, G, S, B 4 W=5.0u L=0.34u 5<=Nf<=21 3.3V RF PMOS (Nf scalable) P_L34W500_33_RF 4 D, G, S, B 4 W=5.0u L=0.34u 5<=Nf<=21 3.3V PMOS P_33_MM 4 D, G, S, B 4 0.24u<=W<=100u 0.34u<=L<=50u 1<=Nf<=10000 3.3V NMOS N_33_MM 4 D, G, S, B 4 0.24u<=W<=100u 0.34u<=L<=50u 1<=Nf<=10000 3.3V Low Vt NMOS N_LV_33_MM 4 D, G, S, B 4 0.8u<=W<=100u 0.5u<=L<=50u 1<=Nf<=10000

(11)

UM180FDKMFC_C

3.3V Low Vt PMOS P_LV_33_MM 4 D, G, S, B 4 0.8u<=W<=100u 0.5u<=L<=50u 1<=Nf<=10000 3.3V Zero Vt NMOS N_ZERO_33_MM 4 D, G, S, B 4 0.8u<=W<=100u 0.5u<=L<=50u 1<=Nf<=10000 3.3V TWELL NMOS N_BPW_33_MM 4 D, G, S, B 4 0.24u<=W<=100u 0.34u<=L<=50u 1<=Nf<=10000 N+/Pwell Diode

DION_MM 2 PLUS, MINUS 2 0.94u<=W<=160u 0.94u<=L<=200u P+/Nwell Diode

DIOP_MM 2 PLUS, MINUS 2 0.94u<=W<=160u 0.94u<=L<=200u Nwell/Psub

Diode DIONW_MM 2 PLUS, MINUS 2

Emitter W=1080u Emitter L=90u P+/Nwell/PSUB PNP Bipolar Tr. (5*5) PNP_V50X50_MM 3 C, B, E 3 Emitter W=5u Emitter L=5u P+/Nwell/PSUB PNP Bipolar Tr. (10*10) PNP_V100X100_MM 3 C, B, E 3 Emitter W=10u Emitter L=10u Non-Salicide P+ Poly Resistor

RNPPO_MM 3 PLUS, MINUS, B 3 0.18u<=W<=20u 0.6u<=L<=1000u Non-Salicide

N+ Poly Resistor

RNNPO_MM 3 PLUS, MINUS, B 3 0.18u<=W<=20u 0.6u<=L<=1000u HR Poly

Resistor RNHR1000_MM 3 PLUS, MINUS, B 3

0.18u<=W<=20u 1.0u<=L<=1000u HR Poly

Resistor RNHR_RF 3 PLUS, MINUS, B 3

2u<=W<=10u 2u<=L<=100u

1<=L/W<=10 N+ Poly

Resistor RNNPO_RF 3 PLUS, MINUS, B 3

2u<=W<=10u 2u<=L<=100u

1<=L/W<=10 P+ Poly

Resistor RNPPO_RF 3 PLUS, MINUS, B 3

2u<=W<=10u 2u<=L<=100u 1<=L/W<=10 NMOS Capacitor NCAP_MM 3 D, G, B 4 0.24u<=W<=100u 0.18u<=L<=50u 1<=Nf<=10000 PMOS Capacitor PCAP_MM 3 D, G, B 4 0.24u<=W<=100u 0.18u<=L<=50u 1<=Nf<=10000 MIM Capacitor MIMCAPS_MM 2 PLUS, MINUS 2 1.28u<=W<=100u

1.28u<=L<=100u

RF MIM

capacitor MIMCAPM_RF 3 PLUS, MINUS, B 3

Single Retangle: NX=1 NY=1 10u<=W<=70u 10u<=L<=70u 1<=L/W<=6 Multi Retangle: 1<=NX<=7

(12)

UM180FDKMFC_C

1<=NY<=7 W=10u L=10u 1<=NY/NX<=6 1.8V MIS

Varactor VARMIS_18_RF 3 PLUS, MINUS, B 3 24<=Nf<=120 P+/Nwell

Junction Varactor

VARDIOP_RF 3 PLUS, MINUS, B 3 30<=Nf<=120 Spiral Inductor L_SLCR20K_RF 3 PLUS, MINUS, B 3

126u<=D<=238u 6.0u<=W<=20u

1.5<=N<=5.5 RF Pad PAD_RF 2 PLUS, PSUB 2 1<=index<=5

(13)

Release Note Um180fdkmfc c02 Pb

UM180FDKMFC_C

UMC 0.18um Mixed Mode/RF CMOS

1.8V / 3.3V 1P6M Processes

Release Note

UM180FDKMFC_C

Revision History

UM180FDKMFC_C

UM180FDKMFC_C

UM180FDKMFC_C

Table of Contents

GENERAL DESCRIPTION ... 6

FDK CHECKLISTS ... 7

KNOWN PROBLEMS AND SOLUTIONS ... 13

UM180FDKMFC_C

General Description

UM180FDKMFC_C

FDK Checklists

UM180FDKMFC_C

UM180FDKMFC_C

UM180FDKMFC_C

UM180FDKMFC_C

UM180FDKMFC_C

UM180FDKMFC_C

Known Problems and Solutions

DIODE (DION_MM, DIOP_MM)

For the backward compatibility, the diode PCells keep the fixed layout size provided in

previous FDK package as the default (W = 80um, L=100um).

Design variable does not support MOS dog-bone status.

We do not recommend user use design variable when MOS width is less than 0.48um

(dog-bone status). This function is not support in this package.

Slot rule violation of MOSCAP (NCAP_MM & PCAP_MM)

When the size of ME1 of MOSCAP is larger than 30um is 20um, it will violate the DRC rule of

metal slot (6.1A_M1). Designer should follow the slot rule and add slot manually.

The width of connection line which on L_SLCR20K_RF terminals (PLUS & MINUS).

As the width of connection lines on L_SLCR20K_RF are not coincident the width of terminals,

the DRC rule, 4.31H, will be violated. For avoid the DRC violation, user should connect to the

terminals with ME6, and the layer width must be coincident with the width of terminals.

Warning messages about layers does not defined in DFII when Assura LVS running.

When running Assura LVS flow, it shows warning message about layer (“VSTRES” “drawing”)

& (“IRAM” “drawing”) are not defined in DFII. These alerts will not impact the LVS execution,

and user can ignore it.

The resistance (“r”), capacitance (“c”) & inductance (“l”) on Calibre view.

When building calibre view, the value of “r”, “c” & “l” will be set to default value. These

parameters are for reference only and will not affect the post simulation.