Ch6. Transistor Amplifiers

▪ How the transistor (a MOSFET or a BJT) can be used to make an amplifier.

▪ How to obtain linear amplification from the fundamentally nonlinear MOS transistor.

▪ How to model the linear operation of a transistor around a bias point by an equivalent circuit that can be used in the analysis and design of transistor amplifiers.

▪ The three basic ways to connect a MOSFET or a BJT to construct amplifiers with different properties.

Ch6. Transistor Amplifiers

▪ When a MOSFET is operated in the saturation or pinch-off region, also referred to in this chapter as the active region, the voltage

between gate and source, v

, controls the drain current i

according to the square-law relationship which, for an NMOS transistor,

▪ Similarly, when a BJT is operated in the active region, the base- emitter voltage v

controls the collector current i

according to exponential relationship which, for an npn transistor,

Oxford University Publishing Microelectronic Circuits by Adel S.

Sedra and Kenneth C. Smith

1

( )

(eq6.1) i

= 2 k v

− V

(eq6.2) i

= I e

6.1.1. The Basic for Amplifier Operation

6.1.1. The Basic for Amplifier Operation

6.1.2. Obtaining a Voltage Amplifier

▪ From the above, we learned that voltage

controlled current source (VCCS) can serve as transconductance amplifier.

▪ the following slides (with blue tint) are a review

▪ Q: How can we translate current output to voltage?

▪ A: Measure voltage drop across load resistor.

out

function of input supply

(eq6. 3)

G

DS DD D D

v v

v = v − i R Figure 6.2: (a) an NMOS amplifier

example of transconductance amplifier

▪ voltage transfer characteristics (VTC) – plot of out voltage vs. input

▪ three regions exist in VTC

▪ v_GS < V_t → cut off FET

▪ v_OV = v_GS – V_t < 0

▪ I_D = 0

▪ v_DS??? v_OV

▪ v_out = v_DD

▪ V_t < v_GS < v_DS + V_t → saturation

▪ v_OV = v_GS – V_t > 0

▪ I_D = ½ k_n(v_GS – V_t)²

▪ v_DS>> v_OV

▪ v_out= V_DD – I_DR_D

▪ v_DS + V_t < v_GS < V_DD → triode

▪ v_OV = v_GS – V_t > 0

▪ I_D = k_n(v_GS– V_t – v_DS)v_DS

▪ v_DS> v_OV

▪ v_out= V_DD – I_DR_D

Figure 6.2: (b) an NMOS amplifier’s (VTC)

Or Active region

v_DS + V_t

6.1.3. Voltage Transfer Characteristic (VTC)

▪ Q: What observations may be drawn?

▪ A: Cutoff FET represents

transistor blocking, cutoff AMP represents v

= 0

▪ A: As v

increases…

▪ v

(effectively) decreases

▪ i

increases

▪ v

decreases nonlinearly

▪ gain (G) decreases

▪ A: Once v

> v

, all power is dissipated by resistor R

cutoff FET cutoff AMP

Figure 6.2: (b) an NMOS amplifier’s (VTC)

Or Active region

6.1.3. Voltage Transfer Characteristic (VTC)

▪ Cutoff FET represents transistor blocking,

▪ cutoff AMP represents v

= 0

▪ As v

increases…

▪ v

(effectively) decreases

▪ i

increases

▪ v

decreases nonlinearly

▪ gain (G) decreases

▪ Once v

> v

, all power is dissipated by resistor R

-7-

cutoff FET

cutoff AMP

Figure 5.27: (b) the voltage transfer characteristic (VTC) of the amplifier

define v

in terms of v

for saturation

( )

this is equation is simply ohm's law / KVL 2

GS

(eq5.32)

(eq5.33)

1 2

2 1 1

V

D

DS DD n GS t D

n D DD B t

n D i

v V k v V R

k R V

V k R

 

= −   −  

= + + −

point B – boundary between saturation and triode regions

linearize the VTC

biasing the MOSFET amplifier at point Qlocated on segment ABof VTC

Q

Figure 6.2: (b) an NMOS amplifier’s (VTC)

( )

this is equation is simply ohm's law / KVL 2

GS

(eq6.5)

(eq6.6)

1 2

2 1 1

V

D

DS DD n GS t D

n D DD B t

n D i

v V k v V R

k R V

V k R

 

= −   −  

= + + −

Q: How do we define v

in terms of v

for saturation?

Q: How do we define point B – boundary between saturation and triode regions?

Or Active region

6.1.3. Voltage Transfer Characteristic (VTC)

6.1.4. Obtain Linear Amplification by Biasing the Transistor

▪ Biasing enables us to obtain almost- linear amplification from the

MOSFET and the BJT.

▪ The technique is illustrated for the MOSFET case in Fig. 6.3(a).

Figure 6.3(a): Biasing the MOSFET amplofoer.

6.1.4. Obtain Linear Amplification by Biasing the Transistor

▪ Q: How can we linearize VTC?

▪ A: Appropriate biasing technique

▪ A: Dc voltage v

is selected to obtain operation at point Q on segment AB

▪ Q: How do we choose v

?

▪ A: Will discuss shortly…

( )

this equation is

2 simply ohm's law

(eq6.10) 1

2

source D D

V I R

DS DD n D GS t

V V k R V V

−

 

= −   −  

Figure 6.3(b): Biasing the MOSFET amplifier at point Q located on

segment AB of VTC

This equation differs from eq(6.8) because it considers dc component only.

function of input supply

(eq5. 30 )

G

out v

v

DS DD D D

v = v − i R

Figure 5.27: (a) simple MOSFET amplifier with input v_GSand output v_DS

example of transconductance amplifier

6.1.4. Obtain Linear Amplification by Biasing the Transistor

▪ bias point / dc operating pt. (Q) – point of linearization for MOSFET

▪ Also known as quiescent point.

▪ Q: How will Q help us?

▪ A: Because VTC is linear near Q, we may perform linear

amplification of signal << Q

Figure 6.3(b): Biasing the MOSFET amplifier at point Q located on segment AB of VTC

( )

this equation is

2 simply ohm's law

(eq6.10) 1

2

source D D

V I R

DS DD n D GS t

V V k R V V

−

 

= −   −  

6.1.4. Obtain Linear Amplification by Biasing the Transistor

linear amplification around Q in

saturation region

Figure 6.3(b): Biasing the MOSFET amplifier at point Q located on

segment AB of VTC

▪ bias point / dc operating pt. (Q) = point of linearization for MOSFET

▪ also known as quiescent point

-14-

linear amplification around Q in saturation region

#1:Bias MOSFET with dc voltage V_GS as defined by (5.34)

#2:Superimpose amplifierinput (v_gs) upon V_GS.

#3:Resultant v_dsshould be linearly proportional to small- signal component v_gs.

( ) ( )

( ) ( )

GS GS gs

ds gs

t V t

t t

− − − − − − − +

−

=

− − −



v v

v v

As long as v

(t) is small, its effect on v

(t) will be linear – facilitating linear amplification.

Figure 5.29: The MOSFET amplifier with a small time-varying signal v_gs(t)

superimposed on the dc bias voltage v_GS. The MOSFET operates on a short almost- linear segment of the VTC around the bias point Q and provides an output voltage v_ds

= A_vv_gs

▪ Q: How is linear gain achieved?

▪ step #1: Bias MOSFET with dc voltage V

as defined by (6.5)

▪ step #2: Superimpose amplifier input (v

) upon V

.

▪ step #3: Resultant v

should be linearly proportional to small-signal component v

.

( ) ( )

( ) ( )

GS GS gs

ds gs

v t V v t

v t v t

− − − −

= +



− − − − − − −

6.1.4. Obtain Linear Amplification by Biasing the Transistor

Q: How is linear gain achieved?

Figure 6.4: The MOSFET amplifier with a small time-varying signal v_gs(t) superimposed on the dc bias voltage v_GS. The MOSFET operates on a short almost-linear segment of the VTC around the bias point Q and provides an output voltage v_ds= A_vv_gs

As long as v

(t) is small, its effect on v

(t) will be linear – facilitating linear

amplification.

Q: How is linear gain achieved?

▪ step #4: Note if v

is small, output v

will be nearly linearly proportional to it.

▪ Slope will be constant.

( )

( )

( )

means that is small

replace with (6.5)

sim 1 2 2

plify

(eq6.13)

(eq6.14)

(e

(eq6.13)

GS GS

GS D

GS vgs

S

v

DS v

GS v V

DD n GS t D

GS

v V

v n GS

v

t D

A dv

dv

d V k v V R

dv

A k V V R

A





=

− −

=

= − −

action:

action:

replace with

q6.15)

OV

v n OV D

V

A = − k V R

action:

6.1.4. Obtain Linear Amplification by Biasing the Transistor

▪ Q: How is Q for VTC defined (assuming R

is fixed)?

▪ A: As point Q approaches B:

▪ gain increases

▪ maximum v

swing decreases

6.1.4. Obtain Linear Amplification by Biasing the Transistor

Note that a trade-off between gain and linear range exists.

linear range is large

gain is low

gain is high linear range is small

6.1.5. Small-Signal Voltage Gain __ The MOSFET Case

▪ Q: What observations can be made about voltage gain?

▪ A: Gain is negative.

▪ A: Gain is proportional to:

▪ load resistance (R

)

▪ transistor conductance parameter (k

)

▪ overdrive voltage (v

)

( )

( )

means that is small

replace with (6.5)

1 2

(eq6.13)

(eq6.13)

GS GS vg

S G

s

G S

DS

DS v

GS v V

D v

v

D n GS t D

GS

v V

A dv

dv

d V k v V R

A dv





=

− −

=

action:

( )

simplify

replace with

(eq6.14)

( eq6.1 ) 5

OV

v n GS t D

v n O D

V

V

A k V V R

A k V R

= − −

= −

action:

action:

▪ Equation (6.16) is another version of (6.15) which incorporates V

.

▪ It demonstrates that gain is ratio of:

▪ voltage drop across R

▪ half of over voltage

2 1 2

incorporate

(eq6.15)

(eq6.16)

(

/ 2 eq6.17) / 2

D n OV

v n OV

I k D

D D v

OV

D V

D DS

v

OV

A k V R

A I R

V

V V

A V

=

= −

 

= −  

 

= − −

action:

▪ Q: How does (6.16) relate to physical devices?

▪ A: For modern CMOS technology, v

is usually no less than 0.2V.

max

max

/ 2

since ,

DS B OV B

/ 2

DD DS B

v

OV B

DD OV B

v

OV B

V V

A V V

A

V V

V

= V

= −

= −

For example, 0.13mm CMOS technology with V

= 1.3V yields

maximum gain of 11V/V.

Example 6.1: MOSFET Amplifier

▪ Consider the amplifier circuit shown in Figure 6.4(a). The transistor is specified to have V_t = 0.4V, k^’_n = 0.4mA/V², W/L = 10, and l = 0. Also, let V_DD = 1.8V, R_D = 17.5kOhms, and V_GS = 0.6V.

▪ Q(a): For v_gs = 0 (and hence v_ds = 0), find V_OV, I_D, V_DS, and A_v.

▪ Q(b): What is the maximum symmetrical signal swing allowed at the drain? Hence, find the maximum allowable amplitude of a sinusoidal v_gs.

Figure 6.4(a)

▪ step #1: Define and solve for V

.

▪ step #2:, assume saturation.

▪ as such, employ (6.17)

0.6

0.6 0.4 0.2

GS OV

V V

V

V

=

= − =

' 2

2

1 2

1 0.4 10 0.2 0.08 2

D n OV

i k W V

L

mA

 

=    

=    =

▪ step #3: Calculate V

from KVL.

▪ step #4: Test assumption that MOSFET operates in saturation

▪ YES!!!

▪ step #5: Calculate gain (A

).

1.8 17.5 0.08 0.4

>

0.4 10 0.2 1

If then satu

7.5 rati

1

o

n

4 /

DS DD D D

DS OV

v n D

V V

OV

V

V V

V V R I

V V

A k V R



= −

= −  =

= −

= −   

= −

▪ step #6: What is the constraint which defines saturation?

▪ step #7: Put this expression in terms of v_gs using

▪ v_OV = v_GS– V_t

▪ v_GS= V_GS – v_gs

( )

remem solve for

define ne

ber tha w constraint

replac replace

with

t

GS GS ds

O GS t

s V

DS DS ds OV

ds OV DS

ds GS

v

t DS

v V v

gs GS t

v v V

DS

v V v v

v v V

v v V V v V V V

−

= +

= + 

 −

 − = = + − −

action:

action:

action:

action: e

with

OV GS t

v v −V

▪ step #7: Put this expression in terms of v_gs using

▪ v_OV = v_GS– V_t

▪ v_GS = V_GS – v_gs

▪ step #8: Solve for v_gs.

( )

remember tha

replace replace

with with

t

OV GS t

O

GS GS s

V GS t

v

v v V

v

ds GS t DS gs

V v

v

GS t D

V

v v V V v V V V

=

− −

+

 − = = + − −

action:

action:

replace with

isolate

solve for

( 1)

0.6 0.4 0.4

1 14

13.

1 3

ds v gs

gs

gs

v gs gs GS t DS

v gs GS t DS

GS t D

v A v

v

v

S gs

v gs

A v v V V V

A v V V V

V V V

v A

mA v

 + − −

−  − −

− − − −

 =

− − −



action:

action:

action:

Figure 6.5 Signal waveforms at gate and drain for the amplifier in Example 6.1.

Note that to ensure operation in the saturation region at all times, v

≥ v

– V

.

Example 6.1: MOSFET Amplifier

6.1.6. Determining the VTC via Graphical Analysis

▪ Graphical method for determining VTC is shown in Figure 6.7

▪ Rarely used in practice, b/c difficult to draw vi-relationship.

▪ Based on observation that, for each value of v

, circuit will operate at intersection of i

and v

.

(eq6.24) _D ^{DD DS}

D D

v i V

R R

= −

Figure 6.7: Graphical construction to determine the voltage transfer characteristic of the amplifier in Fig. 6.4(a).

▪ point A – where v_GS = V_t

▪ point Q – where MOSFET may be biased for amplifier operation

▪ v_GS = V_GS, v_DS= V_DS

▪ point B – where MOSFET leaves saturation / enters triode

▪ point C – where MOSFET is deep in triode region and v_GS = V_DD

Points A (open) and C (closed) are suitable for switch applications

Point Q is suitable for amplifier applications

6.1.6. Determining the VTC via Graphical Analysis

Figure 6.8: Operation of the MOSFET in Figure .64(a) as a switch: (a) Open, corresponding to point A in Figure 6.7; (b) Closed, corresponding to point C in Figure 6.7. The closure resistance is approximately equal to r_DSbecause V_DSis usually very small.

6.1.6. Determining the VTC via Graphical Analysis

6.1.7. Deciding on a Locating for the Bias Point Q

▪ bias point (Q) – is determined by value of v

and load resistance R

.

▪ Two considerations in deciding Q:

▪ Required gain.

▪ Allowable signal swing at output.

▪ To define load resistance R_D, one should refer to the i_D - v_DS plane.

▪ Two examples of R_D are shown to right for illustration:

▪ Q2: too close to triode

▪ not enough legroom

▪ Q1: too close to V_DD

▪ not enough headroom

▪ Ideally, we want to be somewhere in the middle.

6.1.7. Deciding on a Locating for the Bias Point Q

Figure 6.9: Two load lines and corresponding bias points. Bias point Q₁does not leave sufficient room for positive signal swing at the drain (too close to V_DD). Bias point Q₂is too close to the boundary of the triode region and might not allow for sufficient negative signal swing.

The objective is to prevent v_DS from “clipping” or entering triode region

6.2. Small-Signal Operation and Models

▪ Previously it was stated that linear amplification may be obtained from MOSFET via…

▪ Operation in saturation region

▪ Utilization of small-input

▪ This section will explore small-signal operation in detail

▪ Note the conceptual amplifier circuit to right

Figure 6.10: Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.

dc bias voltage output voltage

input voltage to be amplified

6.2.1. The MOSFET Case The DC Bias Point

▪ Q: How is dc bias current I

defined?

( )

only applies in saturation where

2 2

(eq6.25) (eq6.26)

1 1

2 2

DS OV

D n GS t n OV

DS DD D

V

D

V

I k V V k V

V V R I



= − =

= −

Figure 6.10: Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.

6.2.1. The MOSFET Case

The Signal current in the Drain Terminal

▪ Q: What is effect of v

on i

?

▪ step #1: Define v

as in (6.27).

▪ step #2: Define i

, separate terms as

function of V

and v

( )

( )

( )

2

2

2 state (5.17)

1 2

1 2 (eq6.27)

(eq5

(e

.17)

q5.28

2 )

GS OV

GS gs t

GS GS gs

D n GS gs t

GS t

n

GS t gs gs

v v

V D

v V

v V v

i k V v V

V V

k

V V

i

v v

+ −

= +

 

 

=   + − 

− − − − − − − − − − − − − − − − −

  

 − + 

 

=  

− − −



− −

+ − +



−

action:

( )

( )

expand the sq

2

uared term via and

simplif

2 y

(eq6.

1 2 1 28

2 )

GS t gs

D n GS t

n GS t gs n s

v

g V V

i k V V

k V V v k v

−

= − +

+ − +

action:

action:

Note that this differs from previous analyses - because of attempt to isolate the effect of v_gs from V_GS.

Q: What is effect of v

on i

?

( )

( )

( )

current gain term

distortion term

2 2

(eq6.2 1 1

2 2

8)

D

D n GS t n GS t gs n gs

I

i = k V − V + k V − V v + k v

linear

nonlinear dc bias

▪ step #3: Classify terms.

▪ dc bias current (I

).

▪ linear gain – is desirable.

▪ nonlinear distortion – is undesirable, because rep. distortion.

Note that to minimize nonlinear distortion, v

should be kept small.

½ k

v

<< k

(V

-V

)v

v

<< 2(V

-V

) (6.29)

v

<< 2v

(6.30)

▪ step #4: Adapt (6.28) for small-signal condition.

▪ If v

<< 2v

, neglect distortion.

( )

( )

( )

( )

current gain term

distortio 2

m 2

n ter

1 1

(eq6.28)

(eq6.32)

2 2

D

D n GS t n GS t gs n gs

d

m n GS t

g I

s

i k V V k V V v k v

g i k V V

v

= − + − +

 = −

linear

nonlinear dc bias

MOSFET transconductance

Q: What is effect of v

on i

?

Figure 6.11: Small-signal operation of the MOSFET amplifier.

(eq6.34)

GS GS

D

m v V

GS

g i

v

 



6.2.1. The MOSFET Case The Voltage Gain

▪ Q: How is voltage gain (A

) defined?

▪ step #1: Define v

for circuit of Figure 6.10 using KVL.

( )

( )

dc comp

apply small-signal condition

regroup terms sim

on

plif

ent

y

ds DS

DS DD D D DD D D d

DD D D D d DS D

v V

DS d

v V R i V R I i

V R I R i V R

v i

= − = − +

= − − = −

action:

action: action:

Figure 6.10: Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.

Q: How is voltage gain (A _v ) defined?

▪ step #2: Isolate v

component of v

.

▪ step #3: Solve for gain (A

).

( )

isolate

insert (6.32)

solve (5

for gai 4 )

n . 7

(eq6.35) (eq6.35)

(eq6.36)

ds

ds D d

D m gs

ds

v m D

g d

v

s s

v R i

R g v

A v g R

v

v

− − − − − − − −

= −

= −

 = −

− − − − − − −

action:

action:

action:

Figure 6.10: Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.

6.2.1. The MOSFET Case The Voltage Gain

▪ Output signal is shifted from input by 180°.

▪ Input signal v

<< 2(V

– V

).

▪ Operation should remain in MOSFET saturation region

▪ v

> v

– V

(legroom)

▪ v

< V

(headroom)

Figure 6.12: Total instantaneous voltage v_GSand v_DSfor the circuit in Figure 6.10.

6.2.1. The MOSFET Case

Small-Signal Equivalent Models(a)

▪ From signal POV, FET behaves as VCCS.

▪ Accepts v

between gate and source

▪ Provides current (i

) at drain

▪ Input resistance is high

▪ b/c gate terminal draws i

= 0

▪ Output resistance is high

Figure 6.13: Small-signal models for the MOSFET: (a) neglecting the dependence of i_Don v_DSin saturation (the

channel-length modulation effect) and (b) including the effect of channel length modulation

Figure 6.13: Small-signal models for the MOSFET: (a) neglecting the dependence of i

on v

in saturation (the channel-length modulation effect) and (b) including the

effect of channel length modulation

Note that this resistor (r

) takes on value 10kOhm to

1MOhm and represents channel-length modulation.

6.2.1. The MOSFET Case

Small-Signal Equivalent Models(a)

▪ Model (b) is more accurate than model (a)

▪ r

= V

/ I

▪ Small signal parameters (g

, r

) both depend on dc bias point

▪ If channel-length modulation is

considered, (6.36) becomes (6.39). ( )

less accurate, b/c does not consider channel length modulation

more accurate, b/c does consider channel length modulation

(eq6.36)

(eq6.39)

ds

v m D

gs

ds

v m D o

gs

A v g R

v

A v g R r

v

 = −

= = −

6.2.1. The MOSFET Case

Small-Signal Equivalent Models(b)

6.2.1. The MOSFET Case The Transconductance g

▪ Observations from (6.40)

▪ g

is proportional to m

, C

, ratio W/L, dc component V

.

▪ MOSFET with short / wide channel provides maximum gain.

▪ Gain may be increased via V

, but not without reducing allowable swing of v

.

( )

( )

make some substitutions

simplify

(eq6.40)

(eq6.40)

(eq6 .41 )

n

m

d

m n GS t

gs

n GS t

m n OV

k

g i k V V

v

k W V V L

k W V L g

g

 = −

=  −

= 

action:

action:

▪ Observations from (6.40)

▪ g

is proportional to square root of dc bias current (I

)

▪ For given I

, g

is proportional to (W/L)

▪ This behavior is sharp contrast to the bipolar junction transistor (BJT).

▪ For which, g

is proportional to g

alone (not size or geometry).

solve (6.25) for

substitute for as defined above

(eq6.25)

(e

(eq6.25)

1 2

2 /

2 (eq6.40 /

q6.40)

(eq6

)

OV

OV

m

D n OV

D OV

n

m n OV

D V

V

n

n

I k W V L

V I

k W L

g k W V L

I k W

L k W L g

− − − − − − − − − − − − − −

= 

= 

= 



−

=

−



action:

action:

simplify

.41) g

= 2 k

 W L I /

action:

6.2.1. The MOSFET Case

The Transconductance g

6.2.1. The MOSFET Case The Transconductance g

▪ Figure 6.14 illustrates the relationship defined in (6.42).

( )

replace

s

2

implify

(eq6.41) (eq6.40)

(eq6.4

2

2 2

2)

n

m n OV

D

OV

GS t

D D

m

GS

k W

t OV

L

m

g k W V L

I V

V V

I I

g g

V V V



= 

 

 

=   −  

= =

−

action:

action:

Figure 6.14: The slope of the tangent at the bias point Q intersects the v_OV axis at 1/2V_OV. Thus g_m

= I_D/(1/2V_OV).

6.2.1. The MOSFET Case The Transconductance g

▪ In summary, there are three relationships for determining g

:

▪ (6.40), (6.41), and (6.42)

▪ These relationships are dependent on three design parameters:

▪ W/L, V

, I

(eq6.40)

(eq6.41)

(eq6.

2 /

) 2 42

m n OV

m n D

D m

OV

g k W V L

g k W L I

g I

V

= 

= 

=

Example 6.3: MOSFET Amplifier

Figure 6.15: Example 6.3 amplifier circuit.

note: capacitors block dc signals completely, but have no effect on small-signal

▪ Figure 6.15 shows a discrete common-source MOSFET amplifier utilizing a drain-to-gate resistance R

for biasing purposes. The input signal v

is coupled to the gate via a large

capacitor, and the output signal at the drain is couppled to the load resistance R

via another large capacitor. The transistor has V

= 1.5V, k

(W/L) = 0.25mA/V

, and V

= 50V. Assume the coupling capacitors to be sufficiently large so as to act as short circuits at the signal-

frequencies of interest.

▪ Analyze this amplifier circuit to determine its (a) small-signal voltage gain, its (b) input

resistance, and the largest allowable input signal.

Figure 6.15 Example 6.3: (a) amplifier circuit; (b) circuit for determining the dc operating point; (c) the amplifier small- signal equivalent circuit; (d) a simplified version of the circuit in (c).

-50- 1st : determine the dc operating point

eliminate the input signal v_i , and open circuit the two coupling capacitors (since they block dc currents).

since I_G=0, the dc voltage drop across R_G will be zero, and

With V_DS=V_GS, the NMOS transistor will be operating in saturation

V

= 1.5V, k

(W/L) = 0.25mA/V

, V

=15V, R

=10k Ω

 I

=1.06mA, V

=V

=4.4V, V

=4.4-1.5=2.9(V)

▪ step #1: Analyze dc operation of the circuit.

▪ Eliminate vgs.

▪ Represent all capacitors as open circuits (b/c dc).

▪ step #2: Note that I

= 0 b/c of capacitive gate.

Example 6.3: MOSFET Amplifier

▪ step #2: note that I

= 0 b/c of capacitive gate

▪ and drop across R

will be 0.

▪ step #3: define I

with assumption of saturation.

▪ step #4: define V

=V

via KVL.

( )

assume saturation

efine via KVL

(eq6.25)

(eq6.26)

1

D

2

DS DD D D

d

GS

I k V V

V V R I V

= −

= − =

action:

action:

Example 6.3: MOSFET Amplifier

-53- 2ndly, proceed with the small-signal analysis of the amplifier

Replacing the coupling capacitors with short circuits and the dc voltage supply being replaced with a short circuit to ground.

i o v

i i

in

v i , A v v

R = / = /



=

=

= R R r k

R

||

||

10 || 10 || 47 4 . 52

)

(

o

i g v R

v = −

G o gs

i

R

v i v −

=

G L

G m L

m v

R R

R R g

g

A

1 1 1

+

−

−

=



=

=

=

=



=

= I k r V

V k g

D A o

OV n m

06 47 . 1

50

mA/V 725

. 0 9 . 2 25 . 0

+

_

vgs

G D

S

gmvgs

ii

+

vi _

RG

RD RL +

_

vo

ro

Rin

+

_

v

=v

G D

S

g

v

i

+

v

R

R

_

v

i

-g

v

R

= v

i

R

=R

||R

||r

▪ step #4: Use (6.25) and (6.26) together, to

solve for V

▪ the expression is quadratic, and is solved accordingly

▪ step #5: Calculate I

.

▪ step #6: Calculate V

.

( )

( )

assume saturation

efine via 2

K

2

2 VL

(eq6.43)

(eq6.43) (eq6.43)

( 1

2

1 2

15 1 0.25 eq6.44

( 1.5) )

(eq6.4

2 )

1 3

0

D n GS t

DS DD D D GS

DD n GS t

d

D

DS DS

DS

I k V V

V V R I V

V k V R

V V

V V

v

= −

= − =

 

= −  − 

 

= −   − 

action:

action:

(eq6.43)

4.4 1.06

2.9

DS GS

DS

OV GS t

V mA

v v

V

v v V V

= =

=

= − =

Example 6.3: MOSFET Amplifier