Lecture5-Logic-CombinatinalLogic-abu-arqoub-2009.pdf

Chapter 4

Introduction

Combinational

.

N _{Combinational} 

.

Logic Circuit

.

.

Input 

Variables

.

.

Output 

Design Procedure

g

1. The problem is stated.

2 Th b f il bl i i bl & i d

2. The number of available input variables & required 

output variables are determined.

3 The input & output variables are assigned letter 3. The input & output variables are assigned letter 

symbols.

4. The truth table that defines the required relationships 

between the inputs & outputs is derived.

5. The simplified Boolean function for each output is 

obtained obtained.

Example

Example

•

Design

a

system

with

three

switches

and

two

lamps,

p

where

–

The

first

lamp

on

only

if

any

two

sequence

switches are on.

switches

are

on.

–

The

second

lamp

on

only

if

the

first

and

the

last

switches on

switches

on.

Example

Example

N b f i t Î 3

– Number of inputs Î 3

– Number of outputs Î 2

– Let the three inputs be a, b, & c.Let the three inputs be a, b, & c.

– Let the two outputs be L1, & L2. Truth Table:

Example

Example

–

Boolean

Function

for

the

outputs:

Adders

Add f t t

Adders are of two types:

• Half Adder (HF).

• Full Adder (FA)

• Full Adder (FA).

Half Adder: is the addition of two bits.

Design a combinational logic circuit to perform the addition 

Adders

Number of inputs Î 2 (2 bits to be added)

N b f Î 2 ( h & f bi )

Number of outputs Î 2 (the sum & carry of two bits)

• Let two input bits be X Y & the sum (S) & the carry (C)

• Let two input bits be X, Y & the sum (S) & the carry (C).

• Truth Table:

C S

Y X

0 0

0 0

0 1

1

0 1 1 0

0

0 1

0 1

1 0

Adders

Combinational

X

S

Combinational 

Logic Circuit For HA

Y

S

C

B l F ti f th t t

Boolean Function for the outputs:

S = X’Y + XY’ = X

⊕

S = X Y + XY  = X     Y

C = XY

1

⊕

C = XY

Adders

S = X     Y = (X    Y)’ 

(XY X’Y’)’

⊕

= (XY + X’Y’)’ 

Full Adder

It’s the arithmetic sum of three input bits (the sum of two 

significant bits & the carry from the previous lower significant bits & the carry from the previous lower 

significant position).

b l l f h

Design a combinational logic circuit to perform the 

addition of 3 bits (sum of 2 bits & the carry).

Number of Inputs Î 3 (2 bits & carry) Number of outputs Î 2 (sum & carry)

Let the inputs be X, Y, C_in Let the outputs be S C

X

Y +

C_in

Let the outputs be S, C_out

Full Adder

Truth Table:

C_out S C_in Y X 0 0 0 0

0 0 0 0 0

0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 1 1

1 1 1 1 1

Full Adder

Boolean functions for the outputs:

No Simplification

Full Adder

C YC XC XY

C_out = YC_in + XC_in + XY

S = XY’C ’ + X’YC ’ + XYC + X’Y’C S = XY C_in + X YC_in  + XYC_in + X Y C_in

= C_in’ (XY’ + X’Y) + C_in (XY + X’Y’) = C C_iin’ (X (X

⊕

⊕

= C_in’ Z + C_in Z’ = C_in         Z  = C_in         (X     Y)

⊕

⊕

Full Adder

C_out = XY’C_in + X’YC_in + XYC_in‘ + XYC_in C (XY’ X’Y) XY (C ‘ C ) = C_in (XY’ + X’Y) + XY (C_in‘+ C_in)

Subtractors

Problem: Using a combinational logic circuit, Design 

1 H lf S b (HS)

1. a Half Subtractor (HS) 2. a Full Subtractor (FS)

1. Half Subtractor:

b

Inputs Î X, Y

X

-Y Inputs Î X, Y

Outputs Î D, B(Borrow)

Subtractors

T h T bl

Truth Table:

D B Y X 0 0 0 0 1 1 1 0 1 0 0 1

B = X’Y

1 0 0 1 0 0 1 1

B   X Y

D = X’Y + XY’ = X      

⊕

Subtractors

2. Full Subtractor:

Inputs Î X, Y, Bp (Bp is the previous borrow)

Outputs Î Bn D (Bn is the next borrow)

Outputs Î Bn, D   (Bn is the next borrow)

Truth Table: X Y Bp Bn D

Truth Table: _{0 0 0 0 0}

1 1 1 0 0 1 1 0 1 0

Bn Bp

1 1 0 1 0 0 1 1 1 0 1 0 0 0 1

Subtractors

D = X’Y’Bp + X’YBp’ + XY’Bp’ + XYBp

Code Conversion

Ex: Design a combinational logic circuit to perform a 

conversion from the BCD to the Excess 3 code conversion from the BCD to the Excess‐3 code.

Inputs Î 4 (A, B, C, D)

Inputs Î 4 (A, B, C, D)

Code Conversion

Code Conversion

Truth Table:

Output Excess‐3 Inputp  BCD p

Z Y X W D C B A 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 . . . . . . . . . . . . . . . . 0 0 1 1 1 0 0

1 0 0 1 1 1 0 0

Code Conversion

W

W = m₅ + m₆ + m₇ + m₈ + m₉ X = m₁ + m₂ + m₃ + m₄ + m₉ Y m + m + m + m + m Y = m₀ + m₃ + m₄ + m₇ + m₈ Z = m₀ + m₂ + m₄ + m₆ + m₈

Code Conversion

Code Conversion

Code Conversion

Code Conversion

W = A + BC + BD = A + B (C + D)

X = B’C + B’D + BC’D’ = B’ (C + D) + BC’D’ B’ (C + D) + B ( C + D)’

= B  (C + D) + B ( C + D)

Y = CD + C’D’ = CD + (C + D)’ Y = CD + C D  = CD + (C + D)

Analysis Procedure

y

Th l i f bi i l i i i h

The analysis of a combinational circuit is the reverse 

process of the design of a combinational logic circuit.

It starts with a given logic diagram & ends with a set of 

Boolean functions, a truth table, or a verbal explanation 

Analysis Procedure

y

Analysis

Procedure

R1 XY R1=XY R2=XZ R3=YZ

F₁ (X, Y, Z) = R₁ + R₂ + R₃ = XY + XZ + YZ

F₂ (X, Y, Z) = F1(X,Y,Z)’= (XY + XZ + YZ)’ = (X’ + Y’) (X’ + Z’) (Y’ + Z’)

T th T bl Truth Table:

F₂ = (F₁)’ F₁ = R₁ + R₂ + R₃

R₃ = YZ R₂ = XZ

R₁ = XY Z Y X 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1

0 1 0 0 0 0 0 1

Analysis Procedure

y

Ex2: Given the following logic circuit, analyze it:

R₁ = (XY)’ R₂ = (R₁ Z)’

R₁  (XY)       R₂    (R₁ Z) F (X, Y, Z) = (R₂ X)’

Analysis Procedure

y

Truth Table:

F = X’ + Y’Z Y’Z X’ Z Y X 1 0 1 0 0 0 1 1 1 1 0 0

F = (R₂X)’ R₂ = (R₁Z)’

R₁ = (XY)’

Analysis Procedure

y

Ex3: Analyze the following logic circuit:

F = (R₂ + Y)’ , R₂  = (R₁ + Z)’ R₁ = (X + Y)’ Î R₂ = ((X + Y)’ + Z)’

Analysis Procedure

y

Truth Table:

F (X, Y, Z) Z Y X 1 0 0 0 1 1 0 0 0 0 1 0 0 1 1

0 1 1 0