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Billion-Gate Secure Computation with Malicious Adversaries

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Figure

Table 1: The size of the working set for various circuits(sizes include input gates)
Figure 1: Average fraction of circuits remaining after each optimization is applied in sequence
Table 3: Time required to compile and optimize RSA and edit distance circuits on a workstation with an Intel Xeon5506 CPU, 8GB of RAM and a 160GB SSD, using the textbook modular exponentiation algorithm
Figure 2: Both the generator and evaluator consist of aroot process (solid dot) and a number of slave processes(hollow dots)
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