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Jackpot Stealing Information From Large Caches via Huge Pages

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Figure

Fig. 1. Cache accesses when it is physically addressed.
Fig. 2. Regular Page (4 KB, top) and Huge Page (256 KB, bottom) virtual to physical address mapping for an Intelx86 processor
Fig. 3. Histograms of 10,000 access times in the probe stage when all the lines are in the L3 cache and when allexcept one are in the cache (and the other one in the memory).
Fig. 4. Prime and reprime stages to ensure we monitor the last level cache.
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