Performance analysis of error recovery schemes in high speed network - part I

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Performance Analysis

of

Error Recovery Schemes

in

High Speed Network - Part

I

Fu-Yung

Lai

Arne A. Nilsson

Center for Communications and Signal Processing

Electrical and Computer Engineering Department

North Carolina State University

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Contents

1 Introduction

2 Frame Switching and Frame Relay Error Recovery Schemes

3 Static Analysis

3.1 Frame Switching - Link-by-link Scheme . .

3.2 Frame Relay - End-to-end Scheme . . . .

4 Results from Static Analysis

5 Dynamic Analysis

5.1 Network Model . . . · · · . · · · 5.2 Frame Relay - End-to-end Scheme

5.3 Frame Switching-Link-by-link Scheme

6 Results from Dynamic Analysis

7 Conclusion

2

3

5

5

7

9

13

13

14

18

24

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1

Introduction

In recent years, the advances in fiber optics technology and the demand for the transmission

of packetized voice, video, and data have brought us into a high speed communication

environment. The usage of fiber optics as a communication media results in very low bit

error rate. Furthermore, the increase of the transmission speed makes the propagation

delay of the medium no longer negligible.

In this paper we have concentrated on the performance analysis of the error

recov-ery schemes which are usually performed in the high speed communication environment.

Basically, there are two error recovery schemes in the high speed network:

• Frame switching scheme - link-by-link error recovery approach.

Two adjacent nodes in a path locally detect and recover from packet error or loss .

• Frame relay scheme - end-to-end error recovery approach.

Error recovery is done solely between the source and the destination node.

We have performed a static and a dynamic analysis of the above error recovery schemes

and in this paper we provide conclusion about their performance under different conditions

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2

Frame

Switching

and

Frame

Relay Error Recovery Schemes

In a high speed computer communication network, there are two major error recovery schemes, the frame switching and the frame relay scheme. As shown in Fig(l), the frame switching is a link-by-link error recovery scheme, where the link layer of two adjacent nodes will perform error detection and error recovery functions. The time for each node to transmit a packet is the sum of the LLC layer processing time and the packet transmission time. If an error occurs, the packet will be retransmitted until it is correctly received by the next node. A node will keep a copy of the transmitted packet until an ACK message from the next node is received. If an ACK message of a transmitted packet is not received within a timeout period, the packet will be retransmitted. We assume that a timeout will happen if a packet is in error or lost.

.

~

LLC LLC LLC

I

I

I

L

I

LLC

All Higher layers LLC layer

MAC and Physical layers

Fig1 Network layer model -- Frame Switching

LLC

LLC

L ___

--J

I

I

I

I

Fig2 Network layer model -- Frame Relay

All Higher layers LLC layer

MAC and Physical layers

Frame relay scheme, shown in Fig(2), is an end-to-end error recovery scheme,

where any detected errors are corrected within peer communication between the source

and the destination node of the network. In this scheme, an intermediate node will not

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3

Static Analysis

In this secction we present results from a static analysis of the two schemes. In this analysis we assume that the behavior of the system is independent of traffic loading. This is clearly not realistic but the results from the analysis will provide us with a bound on the relative merits of the two schemes. In this analysis we only consider the effect of packets in error due to transmission errors. The impairments due to possible loss of a packet caused by insufficient buffer space are ignored. This is of course consistent with the assumption of traffic independent behavior.

3.1 Frame Switching - Link-by-link Scheme

In the frame switching scheme, error detection and error recovery are done in the link layer of each node in the network. If a packet can not be successfully received by a node, it is retransmitted from the preceding node.

source

Fig3 A single path

A simple path from the source to the destination node is shown in Fig(3). For simplicity, we have assumed that the geographical distance between each node is the same.

For the static analysis, we use the following definitions.

N _ the number of hops needed to transmit a packet from the source node to the

desti-nation node.

e -

the bit error rate of a link.

Pi - packet length

x

e , the probability that a packet will be in error when it passes

(7)

N; -

-l!.L

1-PIi .,the average number of retransmission needed to get a successful transmission

from node i-I to node i.

tprop - the propagation delay in each link.

tpacket - the average transmission time for a packet.

tNAK - the average transmission time for a NAK.

t

u.c -

the processing time at the LLC layer.

T8ucce88 - the average time spent in one transmission from node i-I to node i if the

trans-mission is successful.

Tf a i l - the average time spent in one transmission from node i-I to node i if the

trans-mission is not successful.

TJ6 - the average packet delay between the transmission of a packet from the source node and the correct reception of the packet at the destination node.

In the static analysis, we neglect the queueing time. Thus, we have

N

T f s

=

L

[Tsl£cceu

+

N;

X T f ail]

i=l

where

N [

Pi

]

E

T

Sl£cceu

+

1 _

Pi

X

T

f ai l

(1)

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3.2 Frame Relay - End-to-end Scheme

In frame relay scheme, the error recovery is done between the source and the destination

node. If a packet is received in error at an intermediate node, we assume that the

desti-nation node will detect the error situation and send a NAK through the network to the

source node. We also assume that the NAK message will not be in error in this analysis.

If a packet is received correctly at an intermediate node, the packet will be transmitted

immediately to the next node.

Let N be the number of hops in the path from the source node to the destination

node and let Pi be the probability that a packet transmitted by node i-I and received at

node i is in error. Then, the probability that a transmission of a packet from the source

node is received in error at node k is given by :

k-l

II

(1 -

Pi) x Pk·

i=l

If a packet is received in error at node k , the overhead will be Tk , where

(2)

If no errors occurred in the transmission, the time to transmit a packet from the

source node to the destination node is equal to

T

8 U CC •

T

8ucc == t

LLC

+

N x

(tpacket

+

tprop)

+

t

LLC ·

Let T

f r be the average packet delay between the transmission of a packet from the

source node and the correct reception of the packet at the destination node. We find that

(3)

(9)

Finally the average packet delay Tf r can be written as :

N N k-l

II

(1 -

Pi)

X

T

su cc

+

L

II

(1 -

Pi)

X

Pk

X

T

k

T

-

i==1 k==1 ;==1

fr - N k-l

1 -

L

II

(1 - Pj)

X

Pk

k==lj==l

(10)

4

Results from Static Analysis

In the comparison of the results from the static analysis, we normalize the average delay

based on the packet transmission time. In Fig( 4), we compare the ratio of the average

delay of the frame switching and the frame relay schemes, Tf,/Tf r , for different values

of the packet error probability. Fig(5) shows the average end-to-end packet delay for the

frame switching and frame relay schemes. The number of hops between the source and

destination node is 4 for this case. The average packet size is 10,000 bits. We assume that

each link has the same capacity 150 Mbps and the propagation delay for each link is 0.25

msec. The LLC processing time is set to 0.7 msec.

In Fig(6) and Fig(7), we display the case where the number of hops between the

source and the destination node is increased to 12. The results indicate that with small packet error probability, the frame relay scheme has shorter packet delay than the frame

switching scheme. As the error probability increases, the average packet delay of the frame

relay will increase faster than the frame switching scheme. In Fig(7), we find that when

the number of hops is 12, the error probability of the cross over of the two error recovery

schemes will drop to 0.07.

Fig(8) shows the effect of the number of hops on the average packet delay for the

two error recovery schemes. In Fig(9) , the bit error probability is selected to be 2

*

10-8

and we vary the packet length. The result indicates that when the packet length is greater

than 300 K bits, the two error recovery schemes have almost the same performance.

In the static analysis, the model has been simplified. We will consider more

complicated model in the dynamic analysis, but the results from the static analysis can

still give us a good insight in how the two error recovery schemes perform in the high speed

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TfslTfr

1.4 1.3 1.2 1.1 1.0 0.9

no. of hops

=

4

packet length

=

10,000 bits

line capacity

=

150 M bps

prop. delay

=

0.25 msec/link

LLC time

=

0.7 msec

0.8 -+-r--"I"'--...,-....--r--.--...,-...-.--.-...,.-.-....-~

0.10 0.12 0.14 0.16 0.18 0.20 0.22

Probe of error

Fig(4)

Ratio of the delay of the two schemes

frame switching frame relay I!I

no. of hops = 4

packet size=10,000 bits

line capacity

=

150 M bps

prop. delay

=

0.25 msec/link

LLC time

=

0.7 msec

90

70

80

60 4-..--..-.--...-...--..-...-...-....-.-...-...--...-...---.-..---. 0.10 0.12 0.14 0.16 0.18 0.20 0.22

Probe of error

100 110

Average delay

120

Fig (5)

Average end-to-end

delay

(12)

no. of hops

=

12

packet size

=

10,000 bits

line capacity

=

150 M bps

prop. delay

=

0.25 msec/link

LLC

time

=

0.7 msec

0.06 0.08 0.10 0.12

Prob. of error

TfslTfr

1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.02 0.04

Fig(6)

Ratio of the delay of the two schemes

Average delay

400

I!I frame switching • frame relay

300

200

no. of hops

=

12

packet size

=

10,000 bits

line capacity

=

150 M bps

prop. delay= 0.25 msec/llnk

LLC time

=

0.7 msec

0.10 0.12

Prob. of error

0.06 0.08 0.04

100 -J--....-...-....-..~~-,..~-r--r---r-..-or-.,.--~

0.02

Fig(7)

Average end-to-end delay

(13)

Average delay

1200

fro switching fr. relay I!I

line capacity

=

150 M bps

prop. delay

=

0.25 msec/link

packet length

=

10,000 bits

prob. of error

=

0.02

400

200 600

Q-..--.--....---....---....---....--....--....--~...,-.,.----,,...,,...--..----.

o

1 0 20 30 40 50 60 70

No. of hops

80 1000

Fig (8)

The effect of the number of hops

TfslTfr

2.5

2.0

1.5

1.0

no. of hops

=

7

line capacity

=

16 M bps

bit error rate

=

0.00000002

prop. delay

=

0.25 rnsec/llnk

LLC time

=

0.7 msec

o.

5-+-...~--.--....--.-...---.--~~-.--~---.---..-....--.

o

200 400 600 800 1 000 1200

K

bits

Packet length

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5

Dynamic Analysis

5.1

Network Model

The model for the dynamic analysis will be based on a virtual circuit channel in the

communication network. In this model, we will consider the effect of different factors such

as channel errors, finite buffer, propagation delay, timeout mechanism, and traffic load.

Aye

Aye

destination /-Lo

Fig 10 virtual circuit model (before capacity reduction)

(15)

Ave

stage 1 stage 2

;\v~ono-ono-source \ \

J.L - Al J.L - A2

stage M

-ono-

;\vc

\ destination

J.L - AM

Fig 11 virtual circuit model (after capacity reduction)

5.2 Frame Relay - End-to-end Scheme

In the frame relay error recovery scheme, the function of an intermediate node is very

simple. If an intermediate node receives a packet in error or the packet is received correctly

but the buffer size is full, it simply discards the packet. When the timeout period is expired,

the source node will retransmit the packet along the virtual circuit. If a packet is received

correctly and the buffer size of the receive node is not full , the packet will be allocated

a space for storage waiting for transmission. The source node of the virtual circuit will

buffer the transmitted packet until an ACK message from the destination node is received.

We assume that the source node has an infinite buffer size for the incoming traffic.

0-

o

(16)

~vc

o

ILp I

Q

I ~vc

6

Fig 13 Complete VC queueing model of frame relay scheme

A single link and a complete virtual circuit model of the end-to-end error control are shown in Fig(12) and Fig(13) . We assume that the traffic at each node is a Poisson process with rate

Ai.

So, a single outgoing link can be modeled as an M/M/l/K queueing system. K is the maximum number of packets that a node can hold for transmission. For simplicity, we assume that all the nodes along the virtual circuit have the same service rate, propagation delay and finite buffer size. We let /-Lt and

1/

/-Lp be the mean packet transmission rate of each link and the mean propagation delay time through each link respectively. With the probability P; , a packet may be in error when it passes through a link of the virtual circuit. The steady state blocking probability of a node i is denoted as

PBi.

To compute the packet delay, we have to find the blocking probability

PBi

and the traffic rate

Ai.

In steady state, the traffic rate at point

I

and the traffic rate at point

0,

see Fig(13), should be the same. We thus get

AM

(1 -

Ave

(5)

Pe

)2

X

(1 -

P

B M )

A-

Ai+l

,i

=

2,3,···,Af - 1.

(6)

t

(1 -

Pe)(l - PBi)

Al

A2

(7)

Let'5 define:

then,

(17)

, i == 2,3, · · · ,M. (8)

From the analysis of an

M/M/1/K

system, we get the blocking probability at node i to be equal to

P

B, ==

P

TO

b[

ni ==

K]

==

(1 -

Pi)pf.K+1 ,1,

== , , ... ,

2 3 M

·

1 - Pi

(9)

Using equations (

5),(

8),and (

9),

we can solve for AM and PB M • Once we get the

values of AM and

P

B M , we can solve for AM-l and

P

B M -1• With the same method, we can

also find

Ai

and

P

B i , i==

1,2,. · ·,M.

Let n, and

N

i be the number of packets in the node i

and the average number of packets in the node respectively. Thus, we have

or

PI

1 - PI

~

P b[ O J .

~.

(1 -

pdpt

L..J ro ri,

==

J

x

J == L..JJ X K+l

;=0 ;=0 1 - Pi

(10)

(11)

Pl (I-Pl)

J.L. -

(K

+

1)

I-Pi

,i

==

1

,i

==

2, 3, · · · , M.

From Little's law, we can find the system time of a packet at node i, denoted as

N

i

T

i

==

-Aef fective

i

==

1

(18)

For the rest of the analysis we need the following definitions:

Pi -

probability that a transmitted packet from node i may not be accepted by nodei-l-L

P

J - probability that a transmission of a packet from the source node may fail in the middle of the virtual circuit.

nr - number of retransmissions of a packet before it is received correctly by the destination

node.

N; -

average number of retransmissions of a packet before it is received correctly by the

destination node.

Timeout - end-to-end timeout interval of the virtual circuit.

t

u.c -

LLC processing time.

Tf r - average end-to-end delay of a packet in the frame relay error recovery scheme.

We find that

and

i

=

1,2,···,Af - 1,

(12)

(13)

M i-I

PJ =

E

II(1 -

Pj)Pi • i=1 ;=1

and the average number of retransmissions

00

s.

=

E

kProb[nr

==

k]

k=O

00

L

k(Pf

)k(l -

Pf )

k=O

17

(14)

(15)

(19)

Therefore, the average interval between a packet transmitted from the source node

and its successful reception at the destination node is

M

T

l r

==

N;

X

(tLLC

+

T

1

+

Timeout)

+

tLLC

+

LT

i

-i=l

5.3 Frame Switching-Link-by-link Scheme

(17)

In the frame switching scheme, the error recovery is done by two adjacent nodes along

the virtual circuit. Each node of the virtual circuit will buffer a packet which has been

transmitted until an ACK message for the packet is received from the next node. If an

ACK message of a transmitted packet is not received within a timeout period, the packet

will be retransmitted. We assume that a timeout occurs if the packet is lost or the packet

IS In error.

I

a

I I

J,Lw I JL1JJ I

;\vc

~

__ :M_lt

I

~ ~~c

r,

e,

P

e Pe

PB, PB M -1 P B M

(20)

,---,

I

pw

I

----r---ll~

o-?:

Pt

0

Pe

I

I

---~

maximum K customers

(a)

Ai(l -

Pe)

(b)

Fig 15 Single link queueing model in frame switching

A single link and complete virtual circuit queueing model of the frame switching

scheme are shown in Fig(15) and Fig(14). We assume that each node of the virtual circuit

has the same service rate and finite buffer size. Since the transmitted packets have to wait

for an ACK message, the customers in the infinite server queue represent the packets for

which a timeout period has been started. The time 1/ILw is equal to the timeout period, which is in turn assumed equal the sum of twice the propagation delay time

+

the LLC processing time

+

the NAK message transmission time. So, the actual total number of packets buffered at node i is equal to the sum of the number of packets in the transmission

queue and the infinite server queues. If the number of packets buffered at node i is equal to K, all the incoming traffic will be blocked. So, the queueing system in Fig (I5a) can be

modeled as a closed queueing network, shown in Fig (I5b).

In order to find the end-to-end packet delay, we have to find the system time at

(21)

·

In steady state, the incoming traffic rate at point I is equal to the outgoing traffic rate at

point O. So, we get

and

i.e.

Ave

(18)

, for

i

=

2, · · ·

,M -

1.

(19)

(20)

Let's denote the queue with service rate Ai(l-

Pe)

in Fig(15b) to be queue 3, and queue1and queue 2

to

be the transmission queue and the infinite server queue, respectively. We define nl,n2,and n3 to be the corresponding number of customers in queue 1, queue

2, and queue 3. We now get the product form solution from the closed queueing network shown in Fig(15b) as

(21)

(22)

and

This gives us

(22)

(23)

where G(K) is a normalization factor. Since,

1==

L

Prob(nl,n2,n3)

nl+n:z+n3=K

we get:

The blocking probability,

P

B i , that all buffers in node i are full, is given by :

K

L

Prob(nl'

K -

nl,

0)

nt=O

The average number of packets in the transmission queue is N(i) · Where,

(24)

(23)

From Little's law, the system time that a packet spent in the transmission queue

is given by

T1

(i):

Tt(i)

N(i)

~effeet

,i == 2,3,·

··,M.

(26)

N(i)

(27)

Since the first node has an infinite buffer, we can model it as an

M/M/l

queue.

So, the system time for the first node is given by :

(28)

We now need the following definitions:

Pi -

the probability that a packet transmitted from node i may not be accepted by node

i+l.

Timeout -

link timeout interval. The timeout interval is equal to 1//-Lw, and it begins

when a transmission of a packet is completed.

n~ - number of retransmissions needed of a packet from node before it IS correctly

received by node i-l-L

N; -

mean value of the n~.

T(i) -

average delay a packet experiences passing through link i.

i

u.c -

LLC processing time.

Tf~ - average end-to-end packet delay in the frame switching scheme.

So, we have

(29)

(24)

(31)

(32)

The average end-to-end packet delay for the frame switching scheme is given by:

M

Tis

==

L

T(i).

i=l

(25)

6

Results from

Dy

narnic Analysis

In the results of the dynamic analysis, the average packet length is set to 10,000 bits, the link capacity is 150 M bps, and the propagation delay is 0.25 msec /Iink.

In Fig(16) and Fig(17) , we compare the average packet delay along the virtual circuit for the frame switching and the frame relay scheme. The results indicate that under low error rate condition, the frame relay scheme has better performance( shorter delay). This is due to the processing overhead in the LLO layer of the frame switching scheme. The reason why, in Fig (16) , the frame switching scheme will saturate very quickly is due to the finite buffer size problem. In the frame switching scheme, a packet will be held in a node until an ACK message from the next node is received. Since the buffer size(K=10) is too small, the blocking probability will become a important factor to the packet delay. After we increase the error probability the delay curves of the frame switching and the frame relay scheme have a cross point when the throughput is about 0.76, see Fig(18). This indicates that under light traffic the frame relay scheme can have shorter delay in wider range of traffic than the frame switching scheme. However, if we let the error probability increase more, in Fig(19), we will find that the frame switching error recovery scheme will perform bet ter .

(26)

no. of hops = 10

probe in error

=

0.001

K=30 K=20

300

K= 10 e link-by-link buf= 10

0 link-by-link buf=20

200 !! link-by-link buf=30

K=10 K=20

end-to-end buf=10

100

....

6~

K=30 e end-to-end buf=20

8 bOOB

6 end-to-end buf=30

Average delay

400 0.8 1.0

Throughput

0.6 0.4 0.2

O-t-...,-~...,,--..,..-..,..-...-...-...--...--...--...-...-a---.

0.0

Fig (16) Average packet delay, with low error rate

Average delay

400 end-to-end link-by-link I!I

0.6 0.4 0.2

no.ofhops=10

buffer size

=

40

probe in error

=

0.01

0.8 1.0

Throughput

Fig (17) Average packet delay. with low error rate

300

200

100 +-~~";:-~;""--r--.,---r-""'-""-""-'-"'---r-"1

0.0

(27)

no. of hops

=

10

buffer size

=

40

probe in error

=

0.015

Average delay

220

200

180

160

140

I!I

end-Ie-endlink-by-link

0.6 0.8 1.0

Throughput

0.4

0.2

120 -+-...--...-...--..---r--..--...-..-....-...-..--..---....--. 0.0

Fig (18) Average packet delay, with high error rate

Average delay

190

II end-to-end • link-by-link

no. of hops =10

buffer size

=

30

probe in error

=

0.025

180

170

160 -+---..----.---.--..~..---...--.---..---...----.---..----.

0.1 0.2 0.3 0.4 0.5 0.6 0.7

Throughput

Fig (19) Average packet delay, with high error rate

(28)

Average delay

1500 1000 500 !I end-te-end • link-by-link

buffer size

=

20

prob. in error

=

0.005

throughput

=

0.5

o

20 40 60 80

No. of hops

Fig (20) Effect of the number of hops, with lower error rate

end-to-end link-by-link

I!I

buffer size

=

20

prob. in error

=

0.01

throughput

=

0.5

50 60

No. of

hops

40 30 20 1 0 o-l-=.--...----.-....--r---r---r-~-.,~,__-r-_,

o

800 600 200 400 1000

Average delay

1200

Fig (21) Effect of the number of hops, with higher error rate

(29)

Average delay

300

no. of hops

=

10.

max buffer size

=

20

throughput

=

0.1

200

100

I!J

end-to-end

link-by-link

O-P--.---...-...-..-....--.---...----...~....-....-...- ... 0.00 0.01 0.02 0.03 0.04 0.05 0.06

Prob. of error

Fig (22) Frame Switching

vs

Frame Relay

Average delay

300

no. of hops

=

10.

max buffer size

=

20

throughput

=

0.5

200

I!I

end-to-end

link-by-link

100

O-t--.----...-..-..--...-~-....-..-.--...--..--..

0.00 0.01 0.02 0.03 0.04 0.05 0.06

Prob. of error

Fig (23) Frame Switching

vs

Frame Relay

(30)

7

Conclusion

From the above discussion, we find that the average end-to-end packet delay of the frame

switching and the frame relay schemes is affected by the following parameters :

1. error rate of a packet on a link,

2. blocking probability (buffer size),

3. number of hops along the virtual circuit,

4. traffic along the virtual circuit,

5. processing overhead in LLC layer.

Processing overhead gives a fixed offset to the delay. The other factors will have a combined

effect to the end-to-end packet delay.

• When the packet error rate on a link is low, the frame relay error recovery scheme can

achieve shorter delay. Since the effect of the number of retransmissions in the frame

relay scheme is less than the effect of the processing overhead in frame switching

scheme, the frame relay scheme can perform better. Furthermore, under low error

rate condition, the buffer size is a dominant factor to the delay of the frame switching

scheme. If the buffer size is too small, the frame switching scheme will saturate very

fast as the network traffic increases. If the error rate is high, there is a cross point

of the delay between the frame switching and the frame relay scheme. This indicates

that in the light traffic situation, the frame relay scheme can have shorter delay, and

the frame switching scheme can perform better if the traffic load is high .

• When the traffic of the network is light, the error rate of a packet on a link is the

dominant factor to the packet delay. In the high speed optical fiber network( low

error rate), the frame relay error recovery scheme can achieve shorter delay.

• As the number of hops between the source and the destination node increases, the

delay of the frame relay scheme will increase due to the retransmissions. If the number

of hops is adequately large, the frame relay scheme will have shorter delay. However,

if the number of hops is very large, the frame switching error recovery scheme can

(31)

References

[1] Amit Bhargava, James F. Kurose, Don Towsley, Guy Van Leemput "Performance Com-parison of Error Control Schemes in High Speed Computer Communication Networks"

,1988 IEEE.

[2]

Tatsuya Suda, Naoya Watanabe "Evaluation of Error Recovery Schemes for a High-Speed Packet Switched Network: Link-by-Link Ver3u3 Edge-to-Edge Schemes"

,1988,IEEE.

[3] Marek I. Irland and Guy Pujolle "Compari30n of Two Packet-Retransmission Tech-niques" ,IEEE Transactions on Information Theory, Jan. 1980.

Figure

Fig(4)Ratio of the delay of the two schemes
Fig(4)Ratio of the delay of the two schemes p.11
Fig (5)Average end-to-end10

Fig (5)Average

end-to-end10 p.11
Fig (8)The effect of the number of hops

Fig (8)The

effect of the number of hops p.13
Fig (9) The effect of the packet length

Fig (9)

The effect of the packet length p.13
Fig (16) Average packet delay, with low error rate

Fig (16)

Average packet delay, with low error rate p.26
Fig (17) Average packet delay. with low error rate

Fig (17)

Average packet delay. with low error rate p.26
Fig (18) Average packet delay, with high error rate

Fig (18)

Average packet delay, with high error rate p.27
Fig (19) Average packet delay, with high error rate

Fig (19)

Average packet delay, with high error rate p.27
Fig (20) Effect of the number of hops, with lower error rate

Fig (20)

Effect of the number of hops, with lower error rate p.28
Fig (21) Effect of the number of hops, with higher error rate

Fig (21)

Effect of the number of hops, with higher error rate p.28
Fig (22) Frame Switching

Fig (22)

Frame Switching p.29
Fig (23) Frame Switching

Fig (23)

Frame Switching p.29

References