lab Manual soen 228

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SOEN 228/298 Lab Manual

Author: Author:

Rick

Rick Fenster Fenster

Last Revision: June 1, 2015 Last Revision: June 1, 2015

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2 2 Lab ExperLab Experimeiment 0: nt 0: InIntrodtroductuction to the Breadion to the Breadboarboard and d and EleElec- c-ttrroonniic c CCiirrccuuiitts s 1100 22.1 .1 IInnttrrododuuccttioion n tto o LLaab b EExxpeperrimimeennt t 0 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100

22..2 2 UUssiinng g tthhe e PPoowweer r SSuupppplly y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100

22..3 3 WWiirriinng g SSwwiittcchhees s ffoor r IInnppuutts s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100

2. 2.4 4 ThThe e 74740404, , 747408 08 anand d 747432 32 InIntetegrgratated ed CiCircrcuiuits ts . . . . . . . . . . . . . . . . . . . . . . 1010 22.5 .5 SStteep p 00: W: Wiirriinng g tthhe e BBrreeaaddboboaarrd d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111

2. 2.6 6 StSteep 1p 1: Co: Connttrorollllining g an an LELED D By By a Sa Swiwittcch . . h . . . . . . . . . . . . . . . . . . . . . . . . . . 1122

2. 2.7 7 StSteep 2p 2: T: Tesesttining tg the he 74740404, 7, 74408 08 anand d 747432 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122

3 3 LLaab b EExxppeerriimmeennt t 11: : TThhe e HHaallf f AAddddeer r 1133 33..1 1 IInnttrroodduuccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133

33..2 2 TThhe e HHaallf f AAddddeer . . . . . r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133

33.3 .3 SStteep p 00: Si: Simmppliliffy y tthhe e FFuunnccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133

33.4 .4 SStteep p 11: Im: Impplleemmeennt t tthhe e CCiirrccuuit it . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133

4 4 LLaab b EExxppeerriimmeennt t 22: : LLaattcchhees s aannd d FFlliipp--FFlloopps s 1144 44..1 1 IInnttrroodduuccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144

44..2 2 TThhe e SS--R R LLaattcch h . . . . . . . . . . . . . . . . . . . . . . . . . . 1144

44..3 3 TThhe e D D FFlliipp--FFlloop p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144

44.4 .4 SStteep p 00: As: Assseemmbblle e tthhe e SS--R R LLaattcch h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155

44.5 .5 SStteep p 11: As: Assseemmbblle e tthhe e D D FFlilipp--FFlolop p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166

4.6 4.6 *S*Stetep 2p 2: Buil: Build A d A PoPosisititiveve-E-Edgdge Te Tririggggerered ed D FD Fliplip-F-Flolop p . . . . . . . . . . . . 1616 5 5 PrProjojeect ct EExpxpereriimmenent t 00: : ThThe e TiTimiming ng SSigignanal l GGeneneeraratotor r 1177 55..1 1 IInnttrroodduuccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177

55..2 2 DDuutty y CCyycclle e aannd d FFrreeqquueennccy y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177

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55.4 .4 A A RReevvieiew w oon n OOrrddeerrs s oof f MMaaggnnitituudde e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177

55..5 5 TThhe e 55555 5 TTiimmeer r . . . . . . . . . . . . . . . . . . . . . . . . . . 1188

55.6 .6 TThhe e 7744LLSS11664 4 SSIIPPO O SShhifift t RReeggisistteer r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199

5. 5.7 7 FFeeeedbdbacack k FFor or ththe e TiTimiming ng SiSigngnal al GeGeneneraratotor r . . . . . . . . . . . . . . . . . . . . . . . . 2020 5. 5.8 8 AsAssesemmblblining g ththe e TiTimiming ng SiSigngnal al GeGeneneraratotor r . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2121 55..9 9 SSoomme e PPrro jo jeecct t TTiipps s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2211

6 6 Project ExProject Experimeperiment 1: nt 1: The BusThe Bus, Arith, Arithmetimetic Unit ac Unit and Prognd Programram C Coouunntteerr 2233 66..1 1 IInnttrroodduuccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2233

66..2 2 TThhe e DDaatta a BBuus s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2233

66..3 3 TThhe e PPrrooggrraam m CCoouunntteer r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2233

66..4 4 TThhe e AArriitthhmmeettiic c UUnniit t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2244

66..5 5 7744LLSS22883 3 44--BBiit t AAddddeer . . r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2244

66.6 .6 7744LLSS33995 5 44--BBit it SShhifift t RReeggisistteer r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2255

6.7 6.7 A Brief OA Brief Oververview on tview on the Proghe Program Coram Counteunter and Inr and Incremcremententer Syster System em 2626 66..8 8 AAsssseemmbblliinng g tthhe e CCiirrccuuiit t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2266

7 7 ProjeProject Experct Experimeiment 2: nt 2: DatData Regisa Registerters and the Memos and the Memory Ad-ry Ad-d drreesss s RReeggiisstteer r 3300 77..1 1 IInnttrroodduuccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3300

77..2 2 DDaatta a RReeggiisstteerrs s . . . . . . . . . . . . . . . . . . . . . . . . . . 3300

77..3 3 PPuuttttiinng g IIt t AAlll l TTooggeetthheer r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3300

8 8 PPrroojjeecct t EExxppeerriimmeennt t 33: : PPrrooggrraam m MMeemmoorry y 3322 88..1 1 IInnttrroodduuccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3322

88..2 2 A A BBrriieef f OOvveerrvviieew w oon n MMeemmoorry y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3322

88..3 3 DDeeccooddeerrs s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3322

88..4 4 SSCCMM2211CC1144EE--4 4 11K K x x 4 4 RRAAM M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3333

8. 8.5 5 747442 42 BiBinanary ry CoCodeded d DeDecicimamal l to to DeDecicimamal Dl Dececododer er . . . . . . . . . . . . . . . . . . 3434 88..6 6 7744LLSS11557 7 QQuuaad d MMuullttiipplleexxeer r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3344

8.7 8.7 74L74LS12S126 T6 Tri-ri-StaState Bte Buuﬀ ﬀ _eer_{r . . . .}_{. . . 3355}

88..8 8 TThhe e EExxppeerriimmeennt t . . . . . . . . . . . . . . . . . . . . . . . . 3355

88..88..1 1 BBuuiillddiinng g tthhe e CCiirrccuuiit t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3366

88..88..2 2 PPrrooggrraammmmiinng g tthhe e RRAAM M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3366

8. 8.8.8.3 3 DiDispsplalayyining tg the he CoConntetennts ts of of ththe Re RAM . . AM . . . . . . . . . . . . . . . . . . . . . . 3377

88..88..4 4 DDeemmoonnssttrraattiinng g YYoouur r WWoorrk k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3388

9 9 PPrrojojeecct t EExxpeperriimmeennt t 44: : TThhe e CCoonnttrrool l SSiiggnnaal l GGeenneerraal l 4400 99..1 1 TThhe e IInnccB B IInnssttrruuccttiioon . . . . n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4400

99..2 2 TThhe e MMoovvAAB B IInnssttrruuccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4400

99..3 3 TThhe e MMoovvBBA A IInnssttrruuccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4411

99..4 4 TThhe e IInnccA A IInnssttrruuccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4411

9. 9.5 5 ImImplplememenentiting ng ththe e SSigignnal al GeGenenerratatoor . r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4411

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10 0 A A NNootte e oon n CCiirrccuuiit t SScchheemmaattiiccs s 4433

1100..1 B l1 B loocck k DDiiaaggrraamms . . . s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4433

1100..2 El2 Eleeccttrricicaal l SScchheemmaattiiccs . . . s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4433

10.2.1 10.2.1 Using tUsing the Righe Right Sht Symboymbol and Sl and Showhowing Suing Supply Cpply Conneconnections tions 4343 10. 10.2.2 2.2 PaPart rt NamNames es and and RefRefereerencences: Why s: Why Do Do TheThey My Mattatter? er? . . . . . . 4444 11 11 UsUsining g ththe e 7474LSLS17173 3 As As a a ReReplplacacememenent t fofor r ththe e 7474LSLS39395 5 4646

List of Figures

1 1 BBrreeaaddbbooaarrd d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 2 SSwwiittcch h SScchheemmaattiic c SSyymmbbool l . . . . . . . 22

3 3 DDIIP P SSwwiittcch h PPaacck k . . . . . . . . . . . . . . . . . . . 22

4 4 RReessiissttoor r SScchheemmaattiic c SSyymmbboolls . . . s . . . . . . . . . . . . . . . . . . 33

5 5 RReessiissttoor r PPaacck k EEqquuiivvaalleennt t CCiirrccuuiit t . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6 6 BuBussssed ed ReResisiststor or PPacack k anand d IIndndivivididuaual l ReResisiststor or . . . . . . . . . . . . . . . . . . . . . . 33

7 7 CCaappaacciittoor r SScchheemmaattiic c SSyymmbobolls . s . . . . . . . . . . . . . . . . . . 44

8 8 CCeerraammiic c aannd d EElleeccttrroolylyttic ic CCaappaaccititoorrs s . . . . . . . . . . . . . . . . 44

9 9 LLEED D SScchheemmaattiic c SSyymmbbool l . . . . . . . . . . . . . . . . . . . . 44

110 0 LLEED D PPaacck k aannd d SSiinngglle e LLEED D . . . . . . . . . . . . . . . . . . . . 55

111 1 AAnnoodde e ssiidde e oof f LLEED D PPaacck . . . . . k . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

112 2 TTyyppiiccaal l IInntteeggrraatteed d CCiirrccuuiit . . t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

113 3 PPoowweer r SSuupppplly y SScchheemmaattiic c SSyymmbobols ls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

114 4 PPoowweer r SSuupppplly . . . . y . . . . . . . 66

115 5 LLaab b TToooolls s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

116 6 NNOOT T GGaatte e SSyymmbbool l . . . . . . . 77

117 7 OOR R GGaatte e SSyymmbbool . . . . l . . . . . . . 88

118 8 AANND D GGaatte e SSyymmbbool l . . . . . . . 99

119 9 SSwwiittcch h wwiitth h a a PPuulll l DDoowwn n RReessiissttoor r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100

220 0 7744004 4 PPiinn--OOuut t DDiiaaggrraam . . . m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111

23 23 ScSchhemematatic ic ffor or a a SSwiwittcch h CoConnttrorolllled ed LELED D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122

224 4 NNAANND D SS--R R LLaattcch h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144

225 5 D D FFlliipp--FFlloop p BBlloocck k DDiiaaggrraamms s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155

26 26 LeLevvelel-T-Tririggggerered ed D D FlFlipip-F-Flolop Ip Impmplelememenntatatition on . . . . . . . . . . . . . . . . . . . . . . . . 1515 227 7 IImmpplleemmeennttaattioion n oof f a a NNAANND D GGaatte . . e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166

28 28 ImpImplemlemenentattation ion of of a a PoPositsitivive-Ee-Edge dge TTrigriggergered ed D D FlipFlip-Fl-Flop op . . . . . . . . 1616 229 9 SSaammpplle e TTiimmiinng g DDiiaaggrraam . . . m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177

330 0 55555 5 TTiimmeer r PPiinn--OOuut t DDiiaaggrraam m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188

331 1 55555 5 TTiimmeer r AAssttaabblle e CCiirrccuuiit . . t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199

332 2 SShhiifft t RReeggiisstteer r BBeehhaavviioor r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199

333 3 7744LLSS11664 4 PPiinn--OOuut t DDiiaaggrraam m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2200

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38 38 PrProgograram m CoCoununtter er ReRegigistster er ScSchhemematatic ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2727 339 9 44--BBiit t AAddddeer r SScchheemmaattiic . . c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288

440 0 SSuum m RReeggiisstteer r SScchheemmaattiic c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288

441 1 MMiirrrroor r RReeggiisstteer r SScchheemmaattiic . c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299

442 2 DDaatta a RReeggiisstteer r SScchheemmaattiic . . . . c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3311

43 43 MeMemmorory y AdAddrdresess s ReRegigiststeer r SScchehemamatitic c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3311

444 4 SSCCMM2211CC1144EE--4 4 PPiinn--OuOut t DDiaiaggrraam m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3333

448 8 RRAAM M CCiirrccuuiit t DDiiaaggrraam . m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3399

449 9 CCoonnttrrool l SSigignnaal l GGeenneerraattoor r LLooggiic c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4422

550 0 TTyyppiiccaal l BBllocock k DDiiaaggrraam m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4433

551 1 TTyyppiiccaal l EEleleccttrricicaal l SScchheemmaattic ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4444

52 52 ScSchhemematatic ic WWitith h MMulultitiplple e ReRefferereencnces es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4455

53 53 7474LSLS17173 3 CiCircrcuiuit t fofor r ReReplplacacining g ThThe e 7474LSLS39395 . 5 . . . . . . . . . . . . . . . . . . . . . . . 4646

List of Tables

1 1 TTrruutth h TTaabblle e ffoor r tthhe e NNOOT T FFuunnccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

2 2 TTrruutth h TTaabblle e ffoor r tthhe e OOR R FFuunnccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3 3 TTrruutth h TTaabblle e ffoor r tthhe e AANND D FFuunnccttiioon n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4 4 TTrruutth h TTaabblle e ffoor r tthhe e HHaallf f AAddddeer r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133

5 5 TTrruutth h TTaabblle e ffoor r tthhe e SS--R R LLaattcch h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144

6 6 TTrruutth h TTaabblle e ffoor r tthhe e D D FFlliipp--FFlloop p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155

7 7 OOrrddeerrs s oof f MMaaggnniittuudde . . e . . . . . . . . . . . . . . . . . . . . . 1188

8 8 SSaammpplle e LLaayyoouut t oof f a a 332 2 X X 11B B MMeemmoorry y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3322

9 9 TTruruth th TTabable le fofor 2 r 2 bibit At Actctivive He Higigh ah and nd AcActitive ve LoLow Dw Dececodeoders . rs . . . . . 3333 110 0 BBeehhaavviioor r oof f SSCCMM2211CC1144EE--4 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3344

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1 1 In

Intr

trod

oduc

ucti

tion

on

The purpose of this laboratory is to introduce students to digital logic and The purpose of this laboratory is to introduce students to digital logic and com

computputer er arcarchithitectecture ure at at a a phphysiysical cal levlevel. el. StuStudendents ts will protowill prototytype pe and and testestt circuits that will form a basic, toy computer capable of executing a few selected circuits that will form a basic, toy computer capable of executing a few selected instru

instructionctions s by using TTL by using TTL inteintegratgrated circuits. ed circuits. In particulaIn particular, r, this lab this lab makmakes usees use of the 7400 logic family.

of the 7400 logic family.

The ﬁrst set of lab experiments serve to provide some familiarization and The ﬁrst set of lab experiments serve to provide some familiarization and exploration with digital logic. Once a comfortable working knowledge of digital exploration with digital logic. Once a comfortable working knowledge of digital logic has been established, a simple computer is built through 5 experiments. logic has been established, a simple computer is built through 5 experiments. Thi

This s comcomputputer conter containains s the majorithe majority of ty of the basicthe basics s neeneeded for ded for a a comcomputputer: er: aa program counter, memory, registers, a data bus and a control signal generator. program counter, memory, registers, a data bus and a control signal generator.

This lab

This lab experimexperiment compuent computer has the ter has the follofollowing speciﬁcawing speciﬁcations: tions: a clock of a clock of approximately 3.25 Hz, two 4-bit general purpose data registers, an incrementer, approximately 3.25 Hz, two 4-bit general purpose data registers, an incrementer, 16 X 4 bit instruction memory and three instructions.

16 X 4 bit instruction memory and three instructions.

1.1 1.1 Re

Repre

presen

sentin

ting

g Bin

Binary

ary

Bin

Binary systary systems havems have e twtwo o vvalualues of es of conconcercern: n: LogLogic 0 ic 0 and Logiand Logic c 1. 1. SinSince thisce this laboratory uses TTL technologies, a Logic 0 is considered to be

laboratory uses TTL technologies, a Logic 0 is considered to be 0 Volts (Ground 0 Volts (Ground or GND)

or GND) and a Logic 1 is considered to be and a Logic 1 is considered to be 5 Volts 5 Volts ..

1.2 1.2 Com

Common

monly U

ly Used

sed Pa

Parts

rts in t

in the L

he Lab

ab

1.2

1.2.1 .1 BreBreadboadboardard

The breadboa

The breadboard is rd is a tool a tool used to prototused to prototype and assemblype and assemble digital circuite digital circuits. s. It isIt is designed to intentionally slot integrated circuits with ease. Please see Figure 1 designed to intentionally slot integrated circuits with ease. Please see Figure 1 below. In the center, the gap is used to isolate the columns. For every column, below. In the center, the gap is used to isolate the columns. For every column, the

there is re is a a metmetal plate runnal plate running dowing down. n. TheThese metase metal l plaplates stotes stop p at the gap at the gap inin the breadboar

the breadboard. d. BecauBecause of se of this, each connecthis, each connector in tor in a particular columa particular column forms an forms a parallel connection. The only exceptions to this are the two sets of rows on the parallel connection. The only exceptions to this are the two sets of rows on the top and bottom of a breadboard

top and bottom of a breadboard. . EacEach one of h one of these rothese rows has all ws has all of its socketof its socketss connected together and called

connected together and called rails rails . . This charaThis charactericteristic makestic makes s these twthese two rowso rows ideal for +5 Volts and Ground.

ideal for +5 Volts and Ground.

Figure 1: Breadboard Figure 1: Breadboard

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1.2

1.2.2 .2 SwiSwitctcheshes

The switches used in these labs are single-pole, single throw switches (SPST). The switches used in these labs are single-pole, single throw switches (SPST). When the switch is

When the switch is closed closed , it forms a connection and when, it forms a connection and when open open , the connection, the connection is brok

is broken. en. In the lab, switcIn the lab, switches comhes come in e in pacpacks of ks of 8, 10 8, 10 or 12 or 12 and are placand are placed ined in the gaps of the breadboar

the gaps of the breadboards. ds. A 12 A 12 pacpack switch is shown in Figure 3. k switch is shown in Figure 3. The circuitThe circuit symbol for a SPST is shown in Figure 2.

symbol for a SPST is shown in Figure 2.

Figure 2: Switch Schematic Symbol Figure 2: Switch Schematic Symbol

Figure 3: DIP Switch Pack Figure 3: DIP Switch Pack

1.2

1.2.3 .3 ResResisistortorss

A

A resresististor is or is a a basbasic ic comcomponeponent for nt for anany y eleelectrctricaical l circircuicuit. t. It simply resiIt simply resistssts ele

electrctricaical l curcurrenrent. t. The resiThe resistastance of nce of a a resresististor is or is memeasuasured in red in OhmOhms s (( ΩΩ _)._).

In these expe

In these experimrimenents, a ts, a resresististor is or is useused d for twfor two o purpurposeposes. s. The ﬁrst is The ﬁrst is to actto act as a pull-down resistor for inputs and data lines, meaning that the resistor is as a pull-down resistor for inputs and data lines, meaning that the resistor is conne

connected to Ground. cted to Ground. The other reason is to The other reason is to limit the ﬂow of limit the ﬂow of currecurrent for LEDsnt for LEDs so that the LEDs do not burn out. Two common resistor symbols are shown in so that the LEDs do not burn out. Two common resistor symbols are shown in Figure 4.

Figure 4.

There are two packages available for use in the SOEN 228/289 labs. The ﬁrst There are two packages available for use in the SOEN 228/289 labs. The ﬁrst type is an individual resistor, used primarily in the Timing Signal Generator. type is an individual resistor, used primarily in the Timing Signal Generator. The other type is a resistor pack, which contains multiple resistors in one unit. The other type is a resistor pack, which contains multiple resistors in one unit. The resistor packs used in the lab are all tied to a common pin which makes these The resistor packs used in the lab are all tied to a common pin which makes these

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Figure 4: Resistor Schematic Symbols Figure 4: Resistor Schematic Symbols

resistors ideal for use with switch or LED packs since only one wire is necessary resistors ideal for use with switch or LED packs since only one wire is necessary to tie them to V

to tie them to VCCCC or or GroGroundund. . ComCommon pins are usualmon pins are usually an ly an outoutermermost pinost pin

denoted by a strip or a dot on one end of the resistor pack to show which side denoted by a strip or a dot on one end of the resistor pack to show which side the pin is

the pin is on. on. A typical resisA typical resistor pack of 4 tor pack of 4 resistresistors is ors is equivequivalenalent to t to the circuitthe circuit sho

shown in Figurwn in Figure 5. e 5. ActActual resual resististors are shoors are shown in Figurwn in Figure e 6. 6. A busseA bussed resisd resistortor pack is shown on the left with its common pin emphasized and a single resistor pack is shown on the left with its common pin emphasized and a single resistor is shown on the right.

is shown on the right.

Figure 5: Resistor Pack Equivalent Circuit Figure 5: Resistor Pack Equivalent Circuit

Figur

Figure e 6: 6: BusseBussed d ResistResistor Pack and or Pack and IndivIndividual Resistoridual Resistor

1.2

1.2.4 .4 CapCapaciacitortorss

A

A capacapacitor is a citor is a device that storedevice that stores electrical chas electrical charges then discharges then discharges them. rges them. InIn this lab, capacitors are only used during the Timing Signal Generator this lab, capacitors are only used during the Timing Signal Generator experi-men

ment. t. There are two types of capacitThere are two types of capacitors presenors presented to studentted to students. s. The ﬁrst typeThe ﬁrst type is a ceramic capacitor which is a capacitor that can be placed in any direction. is a ceramic capacitor which is a capacitor that can be placed in any direction. On the other hand, electrolytic capacitors are polarized and must be plugged On the other hand, electrolytic capacitors are polarized and must be plugged in with the longer leg being a

in with the longer leg being a positivpositive side. e side. Its unit is the FarIts unit is the Farad (F). Figure 7ad (F). Figure 7 shows the circuit schematic symbol for the capacitor.

shows the circuit schematic symbol for the capacitor.

In Figure 8, a ceramic capacitor is shown on the left and an electrolytic In Figure 8, a ceramic capacitor is shown on the left and an electrolytic capacitor on the right.

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This is due to the fact that it is polarized and must be connected to the positive This is due to the fact that it is polarized and must be connected to the positive side.

side.

Figure 7: Capacitor Schematic Symbols Figure 7: Capacitor Schematic Symbols

Figur

Figure e 8: 8: CeramCeramic ic and Electrolyand Electrolytic Capacitortic Capacitorss

1.

1.2.2.5 5 LELEDsDs

A light emitting diode is a a device that emits light when a current is passed A light emitting diode is a a device that emits light when a current is passed through. The brightness of the device is proportional to the amount of current. through. The brightness of the device is proportional to the amount of current. Because of this, an LED must be wired in series with a resistor to ensure that Because of this, an LED must be wired in series with a resistor to ensure that the LED will not burn out. The position in which the LED is plugged in does the LED will not burn out. The position in which the LED is plugged in does mat

matterter. . The positThe positivive end, e end, alsalso knowo known as n as thethe anode anode must be connected to a must be connected to a greater voltage than the negative part called a

greater voltage than the negative part called a cathode cathode . In Figure 9, the circuit. In Figure 9, the circuit sche

schematic symmatic symbol for an bol for an LED is shown. LED is shown. Pin 1 Pin 1 desigdesignates the anode, while pinnates the anode, while pin 2

2 designdesignates the ates the cathodecathode..

Figure 9: LED Schematic Symbol Figure 9: LED Schematic Symbol

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In this lab, two types of LEDs are

In this lab, two types of LEDs are avavailablailable. e. The first type is a The first type is a LED packLED pack which has multiple LEDs in one package that is designed to conveniently fit which has multiple LEDs in one package that is designed to conveniently fit the brea

the breadboadboard. rd. The otheThe other r is a is a stastandandard hole-rd hole-thrthrougough h pacpackkageage. . The anodeThe anode is mark

is marked on ed on the LED pacthe LED pack by k by hahavinving text (see Figug text (see Figure re 11, while the hole11, while the hole--through LED has its anode designated by the longer leg. Typically, the package through LED has its anode designated by the longer leg. Typically, the package type is used in the lab experiments due to convenience. The cathode is usually type is used in the lab experiments due to convenience. The cathode is usually conne

connected to a cted to a resistresistor and or and then to ground. then to ground. FigurFigure 10 e 10 presepresents the two types of nts the two types of LEDs available. An LED pack is on the left side and individual LED is on the LEDs available. An LED pack is on the left side and individual LED is on the right.

right.

Figure 10: LED Pack and Single LED Figure 10: LED Pack and Single LED

Figure 11: Anode side of LED Pack Figure 11: Anode side of LED Pack

1.2

1.2.6 .6 InIntegtegratrated Ced Circircuituitss

An integrated circuit (IC or informally, chip) is a device that provides some An integrated circuit (IC or informally, chip) is a device that provides some fun

functictionaonalitlityy. . TheThese devicse devices come in es come in manmany shapes and formy shapes and forms. s. In thesIn these labe lab experiments, the dual inline package (DIP) format is used since these devices experiments, the dual inline package (DIP) format is used since these devices con

convenvenientiently ﬁt ly ﬁt ontonto o the breadboarthe breadboard. d. EveEvery IC ry IC musmust t havhave e its supply pins its supply pins con- con-necte

nected to d to powepower the device. r the device. In these labs, VIn these labs, VCCCC (5 Volts) and Ground must be (5 Volts) and Ground must be

conne

connected to the device at cted to the device at the designthe designated pins. ated pins. A typical 14 pin A typical 14 pin IC is IC is presepresententedd in Figure 12. There is usually a plastic indent to visualize the alignment of the in Figure 12. There is usually a plastic indent to visualize the alignment of the inte

integratgrated ed circucircuit it and and shoulshould d be be refereferencerenced d when placing when placing the integratthe integrated ed circucircuitit onto the breadboard.

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Figure 12: Typical Integrated Circuit Figure 12: Typical Integrated Circuit

1.2

1.2.7 .7 PoPowewer r SupSupplyply

A p

A powower supply provider supply provides the pes the powower needed for the circuit. er needed for the circuit. The red connectoThe red connectorr denotes V

denotes VCCCC (5 Volts) and Ground (0 Volts) is denoted by the black connector. (5 Volts) and Ground (0 Volts) is denoted by the black connector.

This colour scheme is a typical method of colour-coding wires and is suggested This colour scheme is a typical method of colour-coding wires and is suggested for use during the labs.

for use during the labs. The power suppThe power supplies avlies availablailable in e in the lab are shown inthe lab are shown in Fig

Figure 14. ure 14. In this case, the In this case, the deddedicaicated 5 ted 5 VVolt and Grounolt and Ground d chchannannel on el on the farthe far righ

right is used. t is used. The symThe symbols for Vbols for VCCCC and Ground are shown in Figure 13. and Ground are shown in Figure 13. Note Note

that there are di

that there are di ﬀ ﬀ erent symbols for showing V erent symbols for showing V CC CC ..

Figure 13: Power Supply Schematic Symbols Figure 13: Power Supply Schematic Symbols

Figure 14: Power Supply Figure 14: Power Supply

1.

1.2.2.8 8 TTooloolss

In the lab, there are two tools that will be used. The ﬁrst is a wire cutter and In the lab, there are two tools that will be used. The ﬁrst is a wire cutter and stripper. It is used to cut wire and strip the plastic insulation around the wire stripper. It is used to cut wire and strip the plastic insulation around the wire to expose the metal for insert

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Puller, which is used for the extraction and removal of integrated circuits when Puller, which is used for the extraction and removal of integrated circuits when placed on the breadboard. These tools are shown in Figure 15.

placed on the breadboard. These tools are shown in Figure 15.

Figure 15: Lab Tools Figure 15: Lab Tools

1.3 1.3 Bas

Basic

ic Log

Logic

ic F

Fun

unct

ction

ionss

In a digital system, any digital logic function can be expressed by using three In a digital system, any digital logic function can be expressed by using three fun

fundamdamenental functtal functionions. s. TheThese se funfunctictions are ons are ANDAND, , NOT and NOT and OR OR and corrand corre- e-spond with

spond with their equivtheir equivalenalent t funcfunctions in tions in a a discrdiscrete mathemete mathematics course. atics course. EacEachh of these functions hav

of these functions have multiple inputs but only e multiple inputs but only one output. one output. Their behavioTheir behavioursurs are described in

are described in truth tables truth tables which contain every possible combination of inputs which contain every possible combination of inputs and thei

and their r resrespectpectivive e outoutputputs. s. If a If a loglogic functic function has n ion has n inpinputsuts, , it will it will hahave 2ve 2nn possible combinations.

possible combinations.

1.3

1.3.1 .1 NOT NOT FFuncunctiotionn

The NOT function is the simplest basic logic funct

The NOT function is the simplest basic logic function. ion. It has a It has a single input andsingle input and simply inverts it. This function can be described by the following equation: simply inverts it. This function can be described by the following equation:

F F == X X

The behaviour of the function is shown in Table 1. In the SOEN 228/298 labs, The behaviour of the function is shown in Table 1. In the SOEN 228/298 labs, the

the 7404 7404 IC is used to provide inverters that perform this function. The symbol IC is used to provide inverters that perform this function. The symbol for the NOT Gate is

for the NOT Gate is shoshown in wn in FigFigure 16. ure 16. The wire cutThe wire cutterter/st/stripripper is per is on theon the right and the IC puller is on the left.

right and the IC puller is on the left.

Figure 16: NOT Gate Symbol Figure 16: NOT Gate Symbol

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X X FF 0 0 11 1 1 00

Table 1: Truth Table for the NOT Function Table 1: Truth Table for the NOT Function

1.3

1.3.2 .2 OR OR FFuncunctiotionn

The OR function can be described as if any of the inputs are equal to a Logic The OR function can be described as if any of the inputs are equal to a Logic 1, the output will also be a Logic 1. It can be written as the equation

1, the output will also be a Logic 1. It can be written as the equation

F

F == A A++BB

The OR function is provided by the

The OR function is provided by the 7432 7432 IC. The truth table for the OR function IC. The truth table for the OR function is shown in Table 2. The symbol for the OR gate is shown in Figure 17.

is shown in Table 2. The symbol for the OR gate is shown in Figure 17. A A B B FF 0 0 0 0 00 0 0 1 1 11 1 1 0 0 11 1 1 1 1 11

Table 2: Truth Table for the OR Function Table 2: Truth Table for the OR Function

Figure 17: OR Gate Symbol Figure 17: OR Gate Symbol

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1.3

1.3.3 .3 AND AND FFuncunctiotionn

The AND function behaves in such a way that the output is equal to a Logic The AND function behaves in such a way that the output is equal to a Logic 1 if and only if, all the inputs are equal to a Logic 1. The OR function can be 1 if and only if, all the inputs are equal to a Logic 1. The OR function can be described as if any of the inputs are equal to a Logic 1, the output will also be described as if any of the inputs are equal to a Logic 1, the output will also be a Logic 1. It can be written as the equations

a Logic 1. It can be written as the equations F F == A A••BB oror F F == AB AB

The AND gate symbol is shown in Figure 18 and the truth table for the The AND gate symbol is shown in Figure 18 and the truth table for the AND function is shown in Table 3. In the SOEN 228/298 lab experiments, the AND function is shown in Table 3. In the SOEN 228/298 lab experiments, the AND function is provided by the

AND function is provided by the 7408 7408 integrated circuit. integrated circuit. A A B B FF 0 0 0 0 00 0 0 1 1 00 1 1 0 0 00 1 1 1 1 11

Table 3: Truth Table for the AND Function Table 3: Truth Table for the AND Function

Figure 18: AND Gate Symbol Figure 18: AND Gate Symbol

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2 2 Lab

Lab Exper

Experime

iment

nt 0:

0: In

Introdu

troducti

ction

on to

to the

the Bre

Bread-

ad-board and Electronic Circuits

board and Electronic Circuits

2.1 2.1 In

Introd

troduc

uctio

tion to La

n to Lab Expe

b Experim

rimen

ent 0

t 0

The goal of this lab experiment is to become familiar with using the breadboard, The goal of this lab experiment is to become familiar with using the breadboard, integrated circuits, LEDs, power supplies, resistors and switches.

integrated circuits, LEDs, power supplies, resistors and switches.

2.2 2.2 Usi

Using

ng the

the Po

Powe

wer Su

r Supp

pply

ly

To supply power to the breadboard, use the dedicated 5V channel and Ground To supply power to the breadboard, use the dedicated 5V channel and Ground on the far right of the power supply.

on the far right of the power supply. When modifying a circuit, it is important When modifying a circuit, it is important to not perform modiﬁcations on your circuit while the power supply is on to not perform modiﬁcations on your circuit while the power supply is on !!

2.3 2.3 Wir

Wiring

ing Sw

Switc

itche

hes fo

s for In

r Input

putss

To safely provide proper inputs, we must ensure that the input pin of a device To safely provide proper inputs, we must ensure that the input pin of a device get

gets a s a stesteady Logady Logic 0 ic 0 or Logic 1. or Logic 1. ThiThis s is done by wirinis done by wiring a g a swiswitctch in h in a mannea mannerr tha

that t useuses s a a pulpull l dodown resiswn resistortor. . A A pulpull l dodown resiswn resistor sertor serveves s as a as a metmethod tohod to con

controtrol l the currthe currenent t ﬂoﬂowinwing g thrthrougough h a a devdeviceice. . ThiThis s is is the reasthe reason why on why LEDLEDss req

requiruire e resresististors in ors in serseriesies. . If the switcIf the switch h is open, is open, the inputhe input t pin has a pin has a resresististoror and Grou

and Ground connend connectected d whicwhich h lealeads to ds to 0 0 VVoltolts. s. WheWhen n the switthe switch is ch is cloclosedsed, , aa connection to V

connection to VCCCC is formed so that the input pin can receive 5 Volts without is formed so that the input pin can receive 5 Volts without

a short circuit. The implementation of this is shown in Figure 19. a short circuit. The implementation of this is shown in Figure 19.

Figure 19: Switch with a Pull Down Resistor Figure 19: Switch with a Pull Down Resistor

2.4 2.4 Th

The 7404

e 7404, 7408 an

, 7408 and 7432 In

d 7432 Integ

tegra

rated Ci

ted Circu

rcuits

its

In this lab experiment, the student must verify the truth tables of the three basic In this lab experiment, the student must verify the truth tables of the three basic digita

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on integr

on integrated circuiated circuits. ts. The 7404 is The 7404 is an integran integrated circuated circuit that provideit that provides 6 s 6 NOTNOT gates, 4 AND gates are provided on the 7408 and lastly, 4 OR gates are built gates, 4 AND gates are provided on the 7408 and lastly, 4 OR gates are built in

into to the 7432. the 7432. EacEach h inintegtegratrated ed circircuicuit t has its has its owown n lalayoyout ut of what of what pinpins s serserveve wha

what functt functionion. . TTo know what eaco know what each pin h pin doesdoes, , aa pin-out diagram pin-out diagram provides the provides the layout of the integrated circuit in question. The pin-out diagrams for the 7404, layout of the integrated circuit in question. The pin-out diagrams for the 7404, 7408 and 7432 are shown in Figures 20, 21 and 22.

7408 and 7432 are shown in Figures 20, 21 and 22.

Figure 20: 7404 Pin-Out Diagram Figure 20: 7404 Pin-Out Diagram

2.5 2.5 Ste

Step 0

p 0:

: Wir

Wiring

ing th

the B

e Brea

readbo

dboard

ard

Before any circuit can be constructed, the breadboard must ﬁrst be wired Before any circuit can be constructed, the breadboard must ﬁrst be wired prop-erly to ensure that all the rails are powe

erly to ensure that all the rails are powered. red. Wire eacWire each red rail to h red rail to VVCCCC and each and each

blue rail to Ground. blue rail to Ground.

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2.6 2.6 Ste

Step 1:

p 1: Con

Contro

trolli

lling a

ng an LE

n LED By a S

D By a Swit

witcch

h

The ﬁrst portion of the lab experiment is to wire an LED controlled by a switch. The ﬁrst portion of the lab experiment is to wire an LED controlled by a switch. When the switch is closed, the LED should be powered. The circuit is provided When the switch is closed, the LED should be powered. The circuit is provided in Figure 23.

in Figure 23. TTake speake special noticcial notice e of how of how the LED the LED is wireis wired d in in the schematicthe schematic.. Make sure the anode is wired to V

Make sure the anode is wired to V CC CC and the needed resistor is placed in the and the needed resistor is placed in the

circuit. circuit.

Figure 23: Schematic for a Switch Controlled LED Figure 23: Schematic for a Switch Controlled LED

2.7 2.7 Ste

Step 2:

p 2: T

Test

estin

ing the 7

g the 7404

404, 740

, 7408 and 7

8 and 7432

432

In this portion of the lab experiment, the truth tables for NOT, AND and OR In this portion of the lab experiment, the truth tables for NOT, AND and OR functions are to be checked. Outputs are to be driven by LEDs so that when the functions are to be checked. Outputs are to be driven by LEDs so that when the outpu

output is a t is a Logic 1, the LED is on Logic 1, the LED is on and oand oﬀ ﬀ _{when the outp}_{when the output is a}_{ut is a Logic 0.}_{Logic 0. Remem}

Remem--ber to wire V

ber to wire VCCCC and Ground correc and Ground correctly! tly! Ask your lab demonstraAsk your lab demonstrator to verifytor to verify

before powering on the circuit.

before powering on the circuit. Note: Note: FFor more informatior more information on on drawion drawing ng lologic gic diagrams and schematics, please see the section A Note on Circuit Schematics. diagrams and schematics, please see the section A Note on Circuit Schematics.

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3 3 La

Lab Ex

b Exper

perim

imen

ent 1

t 1:

: Th

The Ha

e Half A

lf Add

dder

er

3.1 3.1 In

Introd

troduc

uctio

tion

n

In this lab experiment, a simple combinational circuit is to be designed and In this lab experiment, a simple combinational circuit is to be designed and assem

assembled from the basic three gates. bled from the basic three gates. AA combinational circuit combinational circuit is a circuit that is a circuit that has an output a

has an output aﬀ ﬀ _{ected by inputs. If a combinational circuit has n inputs, then}_{ected by inputs. If a combinational circuit has n inputs, then}

it has up to 2 it has up to 2nn

possible scen

possible scenarios to providarios to provide outputs. e outputs. There is no memory inThere is no memory in these circuits to use when producing the output.

these circuits to use when producing the output.

3.

3.2 2 Th

The

e Ha

Half

lf Ad

Adde

derr

The circuit in question is a

The circuit in question is a half adder half adder , a simple circuit that can add up to two., a simple circuit that can add up to two. It has two inpu

It has two inputs, A ts, A and B, and B, and twand two o outoutputputs, s, sum and carrsum and carry y outout. . The trutThe truthh table for a half adder is shown in Table 4.

table for a half adder is shown in Table 4. A A B B CCaarrrry y OOuut t SSuumm 0 0 00 00 00 0 0 11 00 11 1 1 00 00 11 1 1 11 11 00

Table 4: Truth Table for the Half Adder Table 4: Truth Table for the Half Adder

3.3 3.3 Ste

Step 0: Simp

p 0: Simplif

lify th

y the F

e Fun

uncti

ction

on

The ﬁrst step of this experiment is to simplify the circuit in such a manner that The ﬁrst step of this experiment is to simplify the circuit in such a manner that it can b

it can be implemene implemented by using only the 7404, 7408 and ted by using only the 7404, 7408 and 74327432. . This circuit onlyThis circuit only requires one IC of each type.

requires one IC of each type.

3.4 3.4 Ste

Step 1: Impl

p 1: Impleme

ement

nt the

the Cir

Circu

cuit

it

Thi

This s portportion of ion of the lab experithe lab experimenment t is is to build the to build the actactual circual circuituit. . ShoShow w yoyourur lab demonst

lab demonstrator yourator your functioninr functioning circuit. g circuit. The inputs must be The inputs must be concontrolletrolled byd by switches and outputs must drive LEDs.

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4 4 La

Lab Expe

b Experi

rime

men

nt 2:

t 2: La

Latc

tches a

hes and Fl

nd Flip

ip-F

-Flo

lops

ps

4.1 4.1 In

Introd

troduc

uctio

tion

n

Thi

This s lab experilab experimenment t is is abouabout t seqsequenuentiatial l circircuicuits. ts. A A seqsequenuentiatial l circircuicuit t didiﬀ ﬀ _ers_ers

from a

from a comcombinatbinational circuit since it ional circuit since it has memoryhas memory. . The two primitiThe two primitive types of ve types of memo

memory elemenry elements are to ts are to be built: be built: a latch and a flip-fop. a latch and a flip-fop. A latch immedA latch immediateliatelyy responds to its inputs, while a flip-flop requires an enable of sorts.

responds to its inputs, while a ﬂip-ﬂop requires an enable of sorts.

4.

4.2 2 Th

The

e S-

S-R

R La

Latc

tch

h

The S-R Latc

The S-R Latch is h is the most basic forthe most basic form of memory elemm of memory element possibent possible. le. It can beIt can be built multiple ways but in this lab, the NAND implementation is chosen and built multiple ways but in this lab, the NAND implementation is chosen and sho

shown in Figurwn in Figure 24. e 24. The outThe outputput Q Q is is the datthe data outpua output of t of the memthe memoryory. . TheThe behavior of this S-R Latch is shown in Table 5. When

behavior of this S-R Latch is shown in Table 5. When S S andand R R are both equal are both equal to a Logic 0, the latch enters an undesirable, indeterminate state.

to a Logic 0, the latch enters an undesirable, indeterminate state.

Figure 24: NAND S-R Latch Figure 24: NAND S-R Latch

S

S RR QQ QQ

0

0 0 0 IInnvvaalilid d SSttaattee 0 0 1 1 1 1 00 1 1 0 0 0 0 11 1 1 1 1 NNo o CChhaannggee

Table 5: Truth Table for the S-R Latch Table 5: Truth Table for the S-R Latch

4.

4.3 3 Th

The

e D

D Fl

Flip

ip-F

-Flo

lop

p

The S-R Latch can be impro

The S-R Latch can be improved upon. ved upon. By adding a few componenBy adding a few components, a D ts, a D FlipFlip Flo

Flop p can be can be forformedmed. . The advThe advanantagtages of es of the D the D FlipFlip-Fl-Flop is op is thathat t it is it is easeasier toier to handle with only one data input and it does not allow for the flip-flop to enter handle with only one data input and it does not allow for the flip-flop to enter the indeterm

the indeterminate state. inate state. AdditiAdditionallyonally, , an enable input an enable input is is also placed onto thealso placed onto the ﬂip-ﬂop. The behaviour is detailed in Table 6.

ﬂip-ﬂop. The behaviour is detailed in Table 6. There are tw

There are two ways a Flip-flop can respond to the enable input. o ways a Flip-flop can respond to the enable input. The firstThe first wa

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D D E E QQ QQ X X 0 0 NNo o CChhaannggee 0 0 1 1 0 0 11 1 1 1 1 1 1 00 T

Table 6: able 6: TTruth Taruth Table for ble for the D the D Flip-FFlip-Floplop

be changed. The other method is called edge triggered and is when the flip-flop be changed. The other method is called edge triggered and is when the flip-flop respond

responds to s to the chanthe change in ge in the enable signal. the enable signal. When the flip-flop is triggereWhen the flip-flop is triggered byd by the enable going high to low, the flip-flop is said to be negative-edge triggered. If the enable going high to low, the flip-flop is said to be negative-edge triggered. If the flip-flop is triggered by the enable signal going high, it is called positive-edge the flip-flop is triggered by the enable signal going high, it is called positive-edge trigg

triggered. ered. An edge-triAn edge-triggereggered flip-flop is d flip-flop is far more desirable due to far more desirable due to the change inthe change in data being nearly instantaneous, while the level-triggered flip-flop provides an data being nearly instantaneous, while the level-triggered flip-flop provides an opportu

opportunity to havnity to have data modiﬁed. e data modiﬁed. A block diagram of the level triggerA block diagram of the level triggered Ded D Flip-F

Flip-Flops is lops is showshown in n in Figure 25. Figure 25. On the On the left is an left is an edge-edge-triggetriggered flip-flop andred flip-flop and on the

on the righright is t is a level-tra level-triggeriggered flip-flop. ed flip-flop. Figure 26 details the implemenFigure 26 details the implementatiotationn of the level-triggered D Flip-Flop.

of the level-triggered D Flip-Flop.

Figure 25: D Flip-Flop Block Diagrams Figure 25: D Flip-Flop Block Diagrams

Figure 26: Level-Triggered D Flip-Flop Implementation Figure 26: Level-Triggered D Flip-Flop Implementation

4.4 4.4 Ste

Step 0: Asse

p 0: Assemb

mble t

le the

he S-R

S-R Lat

Latch

ch

The ﬁrst step in this lab experiment is to assemble the S-R latch. Since NAND The ﬁrst step in this lab experiment is to assemble the S-R latch. Since NAND gates are not available, an equivalent circuit can be made by using an AND gates are not available, an equivalent circuit can be made by using an AND

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gate with a NOT gate connected to its output. An example of this is shown in gate with a NOT gate connected to its output. An example of this is shown in Figure 27. Show your lab demonstrator the functioning circuit.

Figure 27. Show your lab demonstrator the functioning circuit.

Figure 27: Implementation of a NAND Gate Figure 27: Implementation of a NAND Gate

4.5 4.5 Ste

Step 1: Asse

p 1: Assemb

mble t

le the

he D F

D Flip

lip-Fl

-Flop

op

Once the S-R latch has been built and veriﬁed

Once the S-R latch has been built and verified, it , it is time to is time to build the D flip-flop.build the D flip-flop. The variant implemented is a level-triggered flip-flop as seen in Figure 26. When The variant implemented is a level-triggered flip-flop as seen in Figure 26. When done, show your lab demonstrator the functioning circuit.

done, show your lab demonstrator the functioning circuit.

4.6 4.6 *Ste

*Step 2:

p 2: Buil

Build A P

d A Posit

ositiv

ive-Ed

e-Edge T

ge Trigg

riggered

ered D Flip

D Flip-Flo

-Flop

p

If there is time remaining in the lab period, a positive-edge triggered D flip-flop If there is time remaining in the lab period, a positive-edge triggered D flip-flop can be built from two level-triggered D flip-flops. A block diagram is shown in can be built from two level-triggered D flip-flops. A block diagram is shown in Fig

Figure 28. ure 28. If the If the invinverterter was er was momoveved d so that so that the enabthe enable le wawas s ininveverterted d on theon the leftm

leftmost D ost D flip-flflip-flop, it op, it woulwould d act as act as a negativea negative-edge trigg-edge triggered D ered D flip-flflip-flop. op. ThisThis method is called the

method is called the master-slave master-slave implementation. implementation.

Figure 28: Implementation of a Positive-Edge Triggered D Flip-Flop Figure 28: Implementation of a Positive-Edge Triggered D Flip-Flop

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5 5 Projec

Project

t Exper

Experime

iment

nt 0:

0: The

The Tim

Timing

ing Sig

Signal

nal Gen

Gen--erator

erator

5.1 5.1 In

Introd

troduc

uctio

tion

n

In this project experimen

In this project experiment, the t, the timintiming signal generatg signal generator is or is built. built. This is This is essen essen--tial for the project since the timing signal generator produces the clock signal, tial for the project since the timing signal generator produces the clock signal, important enable signals and will dictate how fast the computer will function. important enable signals and will dictate how fast the computer will function. Before demonstrating the circuit, a few deﬁnitions and devices must be reviewed. Before demonstrating the circuit, a few deﬁnitions and devices must be reviewed.

5.2 5.2 Du

Duty

ty Cyc

Cycle a

le and F

nd Freq

requen

uency

cy

The ﬁrst

The ﬁrst term that is term that is of interesof interest t is is freqfrequencyuency. . FFrequerequency is ncy is how fast somethinhow fast somethingg may alternate or repeat. It is measured in Hz and is deﬁned as

may alternate or repeat. It is measured in Hz and is deﬁned as

f f ss = = 11 T T ss T

Tss is the period (in seconds) of how long the signal lasts until it is repeated. is the period (in seconds) of how long the signal lasts until it is repeated.

To calculate the duty cycle, use the following equation where t is the amount of To calculate the duty cycle, use the following equation where t is the amount of time that the signal is set to a logic 1:

time that the signal is set to a logic 1:

DC DC = = tt

T T ss

5.

5.3 3 Ti

Timi

ming

ng Di

Diag

agra

rams

ms

A timing diagram is a useful tool to determine how a system may operate when A timing diagram is a useful tool to determine how a system may operate when sig

signalnals s are bounare bound d to chanto change. ge. It is It is simsimply compoply composed of a sed of a timtime e axiaxis s and all theand all the signals of concern. Figure 29 demonstrates how the duty cycle and period may signals of concern. Figure 29 demonstrates how the duty cycle and period may look on

look on a a timtiming diaging diagramram. . In this examIn this exampleple, , the freqthe frequenuency is cy is 50 MHz 50 MHz (wh(whicichh gives a timescale in nanoseconds). The period is found to be 20 ns. If we were gives a timescale in nanoseconds). The period is found to be 20 ns. If we were to use the frequency equation, it can easily be seen that the frequency is in fact to use the frequency equation, it can easily be seen that the frequency is in fact 50 MHz.

50 MHz.

Figure 29: Sample Timing Diagram Figure 29: Sample Timing Diagram

5.4 5.4 A Re

A Revie

view on O

w on Ord

rders o

ers of Ma

f Magni

gnitud

tude

e

Before proceeding further, a review on orders of magnitude is necessary. Table 7 Before proceeding further, a review on orders of magnitude is necessary. Table 7 displays the orders of magnitude to be mindful of.

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Or

Ordeder r of of MaMagngnititudude e PrPreﬁeﬁxx 10 1099 Giga (G) Giga (G) 10 1066 Mega (M) Mega (M) 10 1033 Kilo (K) Kilo (K) 10 10−−33 Milli (m)Milli (m) 10 10−−66 Micro (Micro (µµ)) 10 10−−99 Nano (n)Nano (n)

Table 7: Orders of Magnitude Table 7: Orders of Magnitude

5.

5.5 5 Th

The

e 55

555 5 Ti

Time

merr

At the core of the Timing Signal Generator circuit, a versatile integrated circuit At the core of the Timing Signal Generator circuit, a versatile integrated circuit cal

called the 55led the 555 Timer is used5 Timer is used. . The 555 diThe 555 diﬀ ﬀ _{ers from all the integrated circuits}_{ers from all the integrated circuits}

use

used at d at thithis point sincs point since it e it is an is an 8 pin 8 pin devdeviceice. . ThiThis device has mans device has many modes of y modes of operation but in this lab, it is only used in

operation but in this lab, it is only used in astable astable mode so that it can provide mode so that it can provide a signal that alternates between a logic 0 and logic 1 as seen in Figure 29. The a signal that alternates between a logic 0 and logic 1 as seen in Figure 29. The pin-out diagram for the 555 timer is shown in Figure 30.

pin-out diagram for the 555 timer is shown in Figure 30.

Figure 30: 555 Timer Pin-Out Diagram Figure 30: 555 Timer Pin-Out Diagram Like any integrated circuit used in this lab, the V

Like any integrated circuit used in this lab, the VCCCC and GND pins must be and GND pins must be

conne

connected for the device to operate. cted for the device to operate. AnothAnother thing worth notiner thing worth noting is g is that the 4ththat the 4th pin is a reset pin. To reset the 555 timer,

pin is a reset pin. To reset the 555 timer, R RST ST must be a logic 0 so to prevent must be a logic 0 so to prevent the device from constantly resetting, it is wired directly to V

the device from constantly resetting, it is wired directly to VCCCC. The clock pulse. The clock pulse

is generated by using an RC (resistor and capacitor) circuit and measuring its is generated by using an RC (resistor and capacitor) circuit and measuring its voltage. This RC circuit constantly charges and discharges. Inside the 555 timer voltage. This RC circuit constantly charges and discharges. Inside the 555 timer is a flip flop which switches value when the voltage in the RC circuit reaches is a flip flop which switches value when the voltage in the RC circuit reaches

1 1 3 3 VVCCCC oror 2 2 3

3 VVCCCC. . The vaThe value at the output of the timelue at the output of the timer is r is the vthe value of the ﬂipalue of the ﬂip

ﬂop.

ﬂop. TTo build o build a clock signal generatoa clock signal generator, the r, the freqfrequency and the duty cycle mustuency and the duty cycle must be known. Two equations are used for determining these values. To determine be known. Two equations are used for determining these values. To determine

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the frequency, the following equation is used: the frequency, the following equation is used:

f f ss = = 11 T T ss = = 11..4444 ((RR11 + 2 + 2RR22))C C 22

To determine the duty cycle, the following equation can be used: To determine the duty cycle, the following equation can be used:

D

D = = RR22

R

R11 + 2 + 2RR22

Figure

Figure below shobelow shows a ws a typtypical astable circical astable circuit with the output of the timer calleduit with the output of the timer called CLK (Cloc

CLK (Clock). k). NotNote how pin 4, e how pin 4, the resthe reset pin, is et pin, is wirwired to Ved to VCCCC. . The caThe capacpacitoitorr

C1 is

C1 is optiooptional but desirable to havnal but desirable to have because it can e because it can reducreduce noise. e noise. EveEven thoughn though pin 1 and 8 are not shown, they are wired to their respective V

pin 1 and 8 are not shown, they are wired to their respective VCCCC and Ground and Ground

rails. rails.

Figure 31: 555 Timer Astable Circuit Figure 31: 555 Timer Astable Circuit

5.6 5.6 Th

The 74

e 74LS1

LS164 S

64 SIPO S

IPO Shif

hift Re

t Regis

gister

ter

The other integrated circuit of interest in this lab experiment is the 74LS164 The other integrated circuit of interest in this lab experiment is the 74LS164 SIPO (Seria

SIPO (Serial In, l In, ParaParallel Out) Shift Registellel Out) Shift Register. r. This device takThis device takes an input andes an input and shift

shifts all s all the contethe contents by one output every clock cycle. nts by one output every clock cycle. It has It has 8 outputs which8 outputs which can all be accessed at any time but only one input. A shift register moves values can all be accessed at any time but only one input. A shift register moves values from one intern

from one internal flip al flip flop to flop to the next. the next. The 74LS164 moThe 74LS164 moves vaves values from Qlues from QAA toto

Q

QHH. . A A gragraph showph showing this behaing this behaviovior r for a for a 4 4 bit SIPO shifbit SIPO shift t regregistister is er is seeseen n inin

Figure 32. The pin-out diagram for the 74LS164 is shown in Figure 33. Figure 32. The pin-out diagram for the 74LS164 is shown in Figure 33.

Figure 32:

Figure 32: Shift RegisteShift Register r BehaBehaviorvior To wire the 74LS164 correctly, pin 14 must be wired to V

To wire the 74LS164 correctly, pin 14 must be wired to VCCCC and pin 7 to and pin 7 to

Groun

Ground. d. The outputThe outputs are the pins that correspond to Qs are the pins that correspond to QAA to to QQHH where Q where QAA isis

the ﬁrst output stage.

lab Manual soen 228

SOEN 228/298 Lab Manual

SOEN 228/298 Lab Manual

Contents

Contents

List of Figures

List of Figures

List of Tables

List of Tables

1

1 In

Intr

trod

oduc

ucti

tion

on

1.1

1.1 Re

Repre

presen

sentin

ting

g Bin

Binary

ary

1.2

1.2 Com

Common

monly U

ly Used

sed Pa

Parts

rts in t

in the L

he Lab

ab

1.3

1.3 Bas

Basic

ic Log

Logic

ic F

Fun

unct

ction

ionss

2

2 Lab

Lab Exper

Experime

iment

nt 0:

0: In

Introdu

troducti

ction

on to

to the

the Bre

Bread-

ad-board and Electronic Circuits

board and Electronic Circuits

2.1

2.1 In

Introd

troduc

uctio

tion to La

n to Lab Expe

b Experim

rimen

ent 0

t 0

2.2

2.2 Usi

Using

ng the

the Po

Powe