5 5 4 4 3 3 2 2 1 1 D D C C B B A A
2.5V & 2.8V & 3.3V
12
02.01
02.05
MAX 10 Clocks & Configuration
8
02.06
USB Blaster II
05.01
Expansion Headers - BBB Headers
1
Page
15
11
02.0
01.0
Title
Cover Page
Section
Block Diagram
1.01
2
Design Introduction
4
3
1.02
6
5
7
MAX 10 10M50DAF484
MAX 10 BANK3 & BANK4
02.02
MAX 10 BANK1 & BANK2
02.04
02.03
MAX 10 BANK5 & BANK6
MAX 10 BANK7 & BANK8
MAX10 Power & GND
05.0
Expansion Port
06.0
Memory
06.01
DDR3 SDRAM & QSPI Flash
06.02
SD Card
07.01
20
08.01
Accelerometer
Ethernet
09.02
USB PHY
09.01
08.0
SMA Connectors & Differential Amplifier
Page
Ethernet
22
23
24
07.0
Title
MIPI Interface
Section
HDMI TX
16
17
07.02
19
18
Audio CODEC
09.0
USB PHY
10.0
Analog Interface
10.01
Gesture, Humidity, Temperature Sensors
11.02
11.0
Sensors
LED & BUTTON & SWITCH
11.01
12.01
12.0
User Interface
1.2V & 1.5V & 1.8V & 5V
13
14
25
21
System Power
MAX10 Decoupling
Clock
02.07
9
13.0
13.01
DECA
Clock
03.0
03.01
10
04.0
04.01
JTAG
Video & Audio
07.03
13.02
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Cover Page C
DECA
B 1 25 Wednesday, March 11, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Cover Page C
DECA
B 1 25 Wednesday, March 11, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Cover Page C
DECA
B1 25
5 4 3 2 1 D D C C B B A A Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Block Diagram C
DECA
B 2 25 Thursday, March 19, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Block Diagram C
DECA
B 2 25 Thursday, March 19, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Block Diagram C
DECA
B2 25
5 5 4 4 3 3 2 2 1 1 D D C C B B A A
CAD Notes:
1. Put all the 1pF caps close to each MAX10 analog pin.
2. Route the analog input signal adjacent to the REFGND.
VCCIO = 2.5V
VCCIO = 2.5V
VCCIO = 2.5V
Audio LINE-IN to MAX10 ADC
Ethernet
MIPI I2C Interface
MIPI Interface
MIPI Control Interface
Header Analog Input
ADC1IN1 ADC1IN2 ADC1IN3 ADC1IN5 ADC1IN6 ADC1IN7 ADC1IN4 ADC1IN1 ADC1IN2 ADC1IN3 ADC1IN4 ADC1IN5 ADC1IN6 ADC1IN7 REFGND LINE_IN_L_ADC MIPI_MD_p0 MIPI_MD_n0 MIPI_MD_p1 MIPI_MD_n1 MIPI_MD_p2 MIPI_MD_n2 MIPI_MD_p3 MIPI_MD_n3 NET_RX_ER NET_RX_DV NET_TXD3 NET_RXD3 NET_TXD0 NET_RXD0 NET_RXD1 NET_CRS NET_COL NET_TXD1 NET_TXD2 MIPI_MD_p3 MIPI_MD_n3 MIPI_MD_p2 MIPI_MD_n2 MIPI_MD_p1 MIPI_MD_n1 MIPI_MD_p0 MIPI_MD_n0 MIPI_I2C_SDA MIPI_I2C_SCL MIPI_RESET_n MIPI_MCLK MIPI_CORE_EN NET_MDC MIPI_WP NET_RXD2 NET_MDIO AIN0 12 AIN1 12 AIN2 12 AIN3 12 AIN4 12 AIN5 12 AIN6 12 LINE_IN_L_ADC 17 NET_TXD[3..0] 18 NET_RX_ER 18 NET_RX_DV 18 NET_COL 18 NET_CRS 18 NET_RXD[3..0] 18 MIPI_MD_p[3..0] 15 MIPI_MD_n[3..0] 15 MIPI_MC_p 7,15 MIPI_MC_n 7,15 MIPI_RESET_n 15 MIPI_MCLK 15 MIPI_WP 15 MIPI_CORE_EN 15 MIPI_I2C_SDA 15 MIPI_I2C_SCL 15 AIN[6..0] 12 NET_MDC 18 NET_MDIO 18 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 1, Bank 2 C
DECA
B3 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 1, Bank 2 C
DECA
B3 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 1, Bank 2 C
DECA
B 3 25 Wednesday, March 11, 2015 R178 10 C126 1p R179 10 C125 1p R219 100 R180 10 C124 1p R181 10 R221 100 REFGND1 DNI R230 100 C123 1p R51 10 C24 1p R50 10 C25 1p R49 10 C26 1pMAX 10 LEFT BANKS
BANK-2
BANK-1A
BANK-1B
10M50DAF484C6GES U1A DIFFIO_RX_L1N/ADC1IN1 F5 DIFFIO_RX_L1P/ADC1IN2 F4 DIFFIO_RX_L2N/ADC2IN1 E4 DIFFIO_RX_L2P/ADC2IN8 E3 DIFFIO_RX_L3N/ADC1IN3 J8 DIFFIO_RX_L3P/ADC1IN4 J9 DIFFIO_RX_L4N/ADC2IN3 G4 DIFFIO_RX_L4P/ADC2IN4 F3 DIFFIO_RX_L5P/ADC1IN6 H3 DIFFIO_RX_L5N/ADC1IN5 J4 DIFFIO_RX_L6N/ADC2IN5 H4 DIFFIO_RX_L6P/ADC2IN6 G3 DIFFIO_RX_L7N/ADC1IN7 K5 DIFFIO_RX_L7P/ADC1IN8 K6 DIFFIO_RX_L8P/ADC2IN2 J3 DIFFIO_RX_L8N/ADC2IN7 K4 DIFFIO_RX_L15N K8 VREFB1N0 C1 DIFFIO_RX_L19N K2 DIFFIO_RX_L19P L2 DIFFIO_RX_L23N G1 DIFFIO_RX_L21P F2 DIFFIO_RX_L23P F1 DIFFIO_RX_L21N E1 DIFFIO_RX_L24N M4 DIFFIO_RX_L24P M3 DIFFIO_RX_L25N K1 DIFFIO_RX_L25P L1 DIFFIO_RX_L16P D2 IO_BANK1 D1 DIFFIO_RX_L29N P4 DIFFIO_RX_L29P P5 DIFFIO_RX_L37N N3 DIFFIO_RX_L37P N2 DIFFIO_RX_L39N R4 DIFFIO_RX_L39P R5 DIFFIO_RX_L40N T1 DIFFIO_RX_L40P T2 DIFFIO_RX_L41N N8 DIFFIO_RX_L41P N9 DIFFIO_RX_L42N P1 DIFFIO_RX_L42P N1 DIFFIO_RX_L43N T3 DIFFIO_RX_L43P U2 DIFFIO_RX_L44N U1 DIFFIO_RX_L44P V1 DIFFIO_RX_L45N U4 DIFFIO_RX_L45P U5 DIFFIO_RX_L46N U3 DIFFIO_RX_L46P V3 DIFFIO_RX_L47N P8 DIFFIO_RX_L47P R7 DIFFIO_RX_L48N W1 DIFFIO_RX_L48P W2 DIFFIO_RX_L60N R1 DIFFIO_RX_L60P R2 VREFB2N0 M2 IO_BANK2 M1 DIFFIO_RX_L16N D3 DIFFIO_RX_L20N L8 DIFFIO_RX_L20P L9 DIFFIO_RX_L22N H1 DIFFIO_RX_L22P J1 R220 1005 4 3 2 1 D D C C B B A A
VCCIO = 3.3V
VCCIO = 3.3V
QSPI Flash
Header GPIO
Temperature Sensor
Humidity and Temperature Sensor
Gesture Sensor
Power Monitor
CapSense Buttons
Micro SD Card
GPIO1_D17 TEMP_CS_n GPIO1_D0 GPIO1_D12 GPIO1_D2 GPIO1_D3 GPIO1_D4 GPIO1_D16 FLASH_RESET_n GPIO1_D7 GPIO1_D5 GPIO1_D18 FLASH_NCSO GPIO1_D20 FLASH_DATA3 GPIO1_D15 GPIO1_D1 GPIO1_D13 GPIO1_D11 RH_TEMP_I2C_SCL RH_TEMP_I2C_SDA RH_TEMP_DRDY_n LIGHT_I2C_SCL LIGHT_I2C_SDA LIGHT_INT GPIO1_D10 GPIO1_D9 GPIO1_D6 GPIO1_D22 GPIO1_D19 SYS_RESET_n TEMP_SIO TEMP_SC FLASH_DCLK FLASH_DATA0 FLASH_DATA1 FLASH_DATA2 PMONITOR_I2C_SCL PMONITOR_I2C_SDA PMONITOR_ALERT CAP_SENSE_I2C_SCL CAP_SENSE_I2C_SDA SD_SEL PWR_BUT GPIO0_D38 GPIO0_D30 GPIO0_D29 GPIO0_D28 GPIO0_D27 GPIO0_D10 GPIO0_D40 GPIO0_D18 GPIO0_D15 GPIO0_D14 GPIO0_D11 GPIO0_D9 GPIO0_D8 GPIO0_D7 GPIO0_D6 GPIO0_D33 GPIO0_D32 GPIO0_D16 GPIO0_D22 GPIO0_D26 GPIO0_D41 GPIO0_D31 GPIO0_D20 GPIO0_D19 GPIO0_D42 GPIO0_D3 GPIO0_D12 GPIO0_D25 GPIO0_D17 GPIO0_D2 GPIO0_D5 GPIO0_D1 GPIO0_D4 GPIO0_D21 GPIO0_D23 GPIO0_D24 GPIO0_D0 GPIO0_D37 GPIO0_D36 GPIO0_D39 GPIO0_D34 GPIO0_D35 GPIO0_D43 FLASH_NCSO 13 FLASH_DCLK 13 FLASH_DATA[3..0] 13 FLASH_RESET_n 13 GPIO1_D[22..0] 7,12 TEMP_CS_n 22 RH_TEMP_I2C_SCL 22 RH_TEMP_I2C_SDA 22 RH_TEMP_DRDY_n 22 LIGHT_I2C_SCL 22 LIGHT_I2C_SDA 22 LIGHT_INT 22 SYS_RESET_n 12 GPIO0_D[43..0] 7,12 TEMP_SC 22 TEMP_SIO 22 PMONITOR_I2C_SDA 24 PMONITOR_I2C_SCL 24 PMONITOR_ALERT 24 CAP_SENSE_I2C_SDA 23 CAP_SENSE_I2C_SCL 23 SD_SEL 14 PWR_BUT 12 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 3 & 4 C
DECA
B4 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 3 & 4 C
DECA
B4 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 3 & 4 C
DECA
B4 25
Wednesday, March 11, 2015
BANK-3
BANK-4
MAX 10 BOTTOM BANKS
10M50DAF484C6GES U1B DIFFIO_RX_B10N Y7 DIFFIO_RX_B10P Y8 DIFFIO_RX_B12N AB2 DIFFIO_RX_B12P AB3 DIFFIO_RX_B14N Y3 DIFFIO_RX_B14P Y4 DIFFIO_RX_B17N AA5 DIFFIO_RX_B17P AB5 DIFFIO_RX_B19N AB6 DIFFIO_RX_B19P AB7 DIFFIO_RX_B21N AA8 DIFFIO_RX_B21P AB8 DIFFIO_RX_B23N AA9 DIFFIO_RX_B23P AB9 DIFFIO_RX_B2N V4 DIFFIO_RX_B2P V5 DIFFIO_RX_B4N Y1 DIFFIO_RX_B4P Y2 DIFFIO_RX_B6N AA1 DIFFIO_RX_B6P AA2 DIFFIO_RX_B8N Y5 DIFFIO_RX_B8P Y6 DIFFIO_TX_RX_B11N W9 DIFFIO_TX_RX_B11P W10 DIFFIO_TX_RX_B13N W7 DIFFIO_TX_RX_B13P W8 DIFFIO_TX_RX_B15N R10 DIFFIO_TX_RX_B15P P10 DIFFIO_TX_RX_B16N AA6 DIFFIO_TX_RX_B16P AA7 DIFFIO_TX_RX_B1N W5 DIFFIO_TX_RX_B1P W6 DIFFIO_TX_RX_B22N Y10 DIFFIO_TX_RX_B22P AA10 DIFFIO_TX_RX_B3N U6 DIFFIO_TX_RX_B3P U7 DIFFIO_TX_RX_B5N W4 DIFFIO_TX_RX_B5P W3 DIFFIO_TX_RX_B7N V7 DIFFIO_TX_RX_B7P V8 DIFFIO_TX_RX_B9N R9 DIFFIO_TX_RX_B9P P9 VREFB3N0 AA3 IO_BANK3 AB4 DIFFIO_RX_B25N W11 DIFFIO_RX_B25P Y11 DIFFIO_RX_B27N AB10 DIFFIO_RX_B27P AB11 DIFFIO_RX_B29N AB12 DIFFIO_RX_B29P AB13 DIFFIO_RX_B35N W12 DIFFIO_RX_B35P W13 DIFFIO_RX_B38N AA14 DIFFIO_RX_B38P AB15 DIFFIO_RX_B40N AA15 DIFFIO_RX_B40P Y16 DIFFIO_RX_B42N AB16 DIFFIO_RX_B42P AA16 DIFFIO_RX_B44N AB19 DIFFIO_RX_B44P AB20 DIFFIO_RX_B46N AA19 DIFFIO_RX_B46P Y18 DIFFIO_RX_B50N AB21 DIFFIO_RX_B50P AA20 DIFFIO_RX_B58N AB17 DIFFIO_RX_B58P AB18 DIFFIO_TX_RX_B24N V11 DIFFIO_TX_RX_B24P V12 DIFFIO_TX_RX_B26N R12 DIFFIO_TX_RX_B26P P12 DIFFIO_TX_RX_B28N AA11 DIFFIO_TX_RX_B28P AA12 DIFFIO_TX_RX_B34N V13 DIFFIO_TX_RX_B34P W14 DIFFIO_TX_RX_B36N R13 DIFFIO_TX_RX_B36P P13 DIFFIO_TX_RX_B37N Y13 DIFFIO_TX_RX_B37P Y14 DIFFIO_TX_RX_B39N V14 DIFFIO_TX_RX_B39P W15 DIFFIO_TX_RX_B41N U15 DIFFIO_TX_RX_B41P V16 DIFFIO_TX_RX_B43N AA17 DIFFIO_TX_RX_B43P Y17 DIFFIO_TX_RX_B45N V15 DIFFIO_TX_RX_B45P W16 DIFFIO_TX_RX_B49N Y19 DIFFIO_TX_RX_B49P W18 VREFB4N0 AA13 IO_BANK4 AB14
5 5 4 4 3 3 2 2 1 1 D D C C B B A A
VCCIO = 1.5V
VCCIO = 1.5V
Micro SD Card
Audio CODEC Interface
Audio Control Interface
KEY
SWITCH
DDR3_A1 DDR3_DQS_n1 DDR3_DQS_p1 DDR3_DQ10 DDR3_DQ9 DDR3_DQ11 DDR3_DQ8 DDR3_DM1 DDR3_DQ12 DDR3_DQ15 DDR3_DQ14 DDR3_DQ13 DDR3_DM0 DDR3_A14 DDR3_DQ6 DDR3_DQ7 DDR3_DQ2 DDR3_DQ4 DDR3_DQ0 DDR3_DQ1 DDR3_DQ5 DDR3_DQ3 DDR3_CK_n DDR3_CK_p DDR3_A8 DDR3_CAS_n DDR3_CKE DDR3_A9 DDR3_A4 DDR3_A6 DDR3_RESET_n DDR3_A11 DDR3_A13 DDR3_BA1 DDR3_VREF DDR3_VREF DDR3_BA2 DDR3_A0 DDR3_RAS_n DDR3_WE_n DDR3_A10 DDR3_A2 DDR3_A12 DDR3_A7 DDR3_A5 DDR3_BA0 AUDIO_DOUT_MFP2 AUDIO_SCLK_MFP3 AUDIO_SCL_SS_n AUDIO_SDA_MOSI AUDIO_MISO_MFP4 AUDIO_SPI_SELECT AUDIO_RESET_n AUDIO_GPIO_MFP5 AUDIO_MCLK AUDIO_BCLK AUDIO_WCLK AUDIO_DIN_MFP1 SD_DAT0 SD_DAT1 SD_CLK SD_DAT3 SD_CMD_DIR SD_D0_DIR SD_CMD SD_D123_DIR SD_DAT2 KEY0 KEY1 SW0 SW1 SD_FB_CLK DDR3_A3 DDR3_CS_n DDR3_ODT VCC1P5_DDR3 VCC1P5_DDR3 DDR3_VREF DDR3_RESET_n 13 DDR3_WE_n 13 DDR3_RAS_n 13 DDR3_CAS_n 13 DDR3_ODT 13 DDR3_BA[2..0] 13 DDR3_DQ[ 15..0] 13 DDR3_DQS_p[1..0] 7,13 DDR3_DQS_n[1..0] 7,13 DDR3_DM[1..0] 13 DDR3_A[14..0] 13 DDR3_CK_p 13 DDR3_CK_n 13 DDR3_CKE 13 DDR3_CS_n 13 SD_CLK 14 SD_D0_DIR 14 SD_D123_DIR 14 SD_CMD_DIR 14 SD_DAT[3..0] 14 SD_CMD 14 AUDIO_MCLK 17 AUDIO_BCLK 17 AUDIO_WCLK 17 AUDIO_DIN_MFP1 17 AUDIO_DOUT_MFP2 17 AUDIO_SCLK_MFP3 17 AUDIO_SCL_SS_n 17 AUDIO_SDA_MOSI 17 AUDIO_MISO_MFP4 17 AUDIO_SPI_SELECT 17 AUDIO_RESET_n 17 AUDIO_GPIO_MFP5 17 SW[1..0] 23 KEY[1..0] 23 SD_FB_CLK 14 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 5 & 6 C
DECA
B5 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 5 & 6 C
DECA
B5 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 5 & 6 C
DECA
B5 25
Wednesday, March 11, 2015
BANK-5
BANK-6
MAX 10 RIGHT BANKS
10M50DAF484C6GES U1C DIFFIO_RX_R19N U19 DIFFIO_RX_R19P V18 DIFFIO_RX_R1N/RDN U17 DIFFIO_RX_R1P/RUP U18 DIFFIO_RX_R20N W22 DIFFIO_RX_R20P Y22 DIFFIO_RX_R21N W20 DIFFIO_RX_R21P W19 DIFFIO_RX_R22N Y21 DIFFIO_RX_R22P Y20 DIFFIO_RX_R23N U20 DIFFIO_RX_R23P V20 DIFFIO_RX_R24N V22 DIFFIO_RX_R24P V21 DIFFIO_RX_R25N/DQ1R R14 DIFFIO_RX_R25P/DQ1R R15 DIFFIO_RX_R26N T22 DIFFIO_RX_R26P T21 DIFFIO_RX_R27N/DM1R T18 DIFFIO_RX_R27P/DQ1R T19 DIFFIO_RX_R28N/DQ1R R20 DIFFIO_RX_R28P/DQ1R T20 DIFFIO_RX_R29N U22 DIFFIO_RX_R29P U21 DIFFIO_RX_R2N AA22 DIFFIO_RX_R2P AA21 DIFFIO_RX_R30N/DQ1R P14 DIFFIO_RX_R30P/DQ1R P15 DIFFIO_RX_R31N N22 DIFFIO_RX_R31P P21 DIFFIO_RX_R32N/DQSN1R P18 DIFFIO_RX_R32P/DQS1R R18 DIFFIO_RX_R33N/DQ1R P20 DIFFIO_RX_R33P/DQ1R P19 DIFFIO_RX_R34N L22 DIFFIO_RX_R34P M21 DIFFIO_RX_R35N M22 DIFFIO_RX_R35P N21 IO_BANK5 R22 VREFB5N0 P22 DIFFIO_RX_R39N H21 DIFFIO_RX_R39P H22 DIFFIO_RX_R41N J21 DIFFIO_RX_R41P J22 DIFFIO_RX_R42N G19 DIFFIO_RX_R42P G20 DIFFIO_RX_R43N F22 DIFFIO_RX_R43P G22 DIFFIO_RX_R44N/DQ2R M14 DIFFIO_RX_R44P/DQ2R M15 DIFFIO_RX_R45N E21 DIFFIO_RX_R45P E22 DIFFIO_RX_R46N/DM2R N19 DIFFIO_RX_R46P/DQ2R N18 DIFFIO_RX_R47P/DQ2R M20 DIFFIO_RX_R47N/DQ2R N20 DIFFIO_RX_R48N F20 DIFFIO_RX_R48P F21 VREFB6N0 D21 DIFFIO_RX_R49P D22 DIFFIO_RX_R51N/DQ2R L18 DIFFIO_RX_R51P/DQ2R M18 DIFFIO_RX_R52N/DQ2R L20 DIFFIO_RX_R52P/DQ2R L19 DIFFIO_RX_R53N F18 DIFFIO_RX_R53P E19 DIFFIO_RX_R54N E20 DIFFIO_RX_R54P F19 DIFFIO_RX_R55N/DQSN3R K15 DIFFIO_RX_R55P/DQS3R K14 DIFFIO_RX_R56N D19 DIFFIO_RX_R56P C20 DIFFIO_RX_R57N/DQ3R J18 DIFFIO_RX_R57P/DQ3R K18 DIFFIO_RX_R58N/DQ3R K20 DIFFIO_RX_R58P/DQ3R K19 DIFFIO_RX_R59N E17 DIFFIO_RX_R59P F17 DIFFIO_RX_R60N B21 DIFFIO_RX_R60P B22 DIFFIO_RX_R61N/DM3R J15 DIFFIO_RX_R61P/DQ3R J14 DIFFIO_RX_R62N A21 DIFFIO_RX_R62P B20 DIFFIO_RX_R63N/DQ3R H18 DIFFIO_RX_R63P/DQ3R H19 DIFFIO_RX_R64N/DQ3R H20 DIFFIO_RX_R64P/DQ3R J20 DIFFIO_RX_R70N/CK#_6 E18 DIFFIO_RX_R70P/CK_6 D18 DIFFIO_RX_R49N C22 IO_BANK6 C21 R229 49.9 C195 0.1u C89 0.1u DNI C102 0.1u R177 1K R217 49.9 R167 1K
5 4 3 2 1 D D C C B B A A
VCCIO = 1.2V
VCCIO = 1.8V
USB PHY
LED
HDMI TX
HDMI Audio Interface
MIPI Interface
Accelerometer
HDMI_I2S1 HDMI_LRCLK HDMI_TX_HS HDMI_TX_VS HDMI_I2C_SDA HDMI_SCLK HDMI_I2C_SCL HDMI_I2S3 HDMI_I2S2 HDMI_TX_D20 HDMI_TX_D18 HDMI_TX_D8 HDMI_TX_D21 HDMI_TX_D4 HDMI_TX_D16 HDMI_MCLK HDMI_I2S0 HDMI_TX_D11 HDMI_TX_D23 HDMI_TX_D6 HDMI_TX_D14 HDMI_TX_DE HDMI_TX_INT HDMI_TX_D17 HDMI_TX_D10 HDMI_TX_D22 HDMI_TX_D19 HDMI_TX_D15 HDMI_TX_D12 HDMI_TX_D2 HDMI_TX_D1 HDMI_TX_D7 HDMI_TX_D3 HDMI_TX_D5 HDMI_TX_D0 HDMI_TX_D9 HDMI_TX_D13 USB_FAULT_n USB_DATA0 USB_DATA7 USB_DATA4 USB_DATA2 USB_NXT USB_DIR USB_STP USB_CS USB_DATA3 USB_DATA1 USB_DATA5 USB_DATA6 USB_RESET_n HDMI_TX_CLK MIPI_LP_MD_p2 MIPI_LP_MD_n3 MIPI_LP_MD_n0 MIPI_LP_MD_p3 MIPI_LP_MD_n2 MIPI_LP_MD_n1 MIPI_LP_MD_p1 MIPI_LP_MD_p0 LED4 LED6 LED7 LED0 LED1 LED2 LED3 LED5 USB_CLKOUT_NOPLL G_SENSOR_CS_n G_SENSOR_SCLK G_SENSOR_INT1 G_SENSOR_SDO G_SENSOR_INT2 G_SENSOR_SDI USB_DATA[7..0] 19 USB_NXT 19 USB_DIR 19 USB_STP 19 USB_CS 19 USB_RESET_n 19 USB_FAULT_n 19 LED[7..0] 23 HDMI_TX_D[23..0] 16 HDMI_TX_CLK 6,7,16 HDMI_TX_HS 16 HDMI_TX_VS 16 HDMI_TX_DE 16 HDMI_TX_INT HDMI_I2C_SDA 16 HDMI_I2C_SCL 16 HDMI_I2S[3:0] 16 HDMI_MCLK 16 HDMI_LRCLK 16 HDMI_SCLK 16 USB_CLKOUT_NOPLL 19 HDMI_TX_CLK 6,7,16 MIPI_LP_MD_p[3..0]15 MIPI_LP_MD_n[3..0]15 G_SENSOR_SDO 21 G_SENSOR_SDI 21 G_SENSOR_SCLK 21 G_SENSOR_CS_n 21 G_SENSOR_INT1 21 G_SENSOR_INT2 21 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 7 & 8 C
DECA
B6 25
Thursday, March 19, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 7 & 8 C
DECA
B6 25
Thursday, March 19, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Bank 7 & 8 C
DECA
B 6 25 Thursday, March 19, 2015 R168 0BANK-7
BANK-8
MAX 10 TOP BANKS
10M50DAF484C6GES U1D DIFFIO_RX_T10N A17 DIFFIO_RX_T10P A18 DIFFIO_RX_T15N C15 DIFFIO_RX_T15P C16 DIFFIO_RX_T16N A16 DIFFIO_RX_T16P B16 DIFFIO_RX_T17N J13 DIFFIO_RX_T17P H14 DIFFIO_RX_T18N C13 DIFFIO_RX_T18P C14 DIFFIO_RX_T19N B14 DIFFIO_RX_T19P A14 DIFFIO_RX_T1N E15 DIFFIO_RX_T1P E16 DIFFIO_RX_T20N E13 DIFFIO_RX_T20P D14 DIFFIO_RX_T21P E12 DIFFIO_RX_T21N D13 DIFFIO_RX_T22N J12 DIFFIO_RX_T22P H13 DIFFIO_RX_T23N A12 DIFFIO_RX_T23P A13 DIFFIO_RX_T24N D12 DIFFIO_RX_T24P C12 DIFFIO_RX_T25N A10 DIFFIO_RX_T25P A11 DIFFIO_RX_T26N C10 DIFFIO_RX_T26P C11 DIFFIO_RX_T27N B11 DIFFIO_RX_T27P B12 DIFFIO_RX_T28N J11 DIFFIO_RX_T28P H12 DIFFIO_RX_T31N B8 DIFFIO_RX_T31P A9 DIFFIO_RX_T2N C17 DIFFIO_RX_T2P D17 DIFFIO_RX_T30N C9 DIFFIO_RX_T30P B10 DIFFIO_RX_T29P A7 DIFFIO_RX_T29N A8 DIFFIO_RX_T5N F15 DIFFIO_RX_T5P F16 DIFFIO_RX_T6N B19 DIFFIO_RX_T6P C19 DIFFIO_RX_T7N B17 DIFFIO_RX_T7P C18 DIFFIO_RX_T8N A19 DIFFIO_RX_T8P A20 DIFFIO_RX_T9N E14 DIFFIO_RX_T9P D15 IO_BANK7 A15 VREFB7N0 B15 DIFFIO_RX_T39N C7 DIFFIO_RX_T39P C8 DIFFIO_RX_T41N A6 DIFFIO_RX_T41P B7 DIFFIO_RX_T42P D8 DIFFIO_RX_T43N A4 DIFFIO_RX_T43P A5 DIFFIO_RX_T44N E9 DIFFIO_RX_T45P A2 DIFFIO_RX_T45N A3 DIFFIO_RX_T46P B3 DIFFIO_RX_T46N B4 DIFFIO_RX_T49N D5 DIFFIO_RX_T49P C5 DIFFIO_RX_T51N B1 DIFFIO_RX_T51P B2 DIFFIO_RX_T53P C3 VREFB8N0 D7 IO_BANK8 C6 DIFFIO_RX_T47P B5 DIFFIO_RX_T47N C4 DIFFIO_RX_T48P E8 DIFFIO_RX_T53N C2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A
VCCIO = 1.5V
VCCIO = 2.5V
VCCIO = 3.3V
VCCIO = 3.3V
VCCIO = 1.2V
VCCIO = 1.2V
VCCIO = 2.5V
Ethernet
Header GPIO
HDMI TX
DDR3
USB PHY
MIPI Interface
MAX10 CONFIG Status
JTAG Interface
DDR3_DQS_n0 DDR3_DQS_p0 DDR3_CLK_50 ADC_CLK_10 MAX10_CLK2_50 NET_RX_CLK GPIO1_D8 GPIO1_D14 GPIO0_D13 HDMI_TX_CLK USB_CLKOUT USB_CLKIN USB_CLKOUT USB_CLKIN MIPI_LP_MC_n MIPI_LP_MC_p BOOT_SEL BOOT_SEL JTAG_TCK JTAG_TDO JTAG_TMS JTAG_TDI JTAG_EN MIPI_MC_p MIPI_MC_n NCONFIG NSTATUS CONF_DONE MAX10_CLK1_50 GPIO1_D21 NET_RESET_n NET_TX_EN MIPI_MC_p MIPI_MC_n NET_TX_CLK NET_PCF_EN VCC1P2 VCC2P5 DDR3_DQS_p0 13 DDR3_DQS_n0 13 DDR3_CLK_50 10 MAX10_CLK1_50 10 MAX10_CLK2_50 10 NET_RX_CLK 18 GPIO1_D14 12 GPIO1_D8 12 GPIO0_D13 12 HDMI_TX_CLK 6,16 USB_CLOCK 19 MIPI_MC_p 15 MIPI_MC_n 15 JTAG_TCK 11 JTAG_TMS 11 JTAG_TDO 11 JTAG_TDI 11 JTAG_EN 11 NSTATUS 11 CONF_DONE 11 NCONFIG 11 MIPI_LP_MC_p 15 MIPI_LP_MC_n 15 ADC_CLK_10 10 GPIO1_D21 12 NET_TX_CLK 18 NET_RESET_n 18 NET_TX_EN 18 NET_PCF_EN 18 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Clocks & Configuration C
DECA
B7 25
Thursday, March 19, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Clocks & Configuration C
DECA
B7 25
Thursday, March 19, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX 10 Clocks & Configuration C
DECA
B 7 25 Thursday, March 19, 2015MAX 10 Configuration
BANK-1B
BANK-8
10M50DAF484C6GES U1F DIFFIO_RX_L15P/JTAGEN K9 DIFFIO_RX_L17P/TCK G2 DIFFIO_RX_L17N/TMS H2 DIFFIO_RX_L18N/TDI L4 DIFFIO_RX_L18P/TDO M5 DIFFIO_RX_T42N/DEV_CLRN D9 DIFFIO_RX_T44P/DEV_OE D10 NCONFIG H9 BOOT_SEL H10 DIFFIO_RX_T48N/CRC_ERROR F7 DIFFIO_RX_T50P/NSTATUS G9 DIFFIO_RX_T50N/CONF_DONE F8 R258 10KBANK-2
MAX 10 CLOCK
BANK-3
BANK-4
BANK-6
BANK-8
10M50DAF484C6GES U1E DIFFIO_RX_L28N/CLK0N N4 DIFFIO_RX_L28P/CLK0P N5 DIFFIO_RX_L36N/CLK1N M8 DIFFIO_RX_L36P/CLK1P M9 DIFFIO_TX_RX_B18N/CLK6N V9 DIFFIO_TX_RX_B18P/CLK6P V10 DIFFIO_TX_RX_B20N/CLK7N R11 DIFFIO_TX_RX_B20P/CLK7P P11 DIFFIO_RX_R38N/CLK2N N15 DIFFIO_RX_R38P/CLK2P N14 DIFFIO_RX_R40N/CLK3N K21 DIFFIO_RX_R40P/CLK3P K22 DIFFIO_RX_T38N/CLK4N E10 DIFFIO_RX_T38P/CLK4P E11 DIFFIO_RX_T40P/CLK5P J10 DIFFIO_RX_T40N/CLK5N H11 DIFFIO_RX_L38N/DPCLK0 P3 DIFFIO_RX_L38P/DPCLK1 R3 DIFFIO_RX_L59N/PLL_L_CLKOUTN T5 DIFFIO_RX_L59P/PLL_L_CLKOUTP T6 DIFFIO_TX_RX_B57N/PLL_B_CLKOUTN W17 DIFFIO_TX_RX_B57P/PLL_B_CLKOUTP V17 DIFFIO_RX_R50N/DPCLK2/DQSn2R L15 DIFFIO_RX_R50P/DPCLK3/DQS2R L14 DIFFIO_RX_R69N/PLL_R_CLKOUTN G17 DIFFIO_RX_R69P/PLL_R_CLKOUTP H17 DIFFIO_RX_T52N/PLL_T_CLKOUTN E6 DIFFIO_RX_T52P/PLL_T_CLKOUTP D6 R259 10K R171 0 DNI R256 1K R170 0 R218 100 R195 10K R169 0 DNI 1 ON SW2 SW-DIP2 1 2 R257 10K5 4 3 2 1
D D
C C
B B
A A
Place this FB close to MAX10 ADC_VREF
Place filter close to VCCIO1A pins
REFGND VCC1P2_VCC VCC1P2_VCC VCC1P2_VCCD VCC1P2_VCCD VCC2P5 VCC2P5_VCCA VCC2P5_VCCA VCC1P2_VCC 1.2V_VDDADC 1.2V_VDDADC VCC2P5 VCC2P5_VCCAADC VCC2P5_VCCAADC VCC2P5_VREF VCC2P5 VCC2P5 VCC2P5 VCC3P3 VCC3P3 VCC1P5_DDR3 VCC1P5_DDR3 VCC1P8 VCC1P2 ANAIN1 20 ANAIN2 20 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX10 Power & GND C
DECA
B8 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX10 Power & GND C
DECA
B8 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX10 Power & GND C
DECA
B 8 25 Wednesday, March 11, 2015 L15 30ohm, 3A C164 10uMAX 10 GROUND
10M50DAF484C6GES U1H GND Y9 GND Y15 GND Y12 GND W21 GND V6 GND V2 GND V19 GND U13 GND U10 GND T8 GND T4 GND T16 GND T14 GND R21 GND R19 GND P6 GND P2 GND P17 GND N13 GND N11 GND M7 GND M19 GND M16 GND M10 GND L5 GND L21 GND L17 GND L13 DNU L3 GND K3 GND K12 GND K10 GND J6 GND J2 GND J19 GND J16 GND G8 GND G6 GND G21 GND G18 GND G15 GND F13 GND F10 GND E7 GND E2 GND D4 GND D20 GND D16 GND D11 GND B9 GND B6 GND B18 GND B13 GND AB22 GND AB1 GND AA4 GND AA18 GND A22 GND A1 NC2 F6 NC1 E5 REFGND H5 L21 30ohm, 3A C260 10u C41 10uMAX 10 POWER
10M50DAF484C6GES U1G VCC N12 VCC N10 VCC M13 VCC M12 VCC M11 VCC L12 VCC L11 VCC L10 VCC K13 VCC K11 VCCD_PLL1 T7 VCCD_PLL2 G16 VCCD_PLL3 G7 VCCD_PLL4 U16 VCCA1 R8 VCCA2 H15 VCCA3 H8 VCCA4 T15 VCCINT J7 VCCA_ADC H7 ADC_VREF H6 ANAIN1 G5 ANAIN2 J5 VCCIO1A L6 VCCIO1A K7 VCCIO1B M6 VCCIO1B L7 VCCIO2 R6 VCCIO2 P7 VCCIO2 N7 VCCIO2 N6 VCCIO3 U9 VCCIO3 U8 VCCIO3 T9 VCCIO3 T11 VCCIO3 T10 VCCIO4 U14 VCCIO4 U12 VCCIO4 U11 VCCIO4 T13 VCCIO4 T12 VCCIO5 T17 VCCIO5 R17 VCCIO5 R16 VCCIO5 P16 VCCIO5 N16 VCCIO6 N17 VCCIO6 M17 VCCIO6 L16 VCCIO6 K17 VCCIO6 K16 VCCIO6 J17 VCCIO6 H16 VCCIO7 G14 VCCIO7 G13 VCCIO7 G12 VCCIO7 F14 VCCIO7 F12 VCCIO8 G11 VCCIO8 G10 VCCIO8 F9 VCCIO8 F11 C242 0.1u C163 0.1u C230 10u REFGND2 DNI L16 30ohm, 3A C143 0.1u L26 30ohm, 3A L8 30ohm, 3A C181 0.1u L17 0.35ohm, 0.3A C219 0.1u5 5 4 4 3 3 2 2 1 1 D D C C B B A A VCC1P2_VCC VCC1P5_DDR3 VCC2P5_VCCA VCC1P2_VCCD VCC1P2 VCC1P8 VCC3P3 VCC2P5 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX10 Decoupling C
DECA
B 9 25 Wednesday, March 11, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX10 Decoupling C
DECA
B 9 25 Wednesday, March 11, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MAX10 Decoupling C
DECA
B 9 25 Wednesday, March 11, 2015 C121 4.7u C178 1u C157 22n C122 4.7u C208 10u C38 10u C159 1u C198 1u C139 10n C218 0.1u C179 22n C220 1u C204 1u C259 1u C138 10n C224 0.1u C203 0.1u C116 0.1u C161 1u C217 1u C205 10n C156 10n C199 1u C206 0.1u C140 0.1u C136 0.1u C120 0.1u C155 1u C226 0.1u C228 0.1u C154 1u C118 0.1u C160 10n C221 1u C90 10u C119 0.1u C200 1u C158 10n C162 10n C227 1u C225 0.1u C137 1u C135 1u C223 0.1u C202 1u C262 0.1u C114 0.1u C207 10n C115 10n C222 4.7u C229 0.1u C117 0.1u C201 1u C141 0.1u C209 10u C180 1u C197 1u C196 10n C261 10u5 4 3 2 1 D D C C B B A A
25.00MHz
19.2MHz
VCC3P3_CLKGEN VCC3P3_CLKGEN VCC3P3_CLKGEN VCC3P3 VCC1P5_DDR3 VCC3P3_CLKGEN VCC2P5 VCC2P5 VCC3P3_CLKGEN VCC3P3_CLKGEN VCC1P5_DDR3 VCC3P3_CLKGEN UB2_CLK_24 11 ADC_CLK_10 7 MAX10_CLK1_50 7 MAX10_CLK2_50 7 NET_CLK_25 18 DDR3_CLK_50 7 USB_CLK_19 19 UB2_CLK_50 11 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Oscillator, Clock Generator C
DECA
B10 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Oscillator, Clock Generator C
DECA
B10 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Oscillator, Clock Generator C
DECA
B 10 25 Wednesday, March 11, 2015 C42 0.1u Y1 501BAB25M0000CAFR VCC 4 OUT 3 GND 2 EN 1 VCCA VCCB DIR GND A B U33 SN74AVC1T45 3 4 6 2 5 1 C257 0.47u C255 0.47u U20 Si5350C-B03812-GM XA 1 XB 2 CLK0 13 CLK1 12 CLK2 9 CLK3 8 CLK4 19 CLK5 17 CLK6 16 CLK7 15 V DDO A 11 V DDO B 10 V DDO C 18 V DDO D 14 VD D 20 G ND_ E P 21 GND 3 GND 4 GND 5 CLKIN 6 GND 7 C256 0.47u L25 0.35ohm, 0.3A C63 0.1u C64 0.1u C258 0.1u C43 0.1u VCCA VCCB DIR GND A B U24 SN74AVC1T45 3 4 6 2 5 1 C269 0.47u C268 0.47u R105 24.95 5 4 4 3 3 2 2 1 1 D D C C B B A A
UB2 Clock
MAX10 CONFIG Status
CPLD ISP
Place Near CY7C68013A
JTAG Interface
Place near MAX V Place near MAX V
VCCIO = 2.5V VCCIO = 3.3V CONF_DONE_DISP FX2_PA1 FX2_PA2 FX2_PA3 FX2_PA4 FX2_PA5 FX2_PA6 FX2_PA7 CONF_DONE_DISP CONF_DONE CONF_DONE_MAX10 NSTATUS_MAX10 NCONFIG_MAX10 C_USB_MAX_TDI C_USB_MAX_TDO C_USB_MAX_TMS C_USB_MAX_TCK UB2_CLK_24 C_USB_MAX_TCK C_USB_MAX_TMS CONF_DONE NSTATUS NCONFIG CONF_DONE_MAX10 NSTATUS_MAX10 NCONFIG_MAX10 FX2_RESETn FX2_D_N FX2_D_P VCC5_USB FX2_WAKEUP JTAG_TX FX2_PD4 FX2_PD3 FX2_PD0 FX2_PD1 FX2_PD2 FX2_PD5 FX2_PD6 FX2_PD7 FX2_PB0 FX2_PB1 FX2_PB2 FX2_PB3 FX2_PB4 FX2_PB5 FX2_PB6 FX2_PB7 USB_CLK JTAG_RX FX2_FLAGC FX2_FLAGB FX2_WAKEUP FX2_SLWRn FX2_SLRDn FX2_FLAGA FX2_SCL FX2_SDA FX2_RESETn FX2_RESETn FX2_SDA FX2_PB7 USB_CLK C_USB_MAX_TDO FX2_FLAGB FX2_FLAGC FX2_PA1 FX2_PB4 C_USB_MAX_TDI FX2_PA2 FX2_PA4 FX2_FLAGA FX2_PB6 FX2_PB2 FX2_PA3 FX2_PA6 FX2_PA7 FX2_PB5 FX2_PB0 FX2_SCL FX2_PB3 FX2_PB1 FX2_SLWRn FX2_PD6 FX2_PD5 FX2_PD4 FX2_SLRDn FX2_PA5 FX2_PD7 CLK_12MHz JTAG_TX JTAG_RX UB2_CLK_24 UB2_CLK_50 JTAG_EN JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TCK FX2_PD3 FX2_PD2 FX2_PD0 FX2_PD1 VCC3P3 VCC3P3 VCC3P3 VCC3P3 VCC3P3 VCC3P3 VCC1P2 VCC2P5 VCC3P3 VCC1P8 VCC3P3 VCC3P3 VCC2P5 VCC1P8 VCC1P2 VCC5_USB VCC2P5 JTAG_TCK 7 JTAG_TDI 7 JTAG_TMS 7 JTAG_TDO 7 UB2_CLK_24 10 NSTATUS 7 CONF_DONE 7 NCONFIG 7 JTAG_EN 7 UB2_CLK_50 10 CLK_12MHz 16 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
USB Blaster II C
DECA
B 11 25 Friday, March 13, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
USB Blaster II C
DECA
B 11 25 Friday, March 13, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
USB Blaster II C
DECA
B 11 25 Friday, March 13, 2015 C251 0.1u 10V U39 TLV809K33DBVR GND 1 RESET 2 VCC 3 R122 10K C243 0.1u 10V Q9 AO3400 1 2 3 R121 0 Q8 AO3400 1 2 3 R119 0 C254 0.1u 10V R242 100K R206 10K R245 10K C49 0.1u 10V C271 0.1u 10V R110 0 D5 LEDG 2 1 R248 1K TP1DNI R109 0 C246 0.1u 10V C245 0.1u 10V C250 0.1u 10VBank 2
5M570ZM100
5M570ZM100 U21-2 IOB2_17 B11 IOB2_16 C10 IOB2_15 C11 IOB2_14 D10 IOB2_13 D11 IOB2_12 D9 IOB2_11 E10 IOB2_10 E11 IOB2/CLK2 F10 IOB2_9 F11 IOB2_8 F9 IOB2_7 G10 IOB2/CLK3 G11 IOB2_5 H10 IOB2_37 A1 IOB2_20 A10 IOB2_19 A11 IOB2_35 A2 IOB2_33 A3 IOB2_30 A5 IOB2_29 A6 IOB2_26 A7 IOB2_24 A8 IOB2_22 A9 IOB2_18 B10 IOB2_36 B2 IOB2_34 B3 IOB2_32 B4 IOB2_31 B5 IOB2_28 B6 IOB2_25 B7 IOB2_23 B8 IOB2_21 B9 IOB2_27 C6 IOB2_6 H11 IOB2_4 H9 IOB2_2 J10 IOB2_3 J11 IOB2_1 K11 R239 2K TP6DNI R238 2K D7 LEDG 2 1 C270 0.1u 10V U19 CY7C68013A_VFBGA RDY0 A1 RDY1 B1 XTALIN C1 AVCC D1 DMINUS E1 AGND F1 VCC G1 GND H1 PD7 A2 CLKOUT B2 XTALOUT C2 AVCC D2 DPLUS E2 AGND F2 IFCLK G2 RESERVED H2 PD5 A3 PD4 B3 PD6 C3 SCL F3 SDA G3 PB0 H3 GND A4 GND B4 GND C4 PB1 F4 PB3 G4 PB2 H4 VCC A5 VCC B5 PB6 F5 PB5 G5 PB4 H5 PD3 A6 PD2 B6 PA7 C6 PA4 F6 PA1 G6 PB7 H6 PD1 A7 WAKEUP B7 PA6 C7 GND D7 VCC E7 PA3 F7 CTL1 G7 CTL0 H7 PD0 A8 RESET B8 PA5 C8 GND D8 VCC E8 PA2 F8 PA0 G8 CTL2 H8 VCC C5 C253 0.1u 10V C272 0.1u 10V5M570ZM100
Bank 1
5M570ZM100 U21-1 TMS J1 TDI J2 IOB1_1 B1 IOB1_3 C1 IOB1_2 C2 IOB1_6 D1 IOB1_5 D2 IOB1_4 D3 IOB1/CLK1 E1 IOB1_7 F1 IOB1/CLK0 F2 IOB1_10 F3 IOB1_8 G1 IOB1_9 G2 IOB1_11 H1 IOB1_13 H2 IOB1_12 H3 IOB1_14 L1 TCK K1 TDO K2 IOB1/DEV_CLRN K8 IOB1/DEV_OE L8 IOB1_24 J6 IOB1_30 K10 IOB1_16 K3 IOB1_18 K4 IOB1_20 K5 IOB1_23 K6 IOB1_26 K7 IOB1_28 K9 IOB1_29 L10 IOB1_31 L11 IOB1_15 L2 IOB1_17 L3 IOB1_19 L4 IOB1_21 L5 IOB1_22 L6 IOB1_25 L7 IOB1_27 L9 TP5DNI D8 LEDG 2 1 R228 120 Q4 UTC8050 DNI 1 2 3 R113 10K J10 Mini-USB-B VBUS 1 D- 2 D+ 3 ID 4 GND 5 SHIELD1 6 SHIELD2 7 C244 0.1u 10V R82 10 Q1 AO3400 1 2 3 R120 0 C252 0.1u 10V C267 0.1u 10V C264 0.1u 10V C263 0.1u 10V C266 0.1u 10V C249 0.1u 10V R118 0 R188 10K R108 0 R234 120 R102 1K DNI R247 0 R117 10 DNI R93 1M R246 20K TP4DNI TP3DNI U36 TPD2EUSB30DRTR D- 2 D+ 1 GND 3Power
5M570ZM100
5M570ZM100 U21-3 VCCIO1 E3 VCCIO1 J4 GND A4 GND E2 GND E4 GND G4 GND H5 VCCINT G3 VCCIO1 J8 GND C5 GND D5 GND D7 GND E8 GND G8 GND H7 GND J5 VCCINT C7 VCCINT E9 VCCINT J7 VCCIO2 C4 VCCIO2 C8 VCCIO2 G9 R114 10K R216 120 C265 0.1u 10V C50 4.7n 50V TP2DNI R101 1K C55 0.1u 10V R197 10K5 4 3 2 1 D D C C B B A A
Header GPIO
P8
P9
Header Analog Input
GPIO1_D21 is connected to MAX 10 PLL output pin
AIN3 AIN5 AIN6 AIN1 AIN2 AIN0 AIN4 GPIO0_D0 GPIO0_D1 GPIO0_D43 GPIO0_D4 GPIO0_D2 GPIO0_D6 GPIO0_D10 GPIO0_D8 GPIO0_D14 GPIO0_D12 GPIO0_D16 GPIO0_D20 GPIO0_D18 GPIO0_D22 GPIO0_D26 GPIO0_D24 GPIO0_D30 GPIO0_D28 GPIO0_D32 GPIO0_D36 GPIO0_D34 GPIO0_D38 GPIO0_D42 GPIO0_D40 GPIO0_D3 GPIO0_D13 GPIO0_D11 GPIO0_D9 GPIO0_D7 GPIO0_D5 GPIO0_D23 GPIO0_D21 GPIO0_D19 GPIO0_D17 GPIO0_D15 GPIO0_D25 GPIO0_D35 GPIO0_D33 GPIO0_D31 GPIO0_D29 GPIO0_D27 GPIO0_D41 GPIO0_D39 GPIO0_D37 PWR_BUT SYS_RESET_n GPIO1_D0 GPIO1_D2 GPIO1_D8 GPIO1_D10 GPIO1_D4 GPIO1_D6 GPIO1_D12 GPIO1_D14 GPIO1_D20 GPIO1_D16 GPIO1_D18 GPIO1_D7 GPIO1_D5 GPIO1_D11 GPIO1_D13 GPIO1_D19 GPIO1_D17 GPIO1_D3 GPIO1_D1 GPIO1_D9 GPIO1_D15 GPIO1_D21 GPIO1_D22 VCC3P3 VCC5 VCC1P8_VCCADC VCC3P3 VCC5 VCC1P8 VCC3P3 GPIO0_D[43..0] 4,7 GPIO1_D[22..0] 4,7 AIN[6..0] 3 SYS_RESET_n 4 PWR_BUT 4 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Expansion Headers - BBB Headers C
DECA
B12 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Expansion Headers - BBB Headers C
DECA
B12 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Expansion Headers - BBB Headers C
DECA
B 12 25 Wednesday, March 11, 2015 R20 10K C1 0.1u 10V L4 30ohm, 3A P8 HEADER 23x2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 C4 10u 6.3V P9 HEADER 23x2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 465 5 4 4 3 3 2 2 1 1 D D C C B B A A
place close to DDR3 chip
Note: place a pull down resistor on the FLASH_DCLK wire at the Master
DDR3_BA0 DDR3_BA1 DDR3_BA2 DDR3_CK_n DDR3_CK_p DDR3_RESET_n DDR3_CKE DDR3_DQS_p0 DDR3_DQS_n0 DDR3_DQS_p1 DDR3_DQS_n1 DDR3_RZQ DDR3_DM1 DDR3_DM0 DDR3_A0 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A5 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A9 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A13 DDR3_A14 DDR3_DQ15 DDR3_DQ14 DDR3_DQ13 DDR3_DQ12 DDR3_DQ11 DDR3_DQ10 DDR3_DQ9 DDR3_DQ8 DDR3_DQ7 DDR3_DQ6 DDR3_DQ5 DDR3_DQ4 DDR3_DQ3 DDR3_DQ2 DDR3_DQ1 DDR3_DQ0 DDR3_VREF FLASH_RESET_n FLASH_DATA0 FLASH_DATA2 FLASH_DATA1 FLASH_DATA3 FLASH_DCLK FLASH_NCSO FLASH_DCLK FLASH_RESET_n FLASH_NCSO FLASH_DATA0 FLASH_DATA1 FLASH_DATA2 FLASH_DATA3 VCC1P5_DDR3 DDR3_VREF VCC1P5_DDR3 VCC1P5_DDR3 VCC1P5_DDR3 DDR3_VREF VCC1P5_DDR3 GND VCC3P3 GND VCC3P3 GND VCC3P3 DDR3_CK_p 5 DDR3_CK_n 5 DDR3_CKE 5 DDR3_CS_n 5 DDR3_RESET_n 5 DDR3_WE_n 5 DDR3_RAS_n 5 DDR3_CAS_n 5 DDR3_ODT 5 DDR3_BA[2..0] 5 DDR3_DQS_p[1..0] 5,7 DDR3_DQ[ 15..0] 5 DDR3_A[14..0] 5 DDR3_DQS_n[1..0] 5,7 DDR3_DM[1..0] 5 FLASH_DCLK 4 FLASH_NCSO 4 FLASH_DATA[3..0] 4 FLASH_RESET_n 4 Title
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Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
DDR3 SDRAM, QSPI Flash C
DECA
B13 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
DDR3 SDRAM, QSPI Flash C
DECA
B13 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
DDR3 SDRAM, QSPI Flash C
DECA
B 13 25 Wednesday, March 11, 2015 U12 MT41K256M16HA-125 IT:E VSS A9 VDD B2 NC3 L1 UDM D3 VSS B3 VDD D9 VSS E1 VSSQ B1 DQ0 E3 LDM E7 VSSQ B9 VDDQ A1 VDDQ A8 DQ2 F2 LDQS F3 DQ3 F8 DQ1 F7 VSSQ D8 VSSQ D1 DQ6 G2 LDQSn G3 VDD G7 VSS G8 VSSQ E2 VREFDQ H1 VDDQ C1 DQ4 H3 DQ7 H7 DQ5 H8 VDDQ C9 VSS J8 RAS J3 CLK J7 VSS J2 ODT K1 VDD K8 CAS K3 CLK_n K7 CKE K9 CS L2 WE L3 A10/AP L7 ZQ L8 VSS M1 BA0 M2 BA2 M3 NC4 L9 VREFCA M8 VSS M9 A3 N2 A0 N3 A12/BC_n N7 BA1 N8 VSS P1 A5 P2 A2 P3 A1 P7 A4 P8 VSS P9 A7 R2 A9 R3 A11 R7 A6 R8 VSS T1 A13 T3 A8 T8 VSS T9 A14 T7 VDDQ D2 VDDQ E9 VDDQ F1 VDDQ H2 VDDQ H9 VDD K2 VDD N1 VDD N9 VDD R1 VDD R9 VSSQ E8 VSSQ F9 VSSQ G1 VSSQ G9 NC1 J1 NC2 J9 DQ8 D7 DQ9 C3 DQ10 C8 DQ11 C2 DQ12 A7 DQ13 A2 DQ14 B8 DQ15 A3 UDQS C7 UDQSn B7 RESET T2 NC5 M7 R235 DNI R91 DNI R107 DNI C239 0.1u DNI R215 100 R112 DNI U37 N25Q512A83GSF40F HOLD_n/DQ3 1 VCC 2 DNU_1 3 DNU_2 4 DNU_3 5 DNU_4 6 S_n 7 DQ1 8 W_n/Vpp/DQ2 9 VSS 10 DNU_5 11 DNU_6 12 DNU_7 13 DNU_8 14 DQ0 15 C 16 C60 0.1u 10V C194 2.2n R90 2K C132 0.1u C216 2.2n C214 10n C193 0.47u C133 2.2n C151 0.1u R227 1K DNI C153 10n R106 DNI C215 0.1u R213 4.7K C176 4.7n C240 0.47u R111 2k R92 10K C241 0.47u C134 10n C152 3.3n C177 0.1u C175 2.2n C150 0.1u C174 2.2n C173 2.2n R214 240 R81 1K DNI5 4 3 2 1 D D C C B B A A
Micro SD Card
SD_SEL = 0, VCCIO_SD = 3.3V
SD_SEL = 1, VCCIO_SD = 1.8V
ex_SD_CMD ex_SD_CLK SD_DAT1 SD_DAT0 SD_DAT3 SD_DAT2 SD_CMD SD_CLK SD_FB_CLK SD_D0_DIR SD_D123_DIR SD_CMD_DIR ex_SD_DAT1 ex_SD_DAT0 ex_SD_DAT3 ex_SD_DAT2 ex_SD_CMD ex_SD_DAT1 ex_SD_DAT2 ex_SD_DAT3 ex_SD_DAT0 ex_SD_CMD ex_SD_CLK ex_SD_DAT0 ex_SD_DAT1 ex_SD_DAT2 ex_SD_DAT3 SD_SEL VCC3P3 VCC3P3_SD VCCIO_SD VCC3P3_SD VCCIO_SD VCC1P5_DDR3 VCC3P3 VCC2P8 VCC1P8 VCC1P8 VCCIO_SD SD_DAT[3..0] 5 SD_CMD 5 SD_CLK 5 SD_D0_DIR 5 SD_D123_DIR 5 SD_CMD_DIR 5 SD_FB_CLK 5 SD_SEL 4 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SD Card C
DECA
B 14 25 Wednesday, March 11, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SD Card C
DECA
B 14 25 Wednesday, March 11, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SD Card C
DECA
B 14 25 Wednesday, March 11, 2015 RN1 10K 1 2 3 4 5 6 7 8 VCCIO_SD R129 10K C66 0.1u 10V C61 0.1u 10V 1 2 3 11 4 5 6 7 8 10 9 12 13 14 15 16 J11 S O CK E T -S D_ CA RD_ 3 DAT3 CMD VCC CLK VSS DAT0 DAT1 DAT2 CD VSS VSS CD2 VSS VSS VSS VSS R130 1K U25 TPS22912CYZVR VIN A2 ON B2 VOUT A1 GND B1 R250 1K DNI R126 0 U22 SN74AVCA406L VCCA A5 DATA0A B2 DATA1A A2 DATA2A B4 DATA3A A4 CMDA B1 CLKA A3 CLK-f A1 GND B3 GND C3 DATA0B D2 DATA1B D1 DATA2B C4 DATA3B D4 CMDB C2 CLKB D3 VCCB D5 DATA0_dir C5 DATA123_dir C1 CMD_dir B5 C65 10u Q10 UTC8050 DNI 1 2 3 L9 30ohm, 3A R127 0 R128 0 DNI U26 TPS22910AYZVR VIN A2 ON B2 VOUT A1 GND B1 C68 10u C67 0.1u 10V R252 1K DNI5 5 4 4 3 3 2 2 1 1 D D C C B B A A
MIPI Interface
MIPI Control Interface
MIPI_MCLK_T AVDD AFVCC MIPI_MD_n2 MIPI_MD_p2 MIPI_RESET_n_T MIPI_MD_n0 MIPI_MD_p0 MIPI_MD_n3 MIPI_MD_p3 MIPI_MD_n1 MIPI_MD_p1 MIPI_I2C_SCL_T MIPI_I2C_SDA_T MIPI_CORE_EN_T MIPI_MC_n MIPI_MC_p DOVDD AVDD12 MIPI_WP_T MIPI_LP_MD_p1 MIPI_LP_MD_n1 MIPI_MD_n1 MIPI_MD_p1 MIPI_LP_MD_p2 MIPI_LP_MD_n2 MIPI_MD_n2 MIPI_MD_p2 MIPI_LP_MD_n3 MIPI_LP_MD_p3 MIPI_MD_p3 MIPI_MD_n3 MIPI_MC_p MIPI_MC_n MIPI_I2C_SDA MIPI_I2C_SCL MIPI_MD_n0 MIPI_MD_p0 MIPI_LP_MD_n0 MIPI_LP_MD_p0 MIPI_LP_MC_p MIPI_LP_MC_n MIPI_RESET_n MIPI_MCLK MIPI_WP MIPI_CORE_EN MIPI_I2C_SCL MIPI_I2C_SDA MIPI_I2C_SDA_T MIPI_WP_T MIPI_RESET_n_T MIPI_MCLK_T MIPI_CORE_EN_T MIPI_I2C_SCL_T GND GND VCC1P2 VCC1P8 VCC2P8 GND VCC2P5 VCC2P5 VCC2P5 VCC2P5 VCC2P5 VCC2P5 VCC1P8 VCC1P8 VCC1P8 VCC1P8 VCC1P8 DOVDD VCC2P5 DOVDD VCC2P8 MIPI_I2C_SDA 3 MIPI_I2C_SCL 3 MIPI_MD_p[3..0] 3 MIPI_MD_n[3..0] 3 MIPI_MC_n 7 MIPI_MC_p 7 MIPI_MCLK 3 MIPI_CORE_EN 3 MIPI_WP 3 MIPI_RESET_n 3 MIPI_LP_MC_p 7 MIPI_LP_MD_p[3..0] 6 MIPI_LP_MD_n[3..0] 6 MIPI_LP_MC_n 7 Title
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Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MIPI Interface C
DECA
B 15 25 Thursday, March 19, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MIPI Interface C
DECA
B 15 25 Thursday, March 19, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
MIPI Interface C
DECA
B 15 25 Thursday, March 19, 2015 R153 150 R132 150 C70 0.1u 10V R9 0 C73 10u 6.3V R10 49.9 D1 SD107WS-TP 2 1 R3 49.9 R33 49.9 R136 0 R2 49.9 R12 49.9 R11 49.9 J4 HEADER 15X2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 R131 150 R163 0 DNI R137 150 R4 0 R141 150 R8 0 L2 30ohm, 3A R35 0 C69 10u 6.3V R13 0 C72 0.1u 10V R23 0 R24 49.9 R148 49.9 C71 33p DNI 50V D12 SD107WS-TP 2 1 R6 49.9 R139 0 R36 49.9 D2 SD107WS-TP 2 1 R5 49.9 D10 SD107WS-TP 2 1 R7 0 L1 30ohm, 3A R152 49.9 R25 560 R15 49.9 R134 49.9 D11 SD107WS-TP 2 1 R158 150 R140 560 R150 49.9 R149 150 R151 2K R133 150 R26 2K DNI R135 0 DNI R159 150 R1 0 R138 150 Q7 AO3400 1 2 3 R14 0 R34 05 4 3 2 1 D D C C B B A A
HDMI TX
Default :
I2C Address 0x72/0x73
HDMI TX
HDMI Audio Interface
From MAX
I2C Interface
Note:
Place Capacitor near ADV7513 DVDD pins
Note:
Place Capacitor near ADV7513 AVDD pins
Note:
Place Capacitor near ADV7513 PVDD and BGVDD pin
Note:
Place Capacitor near ADV7513 DVDD_3V
TMDS_TX_p1 TMDS_TX_n1 TMDS_TX_p2 TMDS_TX_n2 TMDS_TX_p0 TMDS_TX_n0 TMDS_TX_p0 TMDS_TX_n0 TMDS_TX_p1 TMDS_TX_n1 TMDS_TX_n1 TMDS_TX_p1 TMDS_TX_p2 TMDS_TX_n2 TMDS_TX_n2 TMDS_TX_p2 TMDS_TXC_p TMDS_TXC_n TMDS_TXC_n TMDS_TXC_p HDMI_TX_D0 HDMI_TX_D1 HDMI_TX_D2 HDMI_TX_D3 HDMI_TX_D4 HDMI_TX_D5 HDMI_TX_D6 HDMI_TX_D7 HDMI_TX_D8 HDMI_TX_D16 HDMI_TX_CLK_T HDMI_TX_DE HDMI_TX_VS HDMI_TX_HS HDMI_I2C_SDA_T HDMI_I2C_SCL DDCSCL DDCSDA CEC HDMI_TX_D9 HDMI_HPD HDMI_TX_D10 HDMI_TX_D11 HDMI_TX_D12 HDMI_TX_D13 HDMI_TX_D14 HDMI_TX_D15 HDMI_TX_D17 HDMI_TX_D18 HDMI_TX_D19 HDMI_TX_D20 HDMI_TX_D21 HDMI_TX_D22 HDMI_TX_D23 TMDS_TXC_p TMDS_TXC_n TMDS_TX_p0 TMDS_TX_n0 DDCSDA DDCSCL CEC_IO HDMI_HPD CEC_CLK CEC_CLK HDMI_I2C_SCL HDMI_SPDIF HDMI_MCLK HDMI_I2S0 HDMI_I2S1 HDMI_I2S2 HDMI_I2S3 HDMI_SCLK HDMI_LRCLK CEC DDCSCL DDCSDA HDMI_HPD HDMI_TX_INT CLK_12MHz HDMI_TX_CLK_T HDMI_I2C_SDA HDMI_I2C_SDA_T VCC1P8 VCC1P8_DVDD VCC1P8 VCC1P8_AVDD VCC1P8 VCC1P8_PVDD VCC3P3 VCC1P8_DVDD VCC3P3_DVDD VCC1P8_PVDD VCC1P8_AVDD VCC3P3_DVDD VCC5 VCC3P3_DVDD VCC1P8_AVDD VCC1P8 GND_EXT VCC5 VCC1P8 VCC3P3 VCC1P2 VCC3P3 VCC1P2 VCC3P3_DVDD VCC1P8 VCC1P8 HDMI_TX_HS 6 HDMI_TX_VS 6 HDMI_TX_DE 6 HDMI_TX_D[23..0] 6 HDMI_TX_INT 6 CLK_12MHz 11 HDMI_I2C_SDA 6 HDMI_I2C_SCL 6 HDMI_I2S[3:0] 6 HDMI_MCLK 6 HDMI_LRCLK 6 HDMI_SCLK 6 HDMI_TX_CLK 6,7 Title
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Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
HDMI TX C
DECA
B 16 25 Thursday, March 19, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
HDMI TX C
DECA
B 16 25 Thursday, March 19, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
HDMI TX C
DECA
B 16 25 Thursday, March 19, 2015 C101 0.1u 10V D3 RClamp0514P 1 8 4 6 3 9 2 5 7 10 R52 2K C77 0.1u 10V R176 887 L3 10uH 74479777310 R165 0 DNI C19 0.1u R157 0 R18 4.99K DNI C6 10u 6.3V L10 10uH 74479777310 C15 0.1u 10V R161 49.9 DNI R142 22 DNI R30 4.99K C98 10u 6.3V D13 DFLS1150-7 DNI L12 10uH 74479777310 C32 0.1u 25V R156 2K D4 RClamp0514P 1 8 4 6 3 9 2 5 7 10 R59 10K C100 0.1u 10V C112 0.1u 10V U31 TPD4E001_0 1 3 2 4 6 5 C76 0.1u 10V SHELL GND CEC D2- D1- CK-D1+ D0+ SDA CK+ GND GND GND D0-D2+ +5V GND HPD SCL J6 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 R166 2K DNI R53 2K Q6 AO3400 DNI 1 2 3 R19 4.99K C9 0.1u C74 10u 6.3V VCCA VCCB DIR GND A B U4 SN74AVC1T45 DNI 3 4 6 2 5 1 L11 10uH 74479777310 C99 0.1u 10V R62 1M C111 10u 6.3V C83 0.1u 10V U5 ADV7513BSWZ D0 62 D1 61 D2 60 D3 59 D4 58 D5 57 D6 56 D7 55 D8 54 D9 52 D10 50 D11 49 D12 48 D13 47 D14 46 D15 45 D16 44 D17 43 D18 42 D19 41 D20 40 D21 39 D22 38 D23 37 CLK 53 DE 63 HSYNC 64 VSYNC 2 R_EXT 14 HPD 16 SPDIF 3 MCLK 4 I2S0 5 I2S1 6 I2S2 7 I2S3 8 SCLK 9 LRCLK 10 PD 22 TXC+ 18 TXC- 17 TX0+ 21 TX0- 20 TX1+ 24 TX1- 23 TX2+ 27 TX2- 26 INT 28 SDA 36 SCL 35 DDCSDA 34 DDCSCL 33 CEC 30 CEC_CLK 32 DVDD_3V 29 DVDD1 1 DVDD2 11 DVDD3 31 DVDD4 51 PVDD 12 BGVDD 13 AVDD1 15 AVDD2 19 AVDD3 25 EPAD_GND 65 R154 27K DNI R160 2K R421 0 R155 0 C113 0.1u 10V C88 0.1u 10V R162 05 5 4 4 3 3 2 2 1 1 D D C C B B A A
LINE IN
LINE OUT
Audio CODEC Interface
Audio Control Interface
Default :
I2C Address 0x30/31
LINE-IN for ADC
Audio LINE-IN to MAX10 ADC
LINE_IN_L LINE_IN_R AUDIO_GPIO_MFP5 AUDIO_SCLK_MFP3 AUDIO_MISO_MFP4 AUDIO_SCL_SS_n AUDIO_SDA_MOSI AUDIO_DIN_MFP1 AUDIO_BCLK AUDIO_DOUT_MFP2 AUDIO_RESET_n AUDIO_MCLK AUDIO_WCLK AUDIO_SPI_SELECT LINE_OUT_R LINE_OUT_L LINE_IN_L_AUD LINE_IN_R_AUD AUDIO_RESET_n AUDIO_SPI_SELECT AUDIO_SDA_MOSI AUDIO_SCL_SS_n LINE_OUT_L LINE_OUT_R LINE_AC_L LINE_IN_R_AUD LINE_IN_L LINE_AC_L LINE_AC_L LINE_IN_L_AUD LINE_IN_L_ADC VCC_AUD VCC_AUD_IO VCC_AUD VCC_AUD VCC3P3 VCC1P5_DDR3 VCC_AUD_IO VCC_AUD_IO VCC_AUD_IO VCC2P5_VCCAADC VCC2P5_VCCAADC VCC5_ADC VCC5_ADC VCC5_ADC VCC2P5_VCCAADC AUDIO_WCLK 5 AUDIO_SCLK_MFP3 5 AUDIO_MISO_MFP4 5 AUDIO_SPI_SELECT 5 AUDIO_GPIO_MFP5 5 AUDIO_RESET_n 5 AUDIO_MCLK 5 AUDIO_DOUT_MFP2 5 AUDIO_DIN_MFP1 5 AUDIO_SDA_MOSI 5 AUDIO_SCL_SS_n 5 AUDIO_BCLK 5 LINE_IN_L_ADC 3 Title
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Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Audio CODEC C
DECA
B 17 25 Friday, March 13, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Audio CODEC C
DECA
B 17 25 Friday, March 13, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Audio CODEC C
DECA
B 17 25 Friday, March 13, 2015 R58 2K C128 0.1u 10V DNI J2 PHONE JACK B L 1 R 2 GN D 3 NCR 4 NCL 5 R187 100 C107 1u 10V C210 10u 6.3V R57 2K R191 47K DNI J1 PHONE JACK G L 1 R 2 GN D 3 NCR 4 NCL 5 C183 0.1u 10V L19 30ohm, 3A R66 4.7K R55 0 R193 47K DNI R190 1K C23 0.1u 10V R67 10K C129 1u 10VDNI C108 47n 25V + -U8A OPA1612AIDR 3 1 8 4 2 C97 1u 10V R253 0 R174 47K DNI + -U8B OPA1612AIDR 5 7 8 4 6 R255 10 C167 0.1u 10V C109 1u 10V U9 TLV320AIC3254_0 MCLK 1 BCLK 2 WCLK 3 DIN/MFP1 4 DOUT/MFP2 5 IO V D D 6 IOVSS 7 SCLK/MFP3 8 SCL/SS 9 SDA/MOSI 10 MISO/MFP4 11 SPI_SELECT 12 AVSS 17 REF 18 MICBIAS 19 IN3_L 20 IN3_R 21 LOL 22 LOR 23 AVD D 24 HPL 25 IN1_L 13 IN1_R 14 IN2_L 15 IN2_R 16 GPIO/MFP5 32 RESET 31 LDO_SELECT 30 DV DD 29 D VSS 28 HPR 27 LD OI N 26 PPAD 33 C184 22u 6.3V R192 47K DNI R54 0 DNI R186 100 C146 10u 6.3V C168 22u 6.3V R182 47K DNI R56 10K DNI C182 10u 6.3V C166 0.1u 10V R183 0 C106 47n 25V R185 47K L7 30ohm, 3A C96 1u 10V C145 0.1u 10V R184 47K R175 47K DNI C280 1p C130 1u 10V5 4 3 2 1
D D
C C
B B
A A
Analog interface , so using 3.3v
NET_TX_CLK NET_TXD0 NET_TXD1 NET_TXD2 NET_TXD3 NET_RXD0 NET_RXD1 NET_RXD2 NET_RXD3 NET_TX_EN NET_RX_CLK NET_RX_ER NET_RX_DV NET_COL NET_CRS NET_RESET_n NET_MDIO NET_MDC ETD_P ETD_N ERD_P ERD_N NET_CLK_25 LED_ACTIVE NET_PCF_EN LED_LINK SPEED LED_ACTIVE NET_VCC3P3 GND VCC3P3 NET_VCC3P3 GND GND VCC2P5 NET_VCC2P5 GND NET_VCC2P5 NET_VCC2P5 GND GND NET_VCC3P3 NET_VCC3P3 GND GND NET_VCC3P3 GND GND NET_VCC3P3 GND NET_VCC3P3 NET_VCC3P3 GND_S NET_RX_CLK 7 NET_TX_EN 7 NET_RESET_n 7 NET_MDIO 3 NET_TXD[3..0] 3 NET_RXD[3..0] 3 NET_RX_ER 3 NET_RX_DV 3 NET_MDC 3 NET_COL 3 NET_CLK_25 10 NET_TX_CLK 7 NET_CRS 3 NET_PCF_EN 7 Title
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Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Ethernet C
DECA
B 18 25 Wednesday, March 11, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Ethernet C
DECA
B 18 25 Wednesday, March 11, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Ethernet C
DECA
B 18 25 Wednesday, March 11, 2015 C33 0.1u C212 0.1u C186 0.1u R65 49.9 R261 0 DNI R231 2.2K R224 4.87K R74 2.2K DNI L23 BEAD R236 1.5K L24 BEAD R201 110 R207 2.2K R80 2.2K U14 DP83620_3 TX_CLK 1 TXD_0 3 TXD_1 4 TXD_2 5 TXD_3 6 TX_EN 2 MDIO 30 MDC 31 COL 42 CRS/CRS_DV 40 RX_DV 39 RX_ER 41 RXD_3 43 RXD_2 44 RXD_1 45 RXD_0 46 RX_CLK 38 PCF_EN 22 IO_VDD 32 IO_VDD 48 TD+ 17 TD- 16 RD+ 14 RD- 13 X1 34 X2 33 RESERVED2 25 LED_ACT 26 LED_SPEED/FX_SD 27 LED_LINK 28 CLK_OUT 24 RESERVED1 23 ANAVSS 18 RESERVED4 37 CLK_OUT_EN 21 VREF 20 IO_CORE_VSS 35 IO_VSS 47 CD_VSS 15 ANA33VDD 19 RESERVED3 36 RESET_N 29 PWR_DOWN/INTN 7 TCK 8 TDO 9 TMS 10 TRST# 11 TDI 12 DAP 49 R202 2.2K C46 0.1u R70 49.9 R64 49.9 R237 2.2K R225 0 R210 0 C234 0.1u R233 110 C235 10u R260 0 J7 480749001 TD+ 3 TD-4 CTT 5 RD+ 7 RD-8 CTR 6 LA 12 LC 11 RA 1 RC 2 CHS_GND 9 CHS_GND 10 SHIELD2 14 SHIELD1 13 R241 2.2K R71 49.9 C185 0.1u C211 0.1u C233 10u R45 0 R232 2.2K5 5 4 4 3 3 2 2 1 1 D D C C B B A A CAD Notes:
Put the TPD4S012 close to each USB connector. CAD Notes:
Put the TUSB1210 close to FPGA.
Default Connection: ULPI with clock output mode
USB_DP USB_DM USB_DATA0 USB_DATA1 USB_DATA2 USB_DATA3 USB_DATA4 USB_DATA5 USB_DATA6 USB_DATA7 TUSB1210_CLK_R GND GND VCC5 USB_VCC5 VCC1P2 GND USB_VCC5 GND GND GND VCC1P8_USB USB_REG1P5 USB_REG3P3 GND USB_REG1P5 GND USB_REG3P3 VBAT VCC1P8 VCC1P8_USB GND VCC3P3 VBAT GND VCC1P8_USB GND GND VCC1P8_USB VCC1P2 VCC1P8_USB VCC1P2 GND GND USB_FAULT_n 6 USB_DATA[7..0] 6 USB_STP 6 USB_NXT 6 USB_DIR 6 USB_CS 6 USB_RESET_n 6 USB_CLK_19 10 USB_CLOCK 7 USB_CLKOUT_NOPLL 6 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
USB PHY C
DECA
B 19 25 Thursday, March 19, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
USB PHY C
DECA
B 19 25 Thursday, March 19, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
USB PHY C
DECA
B 19 25 Thursday, March 19, 2015 CPEN1 DNI R69 22 R63 1M C187 4.7u R60 0 U17 TPS2553DRVR IN 6 GND 5 EN 4 FAULT_n 3 ILIM 2 OUT 1 EP_GND 7 C236 4.7u U13 TUSB1210 REFCLK 1 NXT 2 DATA0 3 DATA1 4 DATA2 5 DATA3 6 DATA4 7 NC1 8 DATA5 9 DATA6 10 CS 11 V DD1 5 12 DATA7 13 CFG 14 NC2 15 NC3 16 CPEN 17 DP 18 DM 19 V DD3 3 20 VBAT 21 VBUS 22 ID 23 NC4 24 NC5 25 CLOCK 26 RESETB 27 V DD1 8 28 STP 29 V DD1 8 30 DIR 31 V DDIO 32 GN D 33 C110 0.1u C170 0.1u VCCA VCCB DIR GND A B U10 SN74AVC1T45 3 4 6 2 5 1 C281 1n C191 0.1u R212 10K DNI L20 60ohm 3A R73 0 U34 TPD4S012 D+ 1 D-2 ID 3 GN D 4 NC 5 VBU S 6 R68 0 R209 0 C282 0.1u R205 0 DNI R83 820 C237 0.1u C190 0.1u R211 0 C131 0.1u C188 0.1u C172 4.7u R79 10k R196 0 R226 20K C189 4.7u R208 0 DNI C238 0.1u C169 0.1u C192 4.7u C213 0.1u C171 0.1u R61 2K DNI VBUS D-D+ ID GND Mini-USB AB J8 Jack-Mini-USB-AB_3 1 2 3 5 7 6 45 4 3 2 1 D D C C B B A A Notes:
the input voltage Vin range (-6.25V --- 8.75V)
Notes:
the input voltage Vin range (-6.25V --- 8.75V)
Notes:
the output voltage Vo range (0.0V --- 3.0V)
Notes:
the output voltage Vo range (0.0V --- 3.0V)
CAD Notes: Put the 1pF caps close to MAX10 pin. CAD Notes: Put the 1pF caps close to MAX10 pin.
Notes:
Amplifier output voltage Vo=(6.25+Vin)/5
Notes:
Amplifier output voltage Vo=(6.25+Vin)/5
ANAIN2_SMA ANAIN2_VOUT2 ANAIN1_SMA ANAIN1_VOUT2 VCC3P3 VCC2P5_VREF VCC5_ADC VCC5 VCC5_ADC VCC5_ADC VCC2P5_VREF VCC2P5_VREF ANAIN2 8 ANAIN1 8 Title
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Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SMA Connectors & Difference Amplifier C
DECA
B
20 25
Monday, March 16, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SMA Connectors & Difference Amplifier C
DECA
B
20 25
Monday, March 16, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SMA Connectors & Difference Amplifier C
DECA
B 20 25 Monday, March 16, 2015 C165 0.47u C86 0.1u C127 0.1u L13 60ohm 3A C104 0.1u C27 1p C95 1u R189 1 U3 INA159AIDGKR REF1 1 IN-2 IN+ 3 V-4 SENSE 5 OUT 6 V+ 7 REF2 8 C103 10u C144 10u C87 10u U32 REF3125 VIN 1 VOUT 2 GND 3 U7 INA159AIDGKR REF1 1 IN-2 IN+ 3 V-4 SENSE 5 OUT 6 V+ 7 REF2 8 J3 Analog IN J5 Analog IN C93 1u R46 10 C94 10u C28 1p R44 10 C142 1u C105 10u5 5 4 4 3 3 2 2 1 1 D D C C B B A A
Accelerometer
Digital Gsensor
G_SENSOR_SCLK_E G_SENSOR_SDI_E G_SENSOR_CS_n_E G_SENSOR_SDO_E G_SENSOR_INT1_E G_SENSOR_INT2_E G_SENSOR_INT1_E G_SENSOR_INT2_E G_SENSOR_SCLK_E G_SENSOR_SDI_E G_SENSOR_CS_n_E G_SENSOR_SDO_E G_SENSOR_SDI G_SENSOR_SCLK G_SENSOR_CS_n G_SENSOR_SDO G_SENSOR_INT1 G_SENSOR_INT2 VCC2P5 VCC2P5_Gsensor VCC2P5_Gsensor VCC2P5_Gsensor VCC1P2 G_SENSOR_SDO 6 G_SENSOR_SDI 6 G_SENSOR_INT1 6 G_SENSOR_INT2 6 G_SENSOR_SCLK 6 G_SENSOR_CS_n 6 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Accelerometer C
DECA
B 21 25 Thursday, March 19, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Accelerometer C
DECA
B 21 25 Thursday, March 19, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Accelerometer C
DECA
B 21 25 Thursday, March 19, 2015 U30 LSF0108 GND 1 Vref_A 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 10 B8 11 B7 12 B6 13 B5 14 B4 15 B3 16 B2 17 B1 18 Vref_B 19 EN 20 EP 21 U6 LIS2DH12TR SCL/SPC 1 SDA/SDI/SDO 4 CS 2 SDO/SA0 3 Res 5 GN D 6 GN D 7 GN D 8 INT1 12 INT2 11 Vdd 9 Vdd_I O 10 R412 301 R414 301 C285 0.1u R408 200K R410 301 R416 301 R420 301 R415 301 R419 301 C284 10u C418 0.1u R409 301 R411 301 R413 301 L28 0.35ohm, 0.3A C419 0.1u R418 301 R417 301 C283 0.1u5 4 3 2 1 D D C C B B A A
LED
＊
s are ~ 1.4" to
1.6"
away from the sensor
"T" formation
configuration
Si1143
or place some other ICs to Isolate it?
Default : I2C Address 0xB4/0xB5
Proximity/Ambient Light Sensor
Note:keep the seneor close to the "hot" area on board Note:keep the seneor away from heat area
Default : I2C Address 0x80/0x81
LIGHT_I2C_SCL LIGHT_I2C_SDA LIGHT_INT VCC3P3 VCC5 VCC3P3 VCC3P3_Si1143 VCC3P3_Si1143 VCC3P3 VCC3P3 VCC3P3_HDC1000 VCC3P3_HDC1000 VCC3P3_LM71 VCC3P3_HDC1000 LIGHT_INT 4 LIGHT_I2C_SDA 4 LIGHT_I2C_SCL 4 TEMP_CS_n 4 TEMP_SIO 4 TEMP_SC 4 RH_TEMP_I2C_SDA 4 RH_TEMP_I2C_SCL 4 RH_TEMP_DRDY_n 4 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Gesture,Humidity,Temperature Sensors C
DECA
B 22 25 Wednesday, March 11, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Gesture,Humidity,Temperature Sensors C
DECA
B 22 25 Wednesday, March 11, 2015 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Gesture,Humidity,Temperature Sensors C
DECA
B 22 25 Wednesday, March 11, 2015 R43 4.99K R194 2.2K C149 0.1u U11 HDC1000YPAR SCL A1 VDD B1 ADR0 C1 ADR1 D1 DRDYn D2 DNC C2 GND B2 SDA A2 DS1 SFH4056NQ 2 1 R249 47 L22 BEAD R42 4.99K C10 0.1u C273 100u R204 2.2K DS2 SFH4056NQ 2 1 U35 LM71CIMF CS_n 1 GND 2 SIO 3 SC 4 VCC 5 L14 BEAD R203 2.2K Si1143 U28 SDA 1 SCL 2 VDD 3 INT 4 DNC_1 5 LED2 6 LED3 7 GND 8 LED1 9 DNC_2 10 R41 4.99K L5 BEAD DS3 SFH4056NQ 2 1 (1/4" dia, 3/32" tall) O-R1 Isolation O-ring C248 0.1u5 5 4 4 3 3 2 2 1 1 D D C C B B A A
Default : I2C Address 0x37
LED
KEY
SWITCH
KEY1 KEY0 SW1 SW0 LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 VCC3P3 VCC3P3_CS VCC3P3_CS VCC1P5_DDR3 VCC1P5_DDR3 VCC1P5_DDR3 VCC3P3 VCC3P3 CAP_SENSE_I2C_SCL 4 CAP_SENSE_I2C_SDA 4 LED[7..0] 6 SW[1..0] 5 KEY[1..0] 5 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CapSense Controller, Buttons, Switchs C
DECA
B
23 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CapSense Controller, Buttons, Switchs C
DECA
B
23 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CapSense Controller, Buttons, Switchs C
DECA
B 23 25 Wednesday, March 11, 2015 RN2 120 1 2 3 4 5 6 7 8 C275 0.1u R251 100K LED7 LEDB 2 1 Shield Sensor B1CapSense Button 8mm Round
DNI 1 2 U38 CY8CMBR3102-SX1I I2C_SCL 1 I2C_SDA 8 CMOD 2 VD D 4 VC C 3 VSS 5 CS1/PS1/GPO0/SH 6 CS0/PS0 7 LED0 LEDB 2 1 LED5 LEDB 2 1 Shield Sensor B0
CapSense Button 8mm Round
DNI 1 2 R173 120 R243 560 C276 0.1u SW1 SLIDE SW 1 2 3 4 5 KEY0 TACT SW 4 3 2 1 C274 1u R244 560 LED1 LEDB 2 1 SW0 SLIDE SW 1 2 3 4 5 C279 1u 10V LED3 LEDB 2 1 R100 2K R124 100K LED6 LEDB 2 1 RN3 120 1 2 3 4 5 6 7 8 CSSH1
CapSense Shield Electrode
DNI 1 KEY1 TACT SW 4 3 2 1 C277 2.2n R99 2K R164 120 L27 220 ohm, 0.3A LED4 LEDB 2 1 LED2 LEDB 2 1 C278 1u 10V
5 4 3 2 1 D D C C B B A A
Overvoltage Protection
Threshold Voltage : 5.45V
5V Power from USB Port
DC 5V Power Input
POWER
Ramp Time = 1.2 msec
1.2V / 3A
I2C ADDRESS = 1000000
Ramp Time = 1.2 msec
1.8V / 1.5A
1.5V / 1.5A
Ramp Time = 1.2 msec
Delay Enable signal
2.59 msec than AVIN
Delay Enable signal
1.1 msec than AVIN
Power up Sequence:
5V -->3.3V--->1.5V--->1.8V
--->2.5V--->1.2V--->2.8V
PMONITOR_ALERT PMONITOR_I2C_SDA PMONITOR_I2C_SCL 2P5_POK 1P8_POK 1P2_POK VCC3P3 VCC3P3 VCC5 VCC5_USB VCC3P3 VCC5 VCC3P3 VCC1P2_VCC VCC3P3 VCC1P8 VCC3P3 VCC1P5_DDR3 VCC3P3 VCC3P3 VCC1P2 PMONITOR_I2C_SCL 4 PMONITOR_I2C_SDA 4 PMONITOR_ALERT 4 1P2_POK 25 1P8_POK 25 2P5_POK 25 TitleSize Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Power - 1.2V, 1.5V, 1.8V, 5V, Power Monitor C
DECA
B
24 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Power - 1.2V, 1.5V, 1.8V, 5V, Power Monitor C
DECA
B
24 25
Wednesday, March 11, 2015 Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Power - 1.2V, 1.5V, 1.8V, 5V, Power Monitor C
