42: A Component-Based Approach to Virtual Prototyping of Heterogeneous Embedded Systems

(1)

42: A Component-Based Approach to Virtual

Prototyping of Heterogeneous Embedded Systems

Ph.D. Defense

Tayeb

bouhadiba

Directrice de th`

ese : Florence

maraninchi

Jury:

Marc

pouzet

Rapporteur

Lionel

seinturier

Rapporteur

Jean-Bernard

stefani

Examinateur

September 15th 2010

Bouhadiba - Ph.D. Defense 42 September 15th 2010 1 / 45

(2)

Embedded Systems

Consumer Electronics

Safety Critical Systems

(3)

Introduction & Sources of Inspiration Embedded Systems

Embedded Systems, Components & Heterogeneity

+

Software

Hardware

(4)

Embedded Systems, Components & Heterogeneity

+

Software

Hardware

Processors

Hardware IP’s

(Intellectual Properties)

(5)

+

Software

Hardware

Processors

Hardware IP’s

(6)

Embedded Systems, Components & Heterogeneity

+

Software

Hardware

Processors

Hardware IP’s

Digital

Analog

(7)

+

Software

Hardware

Processors

Hardware IP’s

Digital

Analog

Synchronous

Asynchronous

(8)

Virtual Prototyping

=

An Executable Model Before the System is

Manufactured

(9)

Virtual Prototyping

=

An Executable Model Before the System is

Manufactured

Modeling

(10)

Virtual Prototyping

=

Manufactured

Software

Modeling

(11)

Virtual Prototyping

=

Manufactured

Software

Virtual Prototyping

Modeling

(12)

Virtual Prototyping

=

Manufactured

Software

Virtual Prototyping

Executability

Modeling

(13)

Introduction & Sources of Inspiration Virtual Prototyping of Embedded Systems

Contents

1

Introduction & Sources of Inspiration

Virtual Prototyping of Embedded Systems

Modeling Hardware/Software with Synchronous Languages

Ptolemy

Specifying Components: Contracts

2

Overview of 42 & Examples

[GPCE07]

3

Hardware Simulation by Interpreting Contracts

[COORD09]

4

Using 42 Together with Existing Approaches

[EMSOFT09]

5

Some Related Work

6

Summary

(14)

SystemC/TLM for Systems-on-a-Chip

Hardware Architecture

A SoC (System-on-a-Chip)

while(true) x = 42; while (xneq0) y = read(addrM + x); write(addrM , x); ... write(addrD+0x0, addrM); write(addrD+0x1, 42); write(addrD+0x4, 0x01); ... ...

Embedded Software

(15)

CPU

provides

(Transaction-Level Modeling)

TLM

Virtual Prototype

Early Available

Embedded Software

(16)

SystemC/TLM for Systems-on-a-Chip

CPU

provides

TLM

Virtual Prototype

Embedded Software

(17)

CPU

provides

TLM

Virtual Prototype

Early Available

Embedded Software

(18)

Virtual Prototyping of Sensor Networks

Several sensors communicating by radio

Network lifetime depends on energy consumption

Use of virtual prototyping to study non-functional aspects

(e.g., energy)

CPU, Sensor, Memory, Radio,

Battery

(19)

Introduction & Sources of Inspiration Modeling Hardware/Software with Synchronous Languages

Summary

(20)

Modeling HW/SW with Synchronous Languages

is Embedded in the ATV

PFS (Proximity Flight Safety)

ATV (Automated Transfer Vehicule)

Models via a Translation into Synchronous Programs”

[EMSOFT07]

(21)

Modeling HW/SW with Synchronous Languages

The original model of the PFS

is written in AADL

(Architecture Analysis and Design Language)

(Not Executbale)

“E. Jahier, N. Halbwachs, P. Raymond, X. Nicollin, D. Lesens, Virtual Execution of AADL

Models via a Translation into Synchronous Programs”

[EMSOFT07]

(22)

Modeling HW/SW with Synchronous Languages

Automatic Translation

into Lustre

PFS description in Lustre

Simulation

Automatic Testing

The original model of the PFS

is written in AADL

(Architecture Analysis and Design Language)

(Not Executbale)

(23)

Introduction & Sources of Inspiration Ptolemy

Contents

1

Modeling Hardware/Software with Synchronous Languages

Ptolemy

2

[GPCE07]

3

[COORD09]

4

[EMSOFT09]

5

Some Related Work

6

Summary

(24)

Ptolemy

ptolemy.eecs.berkeley.edu

MoCC : Model of Computation and Communication

composite actor

hierarchical abstraction actor port external port

Components are actors

The director implements a MoCC

Hierarchical framework

∃

a catalogue of predefined MoCCs:

Synchronous Reactive, Discrete Event, Continuous Time, etc.

(25)

Introduction & Sources of Inspiration Specifying Components: Contracts

Contents

1

Modeling Hardware/Software with Synchronous Languages

Ptolemy

2

[GPCE07]

3

[COORD09]

4

[EMSOFT09]

5

Some Related Work

6

Summary

(26)

Classification of Contracts in the CBSE Community

(Component-Based Software Engineering)

Syntactic contracts

Interface Description languages

(Java-IDL, WSDL, IDL, etc.)

Behavioral contracts

pre and post conditions, assertions, etc.

(Design by Contracts

TM

, Eiffel, iContracts, etc.)

Synchronization contracts

Sequence of method-calls, Component synchronization, etc.

(PROCOL, Interface automata, Session types, etc.)

Quality of service contracts

Resource consumption, Image quality, etc.

(27)

Introduction & Sources of Inspiration Specifying Components: Contracts

Contracts in the Hardware Community

and the Synchronous Languages

Don’t care conditions

Hardware optimization

Conditional dependencies in Signal

Cycle analysis in synchronous circuits

Assume/Guarantee reasoning

Modular verification (K. McMillan)

Executable specifications for Lustre (L. Morel)

b

o’

o

i

b

i

o

o’

A

G

b

i

o’

o

?

o depends on i when b=true

Input (ib)=(01) never occurs

(28)

Observation & Motivations of 42

In each context of Virtual Prototyping of embedded systems, there exists a

notion of components and MoCCs related issues

42 aims at providing:

A

language-independent

component-based framework for modeling

hardware/software systems.

Support for a clean definition of components, and help enforcing the

FAMAPASAP

(Forget As Much As Possible As Soon As Possible)

principle.

Support for integration of

existing code and models

in open virtual

prototyping environments.

(29)

Overview of 42 & Examples[GPCE07] Components & Assemblies

Contents

1

2

[GPCE07]

Components & Assemblies

Explicit Specification of Components (Contracts)

3

[COORD09]

4

[EMSOFT09]

5

Some Related Work

6

Summary

(30)

oc2

Output Control Ports

oc1:

{

a, b, c

}

oc2:

{

T, F

}

Data Ports

Input

Input Control Ports

ic2

ic1

od3

od2

od1

Output

Data Ports

id3

id2

id1

M: internal memory

f o r

i c 1 do :

{

a := i d 1 ;

b := i d 2 ;

od1 := f ( a , b ) ;

o c 1 := ok ;

M := !M;

}

. . .

(31)

42 in a Nutshell: Basic Components

step

atomic

A

oc2

oc1:

{

a, b, c

}

oc2:

{

T, F

}

Data Ports

Input

Input Control Ports

ic2

ic1

od3

od2

od1

Output

Data Ports

id3

id2

id1

M: internal memory

. . .

f o r

i c 1 do :

{

a := i d 1 ;

b := i d 2 ;

od1 := f ( a , b ) ;

o c 1 := ok ;

M := !M;

}

. . .

(32)

42 in a Nutshell: Assembling Components

v a r

M :

b o o l

;

f o r

OP

G

do

:

{

/

∗

d e f i n e s

opg .

dw

,

d r ,

reqw

, . . . :

f i f o

( 1 , i n t ) ;

M :=

random

( ) ;

i f

(M)

{

PROD

.

op

;

r eqw

.

p u t

;

reqw

.

g e t

;

FIFO

.

op

;

gw

.

p u t

;

gw

.

g e t

;

a :=

FIFO

.

r e p o r t

;

/

∗

r e a d s o c .

i f

( a==ok )

{

/

∗

o u t p u t

c o n t r o l

PROD

.

op

;

dw

.

p u t

;

dw

.

g e t

;

FIFO

.

op

;

/

∗

a c t i v a t e s FIFO .

. . .

}

. . .

}

e l s e

{

CONS

.

op

;

r e q r

.

p u t

;

r e q r

.

g e t

;

FIFO

.

op

;

g r

.

p u t

;

g r

.

g e t

;

a :=

FIFO

.

r e p o r t

;

. . .

}

For each

OP

G

the controller:

Activates PROD, CONS, FIFO through op

Reads their output control ports (report)

Manages a temporary memory (reqr, dr,...)

Sets global output values

0101

01

0101

01

0101 01

01

0101

01

PROD

FIFO

CONS

op

G

op

report

(33)

42 in a Nutshell: Assembling Components

C o n t r o l l e r

i s

{

v a r

M :

b o o l

;

f o r

OP

G

do

:

{

/

∗

d e f i n e s

opg .

dw

,

d r ,

reqw

, . . . :

f i f o

( 1 , i n t ) ;

M :=

random

( ) ;

i f

(M)

{

PROD

.

op

;

r eqw

.

p u t

;

reqw

.

g e t

;

FIFO

.

op

;

gw

.

p u t

;

gw

.

g e t

;

a :=

FIFO

.

r e p o r t

;

/

∗

r e a d s o c .

i f

( a==ok )

{

/

∗

o u t p u t

c o n t r o l

PROD

.

op

;

dw

.

p u t

;

dw

.

g e t

;

FIFO

.

op

;

/

∗

a c t i v a t e s FIFO .

. . .

}

. . .

}

e l s e

{

CONS

.

op

;

r e q r

.

p u t

;

r e q r

.

g e t

;

FIFO

.

op

;

g r

.

p u t

;

g r

.

g e t

;

a :=

FIFO

.

r e p o r t

;

. . .

}

For each

OP

G

the controller:

Sets global output values

g

w

req

r

req

w

d

w

d

r

g

r

0101

01

0101

01

0101 01

01

0101

01

PROD

FIFO

CONS

op

G

op

report

(34)

v a r

M :

b o o l

;

f o r

OP

G

do

:

{

/

∗

d e f i n e s

opg .

dw

,

d r ,

reqw

, . . . :

f i f o

( 1 , i n t ) ;

M :=

random

( ) ;

i f

(M)

{

PROD

.

op

;

r eqw

.

p u t

;

reqw

.

g e t

;

FIFO

.

op

;

gw

.

p u t

;

gw

.

g e t

;

a :=

FIFO

.

r e p o r t

;

/

∗

r e a d s o c .

i f

( a==ok )

{

/

∗

o u t p u t

c o n t r o l

PROD

.

op

;

dw

.

p u t

;

dw

.

g e t

;

FIFO

.

op

;

/

∗

. . .

}

. . .

}

e l s e

{

CONS

.

op

;

r e q r

.

p u t

;

r e q r

.

g e t

;

FIFO

.

op

;

g r

.

p u t

;

g r

.

g e t

;

a :=

FIFO

.

r e p o r t

;

. . .

}

For each

OP

G

the controller:

0000000

1111111

controller

g

w

req

r

req

w

d

w

d

r

g

r

0101

01

0101

01

0101 01

01

0101

01

PROD

FIFO

CONS

op

G

op

report

(35)

42 in a Nutshell: Assembling Components

C o n t r o l l e r

i s

{

v a r

M :

b o o l

;

f o r

OP

G

do

:

{

/

∗

d e f i n e s

opg .

dw

,

d r ,

reqw

, . . . :

f i f o

( 1 , i n t ) ;

M :=

random

( ) ;

i f

(M)

{

PROD

.

op

;

r eqw

.

p u t

;

reqw

.

g e t

;

FIFO

.

op

;

gw

.

p u t

;

gw

.

g e t

;

a :=

FIFO

.

r e p o r t

;

/

∗

r e a d s o c .

i f

( a==ok )

{

/

∗

o u t p u t

c o n t r o l

PROD

.

op

;

dw

.

p u t

;

dw

.

g e t

;

FIFO

.

op

;

/

∗

. . .

}

. . .

}

e l s e

{

CONS

.

op

;

r e q r

.

p u t

;

r e q r

.

g e t

;

FIFO

.

op

;

g r

.

p u t

;

g r

.

g e t

;

a :=

FIFO

.

r e p o r t

;

. . .

}

For each

OP

G

the controller:

Sets global output values

0000000

1111111

controller

g

w

req

r

req

w

d

w

d

r

g

r

0101

01

0101

01

0101 01

01

0101

01

PROD

FIFO

CONS

op

G

op

report

(36)

v a r

M :

b o o l

;

f o r

OP

G

do

:

{

/

∗

d e f i n e s

opg .

dw

,

d r ,

reqw

, . . . :

f i f o

( 1 , i n t ) ;

M :=

random

( ) ;

i f

(M)

{

PROD

.

op

;

r eqw

.

p u t

;

reqw

.

g e t

;

FIFO

.

op

;

gw

.

p u t

;

gw

.

g e t

;

a :=

FIFO

.

r e p o r t

;

/

∗

r e a d s o c .

i f

( a==ok )

{

/

∗

o u t p u t

c o n t r o l

PROD

.

op

;

dw

.

p u t

;

dw

.

g e t

;

FIFO

.

op

;

/

∗

a c t i v a t e s FIFO .

. . .

}

. . .

}

e l s e

{

CONS

.

op

;

r e q r

.

p u t

;

r e q r

.

g e t

;

FIFO

.

op

;

g r

.

p u t

;

g r

.

g e t

;

a :=

FIFO

.

r e p o r t

;

. . .

}

For each

OP

G

the controller:

0000000

1111111

controller

g

w

req

r

req

w

d

w

d

r

g

r

0101

01

0101

01

0101 01

01

0101

01

PROD

FIFO

CONS

op

G

op

report

(37)

C o n t r o l l e r

i s

{

v a r

M :

b o o l

;

f o r

OP

G

do

:

{

/

∗

d e f i n e s

opg .

dw

,

d r ,

reqw

, . . . :

f i f o

( 1 , i n t ) ;

M :=

random

( ) ;

i f

(M)

{

PROD

.

op

;

r eqw

.

p u t

;

reqw

.

g e t

;

FIFO

.

op

;

gw

.

p u t

;

gw

.

g e t

;

a :=

FIFO

.

r e p o r t

;

/

∗

r e a d s o c .

i f

( a==ok )

{

/

∗

o u t p u t

c o n t r o l

PROD

.

op

;

dw

.

p u t

;

dw

.

g e t

;

FIFO

.

op

;

/

∗

. . .

}

. . .

}

e l s e

{

CONS

.

op

;

r e q r

.

p u t

;

r e q r

.

g e t

;

FIFO

.

op

;

g r

.

p u t

;

g r

.

g e t

;

a :=

FIFO

.

r e p o r t

;

. . .

}

For each

OP

G

the controller:

Reads their output control ports (report)

0000000

1111111

controller

g

w

req

r

req

w

d

w

d

r

g

r

0101

01

0101

01

0101 01

01

0101

01

PROD

FIFO

CONS

op

G

op

report

(38)

C o n t r o l l e r

i s

{

v a r

M :

b o o l

;

f o r

OP

G

do

:

{

/

∗

d e f i n e s

opg .

dw

,

d r ,

reqw

, . . . :

f i f o

( 1 , i n t ) ;

M :=

random

( ) ;

i f

(M)

{

PROD

.

op

;

r eqw

.

p u t

;

reqw

.

g e t

;

FIFO

.

op

;

gw

.

p u t

;

gw

.

g e t

;

a :=

FIFO

.

r e p o r t

;

/

∗

r e a d s o c .

i f

( a==ok )

{

/

∗

o u t p u t

c o n t r o l

PROD

.

op

;

dw

.

p u t

;

dw

.

g e t

;

FIFO

.

op

;

/

∗

a c t i v a t e s FIFO .

. . .

}

. . .

}

e l s e

{

CONS

.

op

;

r e q r

.

p u t

;

r e q r

.

g e t

;

FIFO

.

op

;

g r

.

p u t

;

g r

.

g e t

;

a :=

FIFO

.

r e p o r t

;

. . .

}

For each

OP

G

the controller:

0000000

1111111

controller

g

w

req

r

req

w

d

w

d

r

g

r

0101

01

0101

01

0101 01

01

0101

01

PROD

FIFO

CONS

op

G

op

report

(39)

C o n t r o l l e r

i s

{

v a r

M :

b o o l

;

f o r

OP

G

do

:

{

/

∗

d e f i n e s

opg .

dw

,

d r ,

reqw

, . . . :

f i f o

( 1 , i n t ) ;

M :=

random

( ) ;

i f

(M)

{

PROD

.

op

;

r eqw

.

p u t

;

reqw

.

g e t

;

FIFO

.

op

;

gw

.

p u t

;

gw

.

g e t

;

a :=

FIFO

.

r e p o r t

;

/

∗

r e a d s o c .

i f

( a==ok )

{

/

∗

o u t p u t

c o n t r o l

PROD

.

op

;

dw

.

p u t

;

dw

.

g e t

;

FIFO

.

op

;

/

∗

. . .

}

. . .

}

e l s e

{

CONS

.

op

;

r e q r

.

p u t

;

r e q r

.

g e t

;

FIFO

.

op

;

g r

.

p u t

;

g r

.

g e t

;

a :=

FIFO

.

r e p o r t

;

. . .

}

For each

OP

G

the controller:

Reads their output control ports (report)

0000000

1111111

controller

g

w

req

r

req

w

d

w

d

r

g

r

0101

01

0101

01

0101 01

01

0101

01

PROD

FIFO

CONS

op

G

op

report

(40)

C o n t r o l l e r

i s

{

v a r

M :

b o o l

;

f o r

OP

G

do

:

{

/

∗

d e f i n e s

opg .

dw

,

d r ,

reqw

, . . . :

f i f o

( 1 , i n t ) ;

M :=

random

( ) ;

i f

(M)

{

PROD

.

op

;

r eqw

.

p u t

;

reqw

.

g e t

;

FIFO

.

op

;

gw

.

p u t

;

gw

.

g e t

;

a :=

FIFO

.

r e p o r t

;

/

∗

r e a d s o c .

i f

( a==ok )

{

/

∗

o u t p u t

c o n t r o l

PROD

.

op

;

dw

.

p u t

;

dw

.

g e t

;

FIFO

.

op

;

/

∗

a c t i v a t e s FIFO .

. . .

}

. . .

}

e l s e

{

CONS

.

op

;

r e q r

.

p u t

;

r e q r

.

g e t

;

FIFO

.

op

;

g r

.

p u t

;

g r

.

g e t

;

a :=

FIFO

.

r e p o r t

;

. . .

}

For each

OP

G

the controller:

0000000

1111111

controller

g

w

req

r

req

w

d

w

d

r

g

r

0101

01

0101

01

0101 01

01

0101

01

PROD

FIFO

CONS

op

G

op

report

(41)

C o n t r o l l e r

i s

{

v a r

M :

b o o l

;

f o r

OP

G

do

:

{

/

∗

d e f i n e s

opg .

dw

,

d r ,

reqw

, . . . :

f i f o

( 1 , i n t ) ;

M :=

random

( ) ;

i f

(M)

{

PROD

.

op

;

r eqw

.

p u t

;

reqw

.

g e t

;

FIFO

.

op

;

gw

.

p u t

;

gw

.

g e t

;

a :=

FIFO

.

r e p o r t

;

/

∗

r e a d s o c .

i f

( a==ok )

{

/

∗

o u t p u t

c o n t r o l

PROD

.

op

;

dw

.

p u t

;

dw

.

g e t

;

FIFO

.

op

;

/

∗

. . .

}

. . .

}

e l s e

{

CONS

.

op

;

r e q r

.

p u t

;

r e q r

.

g e t

;

FIFO

.

op

;

g r

.

p u t

;

g r

.

g e t

;

a :=

FIFO

.

r e p o r t

;

. . .

}

For each

OP

G

the controller:

Reads their output control ports (report)

0000000

1111111

controller

g

w

req

r

req

w

d

w

d

r

g

r

0101

01

0101

01

0101 01

01

0101

01

PROD

FIFO

CONS

op

G

op

report

(42)

Summary of 42 Basics

Summary of 42

Hierarchical

model =

⇒

modeling

heterogeneity

in the same spirit as Ptolemy

Controllers are expressed as

programs

identification of the basic primitives for describing MoCCs

Separation of

control/data

to enforce the FAMAPASAP

more details later

(43)

Overview of 42 & Examples[GPCE07] Explicit Specification of Components (Contracts)

Control Contracts for 42 Components

0

1

0

1

0

1

0

1 0

1

id1

id2

id3

od1

od2

od3

step

atomic

internal memory

oc2

oc1

ic2

ic1

Input Control Ports

Output

Data

P

ort

s

Input

Data

P

orts

c1

c2

c0

oc2:

{

T, F

}

oc1:

{

a, b, c

}

Allowed activation sequences

Data dependencies (

Required

,

Provided

)

Control information

Conditional activations.

Conditional data dependencies.

(44)

ic1

ic2

ic1

ic2

0

1

0

1

0

1

0

1 0

1

id1

id2

id3

od1

od2

od3

step

atomic

internal memory

oc2

oc1

ic2

ic1

Input Control Ports

Output

Data

P

ort

s

Input

Data

P

orts

c1

c2

c0

oc2:

{

T, F

}

oc1:

{

a, b, c

}

Control information

(45)

{

id1

}

{}

{

od2

}

{

id1

}

{

od2

}

{

id2

}

{

od1; od3=L

}

ic1

ic2

ic1

ic2

0

1

0

1

0

1

0

1 0

1

id1

id2

id3

od1

od2

od3

step

atomic

internal memory

oc2

oc1

ic2

ic1

Input Control Ports

Output

Data

P

ort

s

Input

Data

P

orts

c1

c2

c0

oc2:

{

T, F

}

oc1:

{

a, b, c

}

Data dependencies (

Required

,

Provided

)

Control information

(46)

Control Contracts for 42 Components

/α

=

oc

2

/α

=

oc

2

/β

=

oc

1

{

id1

}

{}

{

od2

}

{

id1

}

{

od2

}

{

id2

}

{

od1; od3=L

}

ic1

ic2

ic1

ic2

0

1

0

1

0

1

0

1 0

1

id1

id2

id3

od1

od2

od3

step

atomic

internal memory

oc2

oc1

ic2

ic1

Input Control Ports

Output

Data

P

ort

s

Input

Data

P

orts

c1

c2

c0

oc2:

{

T, F

}

oc1:

{

a, b, c

}

Data dependencies (

Required

,

Provided

)

Control information

(47)

Control Contracts for 42 Components

[

α

=

T

]

[

α

=

F

]

/α

=

oc

2

/α

=

oc

2

/β

=

oc

1

{

id1

}

{}

{

od2

}

{

id1

}

{

od2

}

{

id2

}

{

od1; od3=L

}

ic1

ic2

ic1

ic2

0

1

0

1

0

1

0

1 0

1

id1

id2

id3

od1

od2

od3

step

atomic

internal memory

oc2

oc1

ic2

ic1

Input Control Ports

Output

Data

P

ort

s

Input

Data

P

orts

c1

c2

c0

oc2:

{

T, F

}

oc1:

{

a, b, c

}

Data dependencies (

Required

,

Provided

)

Control information

(48)

Control Contracts for 42 Components

{

if (

β

=a) then od2;

}

[

α

=

T

]

[

α

=

F

]

/α

=

oc

2

/α

=

oc

2

/β

=

oc

1

{

id1

}

{}

{

od2

}

{

id1

}

{

od2

}

{

id2

}

{

od1; od3=L

}

ic1

ic2

ic1

ic2

0

1

0

1

0

1

0

1 0

1

id1

id2

id3

od1

od2

od3

step

atomic

internal memory

oc2

oc1

ic2

ic1

Input Control Ports

Output

Data

P

ort

s

Input

Data

P

orts

c1

c2

c0

oc2:

{

T, F

}

oc1:

{

a, b, c

}

Data dependencies (

Required

,

Provided

)

Control information

(49)

What are 42 Contracts used for?

42 contracts (+ the Architecture Description Language)

Testing controllers/components consistency

Contract Interpretation

Testing component/contract consistency

0000000

1111111

controller

00

11

00

11

00

11

0101

01

0

1

0

1

10

0

1

0

1

PROD

op

report

FIFO

op

report

CONS

op

report

(50)

What are 42 Contracts used for?

Testing component/contract consistency

0000000

1111111

controller

00

11

00

11

00

11

0101

01

0

1

0

1

10

0

1

0

1

PROD

op

report

FIFO

op

report

CONS

op

report

(51)

0000000

1111111

controller

00

11

00

11

00

11

0101

01

0

1

0

1

10

0

1

0

1

PROD

op

report

FIFO

op

report

CONS

op

report

(52)

0000000

1111111

controller

00

11

00

11

00

11

0101

01

0

1

0

1

10

0

1

0

1

PROD

op

report

FIFO

op

report

CONS

op

report

(53)

42 contracts (+ the Architecture Description Language)

0000000

1111111

controller

00

11

00

11

00

11

0101

01

0

1

0

1

10

0

1

0

1

PROD

op

report

FIFO

op

report

CONS

op

report

(54)

Testing component/contract consistency

?

0000000

1111111

controller

00

11

00

11

00

11

0101

01

0

1

0

1

10

0

1

0

1

PROD

op

report

FIFO

op

report

CONS

op

report

(55)

Hardware Simulation by Interpreting Contracts[COORD09]

Contents

1

2

[GPCE07]

3

[COORD09]

Contract Interpretation for Hardware Simulation

Executing Embedded Software on Hardware Models

4

Using 42 Together with Existing Approaches

[EMSOFT09]

5

Some Related Work

6

Summary

(56)

Contract Interpretation: Principle

a2

a

b

op

end

A

op

end

B

ctrl Async

a3

a1

Contract A

b2

b3

b1

{}

op

{}

op

{

b

}

{

a

}

op

{}

Contract B

{

b

}

op

{}

[

α

=

y

]

{}

op

{

a

}

{}

op

/α

=

end

{}

[α

=

n

]

{}

op

/α

=

end

{}

(57)

Hardware Simulation by Interpreting Contracts[COORD09] Contract Interpretation

α

=

⊥

available=

b1

{}

a1

a2

a

b

op

end

A

op

end

B

ctrl Async

a3

a1

Contract A

b2

b3

b1

{}

op

{}

op

{

b

}

{

a

}

op

{}

Contract B

{

b

}

op

{}

[

α

=

y

]

{}

op

{

a

}

{}

op

/α

=

end

{}

The controller maintains:

The current state of each contract

The set of available data

The values of the variables(α)

[α

=

n

]

{}

op

/α

=

end

{}

(58)

available=

{}

available=

{}

A.op

a2

available=

{}

α

=

y

b1

a2

A.op

B.op

b2

a1

α

=

⊥

α

=

n

b1

α

=

⊥

available=

b1

{}

a1

a2

a

b

op

end

A

op

end

B

ctrl Async

a3

a1

Contract A

b2

b3

b1

{}

op

{}

op

{

b

}

{

a

}

op

{}

Contract B

{

b

}

op

{}

[

α

=

y

]

{}

op

{

a

}

{}

op

/α

=

end

{}

For each global activation :

Depending on the available data it selects a

component and activates it

The set of available data is updated

The output controls are given

non-deterministic values

[α

=

n

]

{}

op

/α

=

end

{}

(59)

Contract Interpretation: Principle

available=

{

a

}

A.op

a3 b1

A.op

B.op

b2

available=

{

a

}

a3

B.op

a1 b3

available=

{

b

}

a1 b3

available=

{

a

}

A.op

B.op

a3 b3

available=

{

a

,

b

}

A.op

α

=

⊥

α

=

⊥

α

=

⊥

α

=

⊥

α

=

y

available=

{}

available=

{}

A.op

a2

available=

{}

α

=

y

b1

a2

A.op

B.op

b2

a1

α

=

⊥

α

=

n

b1

α

=

⊥

available=

b1

{}

a1

a2

a

b

op

end

A

op

end

B

ctrl Async

a3

a1

Contract A

b2

b3

b1

{}

op

{}

op

{

b

}

{

a

}

op

{}

Contract B

{

b

}

op

{}

[

α

=

y

]

{}

op

{

a

}

{}

op

/α

=

end

{}

[α

=

n

]

{}

op

/α

=

end

{}

(60)

Example execution path

available=

{

a

}

A.op

a3 b1

A.op

B.op

b2

available=

{

a

}

a3

B.op

a1 b3

available=

{

b

}

a1 b3

available=

{

a

}

A.op

B.op

a3 b3

available=

{

a

,

b

}

A.op

α

=

⊥

α

=

y

available=

{}

available=

{}

A.op

a2

available=

{}

α

=

y

b1

a2

A.op

B.op

b2

a1

α

=

⊥

α

=

n

b1

α

=

⊥

available=

b1

{}

a1

a2

a

b

op

end

A

op

end

B

ctrl Async

a3

a1

Contract A

b2

b3

b1

{}

op

{}

op

{

b

}

{

a

}

op

{}

Contract B

{

b

}

op

{}

[

α

=

y

]

{}

op

{

a

}

{}

op

/α

=

end

{}

[α

=

n

]

{}

op

/α

=

end

{}

(61)

A.op

available=

{

a

}

A.op

a3 b1

A.op

B.op

b2

available=

{

a

}

a3

B.op

a1 b3

available=

{

b

}

a1 b3

available=

{

a

}

A.op

B.op

a3 b3

available=

{

a

,

b

}

A.op

α

=

⊥

α

=

⊥

α

=

⊥

α

=

⊥

α

=

y

available=

{}

available=

{}

A.op

a2

available=

{}

α

=

y

b1

a2

A.op

B.op

b2

a1

α

=

⊥

α

=

n

b1

α

=

⊥

available=

b1

{}

a1

a2

a

b

op

end

A

op

end

B

ctrl Async

a3

a1

Contract A

b2

b3

b1

{}

op

{}

op

{

b

}

{

a

}

op

{}

Contract B

{

b

}

op

{}

[

α

=

y

]

{}

op

{

a

}

{}

op

/α

=

end

{}

[α

=

n

]

{}

op

/α

=

end

{}

(62)

requires b

X

A.op

available=

{

a

}

A.op

a3 b1

A.op

B.op

b2

available=

{

a

}

a3

B.op

a1 b3

available=

{

b

}

a1 b3

available=

{

a

}

A.op

B.op

a3 b3

available=

{

a

,

b

}

A.op

α

=

⊥

α

=

y

available=

{}

available=

{}

A.op

a2

available=

{}

α

=

y

b1

a2

A.op

B.op

b2

a1

α

=

⊥

α

=

n

b1

α

=

⊥

available=

b1

{}

a1

a2

a

b

op

end

A

op

end

B

ctrl Async

a3

a1

Contract A

b2

b3

b1

{}

op

{}

op

{

b

}

{

a

}

op

{}

Contract B

{

b

}

op

{}

[

α

=

y

]

{}

op

{

a

}

{}

op

/α

=

end

{}

[α

=

n

]

{}

op

/α

=

end

{}

(63)

Hardware Simulation by Interpreting Contracts[COORD09] Contract Interpretation for Hardware Simulation

Modeling Hardware with 42: Case Study

Embedded Software

#d e f i n e w i d t h 240 #d e f i n e h e i g h t 240 #d e f i n e g r e e n 0x0000AABB . . . i n t main ( ) { w h i l e ( 1 ) { //∗w r i t i n g t h e g r e e n i m a g e∗/ f o r ( i n t x =0; x<w i d t h ∗ h e i g h t ) w r i t e m e m( g r e e n ) ; w r i t e l c d( 0 x01 , 0 x1 ) ; w a i t i n t e r r u p t( ) ; //∗w r i t i n g t h e b l u e i m a g e∗/ f o r ( i n t x =0; x<w i d t h ∗ h e i g h t ) w r i t e m e m( b l u e ) ; w r i t e l c d( 0 x01 , 0 x1 ) ; w a i t i n t e r r u p t( ) ; //∗w r i t i n g t h e r e d i m a g e∗/ f o r ( i n t x =0; x<w i d t h ∗ h e i g h t ) w r i t e m e m( r e d ) ; w r i t e l c d( 0 x01 , 0 x1 ) ; w a i t i n t e r r u p t( ) ; } }

Interrupt

MEM

CPU

status

data

address

r/w

BUS

address

r/w

status

data

address

r/w

LCD

status

(display)

(64)

Modeling Hardware with 42: Case Study

Embedded Software

Interrupt

MEM

CPU

status

data

address

r/w

BUS

address

r/w

status

data

address

r/w

LCD

status

(display)

(65)

Embedded Software

Interrupt

MEM

CPU

status

data

address

r/w

BUS

address

r/w

status

data

address

r/w

LCD

status

(display)

(66)

Embedded Software

Interrupt

MEM

CPU

status

data

address

r/w

BUS

address

r/w

status

data

address

r/w

LCD

status

(display)

(67)

Modeling Hardware with 42: Case Study

Embedded Software

Interrupt

MEM

CPU

status

data

address

r/w

BUS

address

r/w

status

data

address

r/w

LCD

status

(display)

(68)

Embedded Software

b

a

c

d

Interrupt

MEM

CPU

status

data

address

r/w

BUS

address

r/w

status

data

address

r/w

LCD

status

(display)

(69)

Embedded Software

ok

b

a

c

d

Interrupt

MEM

CPU

status

data

address

r/w

BUS

address

r/w

status

data

address

r/w

LCD

status

(display)

(70)

Modeling Hardware with 42: Case Study

Embedded Software

ok

b

a

c

d

Interrupt

MEM

CPU

status

data

address

r/w

BUS

address

r/w

status

data

address

r/w

LCD

status

(display)

(71)

Embedded Software

ok

b

a

c

d

Interrupt

MEM

CPU

status

data

address

r/w

BUS

address

r/w

status

data

address

r/w

LCD

status

(display)

bug

X

(Synchronization)

// wait interrupt() ;

(72)

Embedded Software

ok

b

a

c

d

Interrupt

MEM

CPU

status

data

address

r/w

BUS

address

r/w

status

data

address

r/w

LCD

status

(display)

X

bug

(Data)

24

bug

X

(Synchronization)

// wait interrupt() ;

(73)

Modeling Hardware with 42: The 42 Model

0

1

0

1

0

1

₀

0

11

resp

LT

acd

L

op

report

op

BUS

intr

op

resp

C

op

acd

C

target

report

0

resp

M

acd

M

op

resp

L

acd

LT

CPU

LCD

MEM

Interpreter

Contract

(74)

Modeling Hardware with 42: The contracts (CPU)

c4

c4’

c0

c3

c1

c2

c3’

c1’

c2’

{

intr=t

}

op

{}

{

intr=t

}

op

{}

{

intr=t

}

op

{}

{

intr=t

}

op

{}

{

intr=t

}

op

{}

op/α=report

{}

[α=MT]

{}

op

{

acdC

; target=M

}

[α=MT]

{}

op

{

acdC

; target=M

}

{

intr=t

}

op

{}

{

respC

}

op/α=report; report’=IT

{}

op/α=report

{}

{

intr=t

}

op

{}

{

respC

}

op/α=report; report’=IT

{}

{

re