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Modeling and Analysis of RLCG Interconnect

using Fourier Series and Frequency Shift

Techniques

1

Pratiksha Singh Gaur, 2 Dr.Vivek Singh Kushwah

1

Dept of Elect. And Comm., Amity University Gwalior, Madhya Pradesh, India

2

Dept of Elect. And Comm., Amity University Gwalior, Madhya Pradesh, India

Abstract - A high speed RLCG circuit interconnects has become faultless and has suited essential to address signal integrity. For faultless representation a full wave exploration is required. Typically circuit simulation of RLC interconnect CPU is lavish. This paper discusses RLCG full wave exploration using frequency shift techniques. The results shown are efficient. It can also be done by Fourier series analysis. A logical interconnects representation is introduce based on Fourier series exploration satisfactory for periodic signal such as clock signal. In this representation, the far end time domain zone waveform is estimates by the super-impose of various sinusoids. The fifth and the higher harmonics are ignored when closed form response of the 50% lag. The representation is applied to the various allocated coupled interconnect and interconnected trees. Good exactness is detecting intermediately within the SPICE and model simulation. The computation complication of the representation is linear with the number of harmonics.

Keywords - Fourier series, Crosstalk, Frequency Shift Technique, RLCG Interconnect, VLSI.

1. Introduction

A high speed interconnect have become prominent [1, 2] due to circuit switching continue to increase, such as rise in degradation, overshoot, undershoot, signal delay and reflections as well as crosstalk between adjacent lines. As a result, transverse electromagnetic mode, lumped models give the inaccurate performance, in such condition full wave analysis is required [3, 4]. It takes all possible boundary conditions. In a built up circuit model the resistance, inductance and the capacitance is used for exploration of proposed circuit model and used for reduction [5, 6], intricate frequencies, intricate frequency hopping, and krylov-space procedure [7]. In this paper it is

allotment simulated port acknowledgement reveal to the passitivity of annex models [8]. The Elmore delay model has been widely used, and have to explore annex synthesis and static timing for explore RLC network [9]. RLC annex are widely used on chip global annex boundary conditions and describe the compressed transient response of high-speed annex dispense resistance, inductance, capacitance [11]. This paper basically introduces a precise exploration for the effects for distributed RLC interconnects that consider both the series resistance and the output parasitic capacitance of the driver into account. Apply a couple of calculations, precise expressions for the transfer function have been presented [12]. To calculate the RLC annex delay, the Elmore delay has been widely used on integration VLSI topologies; Elmore delay deviate signification from MATLAB computed delay [13].

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satisfied results for up to 5000

µ

m

long lines when compared to MATLAB over accurate distributed RLCG circuit model and can be used to model on-chip wires in the layout design logic synthesis and high level design [18]. RLC tree are presented with 50% closed form solution, rise time, overshoots at setting time, peak time,etc. Elmore delay is used tp conserve the integrity peculiar [19]. Asymptotic waveform evaluation (AWE) provides a generalized approach to linear RLCG circuit response approximations. In essence the propagation delay in the digital system design can have a critical and a dominant impact on achievements, the model proposed of RLCG components or RLCG annex comprises of grounded resistors, floating capacitors, inductors and most important the sources which are linearly controlled [20]. An inconsistent transient simulation of lossy annex concludes an inconsistent non-linear element based on convolution simulation is presented [21].

This model exists of two interchangeable conversion networks and n-single transmission line models [22]. This paper presents adequate decoupling models for on-chip annex exploration [23]. Paper present an accurate and efficient model to compute the delay metric of on-chip high speed VLSI annex for ramp input [24]. This paper presents an accurate fast and simple closed form solution to estimate crosstalk noise between adjacent wires in VLSI circuits using RLCG annex model. Remaining part of the paper is synchronized as follows: section 2 describes the modeling of high speed RLCG interconnects using Frequency Shift Technique. A Fourier Series-Based RLCG Interconnect Model for Periodic Signals is discussed in section 3. Section 4 illustrates the simulation result for the proposed model. Finally section 5 concludes this paper.2.

2. Modeling of Full-Wave High Speed

Interconnects

Consider the transmission line system as shown in Figure 1.We use telegraph equation for transmission line. Telegrapher’s equation consists of a infinite length and assuming uniform per unit length parameters of resistance(R), inductance (L), conductance (G), and capacitance(C).

Fig.1. A Typical Transmission Line System

) , ( )

,. ( ) ,

( i xt

x L t x Ri t x v

x

∂ − −

= ∂

(1)

)

, ( )

, ( ) ,

( v xt

x C t x Gv t x i

x

∂ − −

= ∂

(2)

Equation (1) and (2) is a telegraph equation and can also

be represented in following form.

) , ( ) ,

(xs ZIxs V

x =−

∂ ∂

(3)

, , (4)

Where Z and Y represent the impedance and admittance

matrices and G represent the conductance. R represents the resistance, C represents the capacitance, L represents the inductance. R, L, G and C and matrices are symmetric and positive definite. The R, L, G and C matrices are obtained by a 2-D solution of Maxwell’s equations at appropriate positions, along the propagation axis.

ZY

j

s

=

α

+

β

=

γ

(

)

(5)

Where

sL sC G Y sC sL R

Z = + + 1 , = + +

substuting expression of Z and Y in equation (5)

(

)

(

G j C j L

)

L

j LC j R s

L j C j G C j L j R

ω ω ω

ω γ

ω ω ω

ω

+ +

   

+ +

=

+ +

   

 

+ + =

1 )

(

1

2 2

(3)

Fig.2.Bode Diagram for Transfer Function.

Frequency Shift Technique

Model order diminution is a procedure in which huge number of poles and zeros in a circuit and minimizes it to a smaller description composed of dominant poles shown in fig 3

) , ( ) , ( ) , ( 2 2 s x F s x KV s x x v

M + =

∂ ∂ (6) ) , ( ) , ( ) , (

2 xs KI xs G xs

x I

M + =

∂ ∂

(7)

After solving above equations, we can write the above equation ) , ( ) , ( ) , ( 2 2 s x M F s x V M K s x x v = + ∂ ∂ (8) ) , ( ) , ( ) , ( 2 2 s x M G s x I M K s x x I = + ∂ ∂ (9) 2 γ − = M K

Where K is the kth order of m, substituting the value of the ration K/M in equations (8) and (9)

) , ( ) , ( 2 2 2 s x M F s x V x v = − ∂ ∂ γ (10) ) , ( ) , ( ) , ( 2 2 2 s x M G s x I s x x I = − ∂ ∂ γ (11)

Now solving equations (10) and (11)

) , ( ) , ( ) , ( ) , ( ) , ( ) , ( ) , ( ) , ( 2 2 2 2 s x V s x M G s x I s x M F s x V s x x I s x I s x x v − = ∂ ∂ − ∂ ∂ ) , ( ) , ( ) , ( ) , ( ) , ( ) , ( ) , ( ) , ( 2 2 2 2 s x V s x M G s x V s x x I s x I s x M F s x I s x x v − ∂ ∂ = − ∂ ∂       − ∂ ∂       − ∂ ∂ = ) , ( ) , ( ) , ( ) , ( ) , ( ) , ( 2 2 2 2 s x M G s x x I s x M F s x x v s x I s x I (12) We calculate current to find out the power on VLSI chip

because there is so many leakage current such as reverse leakage current, subthresold leakage current etc.

)

,

(

)

,

(

x

s

V

x

s

I

=

(13) Where

=response dependence condensation

Selection of Frequency Shift Value

The frequency shift technique has two functions:

• Accelerating the convergence and

• Making the reduced model close to the original model within any given frequency range.

For the first case, the frequency shift value is 0≤q≤λ1

Where the λ

1 is the lowest eigenvalue of the original

model. The frequency shift value in the second case can be found as

2

2 max 2 min

ω

ω

+

=

q

Where

ω

min and

ω

max are the lower and upper boundary.

3.

A

Fourier

Series-Based

RLCG

Interconnect Model for Periodic Signals

In RF circuit reproduction Fourier exploration has been widely used named as harmonic balance [15]. In this paper, in digital integrated circuit Fourier series exploration is implemented to model the behavior.

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Fig.3.Equivalent Model of RLCG Circuit

From the ABCD parameters [5] of a transmission line, the transfer function from Vin to the far end of a line is

θ θ ( )sinh cosh

) 1

(

1 )

(

s C z s

GC R s

H

l c Z G R l

d c

d +

+ +

=

(14)

Fig.4.Equivalent Circuit Model of a Distributed RLCG

From this above circuit we have to find out output of the circuit

(

sC

sG

)

Z

1

=

+

(

sR

sL

)

Z

2

=

+

Now out of the circuit Zo is

sL

sR

sG

sC

Z

o

+

+

=

Where s is comlpex frequency,we explain a transfer fuction to a infinite series in order to get a inverse laplace solution.From equation (16), by this transfuction we have to calculate bodeplot, nyquist plot,polar plot and step function shown in below.

Fig.5.Nyquistplot for Transfunction of equation(16)

Fig.6.Step-Response for Transfunction of equation(16)

The input signal of periodic signal can be expressed without changing the parameters of transfer function (24)

4. Simulation Results

In this paper we are using the value of parameters R, L, C and G using 90 nm technology. So the exact values of the parameter R, L and C using 90 nm technologies [1] are given in Table I. We take an example of full wave linear circuit with an assumption that the capacitors and inductors are initially charged with unit voltage and unit current.

Table I: RLC Parameters of a Minimum Sized Wire in a 90 nm Technology

Parameter(s) Value/mm

Resistance (R) 13Ω/mm

Inductance (L) 0.16nH/mm

Capacitance (C) 0.45pF/mm

Conductance (G) 0.27pS/mm

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by considering the derivatives of the linear network. The response of the network is calculated using the model order reduction technique i.e. Frequency Shift Technique. This result is shown in Fig. 7. It is also observed that the accuracy of the response increases as the number of derivatives is increased analytically.

Fig.7. Response of Reduced Model

=

250×

250

In Fig. 8, the transfer function of some existing models [12], [13], [16] are compared with the exact transfer function described in equation (16). The driver resistance and load capacitance are RD = 25Ω and CL = 50fF. Fig.8

shows that two pole model can be accurate up to mid frequency range and non-uniform two stage L–type lumped model and a four pole model increase the accuracy range for higher frequency range. We have implemented the proposed model using Model Order Reduction technique and applied it to widely used actual interconnect RLCG networks as shown in Fig. 9.

For each RLCG network source we put a driver, where the driver is a step voltage source followed by a resistor. We generate resistance, capacitance, inductance and conductance values in such way that the resulting circuit has widely varying time-constant and compare the results obtained by SPICE with that obtained by our methods.

Fig. 8. The Amplitude Transfer Function of Different Models of an RLC Interconnect.

Fig. 9. An RLCG Interconnection Tree Example

Only one aggressor is considered and the multi-aggressor problem can be solved by applying superposition. The maximum crosstalk noise determined by the Fourier series-based model is compared with SPICE in Table II. In the experiments, line 1 is the aggressor, and all of the other lines are quiet victims.

Table II: Comparison of the Maximum Crosstalk Noise Voltage obtained from Proposed Model with SPICE

RD1

(Ω) CL

(fF)

Victim-1 Victim-2 SPICE

Values (mV)

Proposed Model Values (mV)

SPICE Values (mV)

Proposed Model Values (mV)

25 50 48 53 43 47

25 75 68 83 59 67

50 50 91 104 87 89

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Fig. 10 and Fig.11 discuss the graphical comparison of the maximum crosstalk noise voltage values obtained from proposed model with SPICE values for victim-1 and victim-2 interconnect lines.

Fig. 10. : Comparison of the Maximum Crosstalk Noise Voltage obtained from Proposed Model with SPICE for Victim-1

Fig. 11. : Comparison of the Maximum Crosstalk Noise Voltage obtained from Proposed Model with SPICE for Victim-2

The response of the original circuit was computed using the model order reduction. As a sample of results, comparison with the output across one of the nodes, obtained from the original system which is shown in Fig. 12 and as seen both the responses follow each other exactly.

Fig.12. Transient Response Comparison

5. Conclusion

The proposed method can be extended to different operating frequencies by incorporating digitally tunable matching capacitances. Hence we explored VLSI interconnect based on frequency shift technique by which a new model order technique is proposed. The proposed method relies on the poles and residues of a transfer function whether exact or approximate and can thus be used in any kind of model order reduction technique. Simulation results show that the technique gives almost all same results as original circuit, while the stability of the original system preserved. Hence, by manipulating a Fourier series representation of typical on-chip signal, an scientific time-domain solution for an RLCG annex is shown to be an effective modeling strategy. We conclude that the exploration can be done in s-domain using algebraic formula, instead of improper integration in the time domain.

References

[1] Ram Achar, M.S. Nakhala, “Simulation of High-Speed Interconnects” Proceedings of IEEE, Vol. 89, No. 5, May 2001, pp. 693-728.

[2] Roni.K, M.S.Nakhla,“Analysis of High-Speed Interconnects in the Presence Of Electromagnetic Interference “In Proceedings of IEEE Trans. On Microwave Theory and Tech., Vol. 46, No. 7, July 1998, pp. 940-947.

[3] Y.Shin, T.Sakurai “Power Distribution Analysis of VLSI Interconnects Using Model Order Reduction” IEEE Trans. On CAD, Vol. 21, No. 6, June 2002, pp. 739-745

[4] Ram Achar et al., “Passive Interconnect Reduction Algorithm for Distributed/Measured Networks” IEEE Trans. On CAS-II, Vol. 47, No. 4, April 2000, pp. 287-301.

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[6] Mike Chou, Jacob K. White, “Efficient Formulation and Model-Order Reduction for the Transient Simulation of Three-Dimensional VLSI Interconnect “In Proceedings of IEEE Trans. on CAD, Vol. 16, No. 12, December 1997, pp. 1454-1476.

[7] Eli.C, M.S.Nakhla, “Analysis of Interconnect Networks Using Complex Frequency Hopping (CFH)”In Proceedings of IEEE Trans. on CAD, Vol.14, No. 2, February 1995, pp. 186-200.

[8] Stefano. G.T, Andrea Ubolli “On the Generation of Large Passive Macro models for Complex Interconnect Structures” In Proceedings of IEEE Trans. On Adv.Packaging, Vol. 29, No. 1, February 2006, pp. 39-54.

[9] J.V.R.Ravindra, M.B.Srinivas, “A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects”,10th EUROMICRO CONFERENCE on DSD 2007, August 27 - 31, 2007, Lubeck in Germany (Paper Accepted). [10] Zu-Qing Qu, “Model Order Reduction Techniques with

Applications in Finite Element Analysis: With Applications in Finite Element Analysis”, Spinger Verlag London Limited, 2004.

[11] J. A. Davis and J. D. Meindl, “Compact Distributed RLC Interconnect models–Part I: Single Line Transient, Time Delay, and Overshoot Expressions,” IEEE Transactions on Electron Devices, Vol. 47, No. 11, pp. 2068–2077, November 2000.

[12] A. B. Kahng and S. Muddu, “An Analytical Delay Model for RLC Interconnects,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 12, pp. 1507–1514, December 1997.

[13] K. Banerjee and A. Mehrotra, “Accurate Analysis of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling,” Proceedings of the IEEE Symposium on VLSI Circuits, pp.195–198, June 2001.

[14] K. S. Kundert, “Introduction to RF Simulation and Its Application,”IEEE Journal of Solid-State Circuits, Vol. 34, No. 9, pp. 1298–1319,September 1999.

[15] L. N. Dworsky, Modern Transmission Line Theory and Applications, John Wiley & Sons, NY, 1979.

[16] A. B. Kahng and S. Muddu, “Optimal Equivalent Circuits for Interconnect Delay Calculations Using Moments,” Proceedings of the European

[17] Design Automation Conference, pp. 164–169, September 1994.

[18] K. T. Tang and E. G. Friedman, “Lumped Versus Distributed RC and RLC Interconnect Impedance,” Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 136–139, August 2000. [19] L. Yin and L. He, “An Efficient Analytical Model of

Coupled On-Chip RLC Interconnects,” Proceedings of the IEEE Design Automation Conference – Asian and South Pacific, pp. 385–390, January 2001.

[20] Y. Ismail, E. G. Friedman, and J. L. Neves, “Equivalent Elmore Delay for RLC Trees,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 1, pp. 83–97, January 2000.

[21] L. T. Pillage and R. A. Rohrer, “Asymptotic Waveform Evaluation for Timing Analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 4, pp. 352–366, April 1990. [22] S. Lin and E. Kuh, “Transient Simulation of Lossy

Interconnects Based on the Recursive Convolution Formulation,” IEEE Transactions on Circuits and System, Vol. 39, No. 11, pp. 879–892, November 1992.

[23] F. Romeo and M. Santomauro, “Time-Domain Simulation of N Coupled Transmission Lines,” IEEE Transactions on Microwave Theory and Technology, Vol. 35, No. 2, pp. 131–137, February 1987.

[24] J. Chen and L. He, “A Decoupling Method for Analysis of CoupledRLC Interconnects,” Proceedings of the ACM Great Lakes Symposiumon VLSI, pp. 41– 46.

Author Profile:

Pratiksha Singh Gaur passed B.Tech degree in Electronics and Communication engineering form college of science, and engineering Jhansi, U.P, Uttar Pradesh technical university luck now. She has published 5 papers in International Journal and publishes 3 papers in national seminar. She has completed M.Tech from Amity University, Gwalior.

Figure

Fig.3.Equivalent Model of RLCG Circuit
Fig. 8. The Amplitude Transfer Function of Different Models of an RLC Interconnect.
Fig. 10 and Fig.11 discuss the graphical comparison of the maximum crosstalk noise voltage values obtained  from proposed model with SPICE values for victim-1 and victim-2 interconnect lines

References

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