Virtual Memory and Address Translation

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Virtual Memory and

Address Translation

1

Review

Program addresses are virtual addresses.

¾ Relative offset of program regions can not change during program execution. E.g., heap can not move further from code.g p

¾ Virtual addresses == physical address inconvenient. ™ Program location is compiled into the program.

A single offset register allows the OS to place a process’ virtual address space anywhere in physical memory.

¾ Virtual address space must be smaller than physical.

¾ Program is swapped out of old location and swapped into new. Segmentation creates external fragmentation and requires large

2

g g q g

regions of contiguous physical memory.

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Virtual Memory

Concept

Key problem: How can one support programs that require more memory than is physically available?

¾ How can we support programs that do not use all of their memory at once?

2

n

-1

Hide physical size of memory from users

¾ Memory is a “large” virtual address spaceof 2n bytes

¾ Only portions of VAS are in physical memory at any one time (increase memory utilization).

Issues

¾ Placement strategies

™ Where to place programs in physical memory

Program

P

’s

VAS

3 ¾ Replacement strategies

™ What to do when there exist more processes than can fit in memory

¾ Load control strategies

™ Determining how many processes can be in memory at one time

0

Realizing Virtual Memory

Paging

Physical memory partitioned into equal sized

page frames

¾ Page frames avoid external fragmentation.

(fMAX-1,oMAX-1) g g (f,o)

o

Physical

Memory

A memory address is a pair (f, o) f — frame number (fmaxframes)

o — frame offset (omax bytes/frames) Physical address = omax×f +o

4 (0,0)

PA:

f

o

f

1 log2omax log2(fmax ×omax)

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Physical Address Specifications

Frame/Offset pair v. An absolute index

Example: A 16-bit address space with (omax=) 512 byte page frames

¾ Addressing location (3, 6) = 1,542 (3,6) 1,542

0

1 9

PA:

16 (3,6)

f

o

Physical

Memory

1

1

1

0

0

0

0

0

0 1

0

0

0

0

0

3

6

10 1,542 5 (0,0)

f

1,542

0

Questions

The offset is the same in a virtual address and a

physical address.

¾A T ¾A. True ¾B. False

If your level 1 data cache is equal to or smaller than

2

number of page offset

bits then address translation is not

necessary for a data cache tag check.

¾A. True ¾B False

6 ¾B. False

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Realizing Virtual Memory

Paging

A process’s virtual address space is partitioned into equal sized pages

¾ page = page frame

2n-1 = (pMAX-1,oMAX-1)

¾ page = page frame

(p,o)

o

Virtual

Address

Space

A virtual address is a pair (p, o) p — page number (pmaxpages) o — page offset (omaxbytes/pages)

Virtual address = omax×p +o

7 (0,0)

p

o

p

VA:

1 log2oMAX

log2(pmax×omax)

Paging

Mapping virtual addresses to physical addresses

Pagesmap to frames

Pages are contiguous in a VAS...

¾ But pages are arbitrarily located

i h i l d

Virtual

in physical memory, and

¾ Not all pages mapped at all times

Virtual

Address

Space

(p2,o2)

Physical

Memory

(f1,o1) 8 (p1,o1) (f2,o2)

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Frames and pages

Only mapping virtual pages that are in use does

what?

¾A. Increases memory utilization. ¾A. Increases memory utilization.

¾B. Increases performance for user applications. ¾C. Allows an OS to run more programs concurrently.

¾D. Gives the OS freedom to move virtual pages in the virtual address space.

Address translation is

¾A. Frequent

9 ¾B. Infrequent

Changing address mappings is

¾A. Frequent ¾B. Infrequent

Paging

Virtual address translation

A page tablemaps virtual

pages to physical frames (f,o)

Program P CPU P’s Virtual Address Space Physical Memory 1 20 109 p o 1 16109 f o Virtual Add 10 Page Table (p,o)

p

Physical Addresses Addresses

f

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Virtual Address Translation Details

Page table structure

Contents:

¾ Flags — dirty bit, resident bit, clock/reference bit

¾ Frame number 1 table per process

Part of process’s state

1 20 109 p o 1 16109 f o Virtual CPU 11 1 0 Page Table

p

Physical Addresses Addresses

f

0 PTBR +

Virtual Address Translation Details

Example

A system with 16-bit addresses ¾ 32 KB of physical memory ¾ 1024 byte pages (4,1023) (4,0) CPU Physical Memory 15 p o 14 109 f o Physical Addresses Virtual Add P’s Virtual Address Space (3,1023) (4,0) 0 0 10 9 12 1 1 0 0 1 0 0 Page Table Addresses 0 0 0 0 0 0 0 (0,0) 1 0

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Virtual Address Translation

Performance Issues

Problem — VM reference requires 2 memory references!

¾ One access to get the page table entry

¾ One access to get the data

Page table can be very large; a part of the page table can be on disk.

¾ For a machine with 64-bit addresses and 1024 byte pages, what is the size of a page table?

What to do?

¾ Most computing problems are solved by some form of…

13 ™ Caching

™ Indirection

Virtual Address Translation

Using TLBs to Speedup Address Translation

Cache recently accessed page-to-frame translations in a TLB ¾ For TLB hit, physical page number obtained in 1 cycle

¾ For TLB miss, translation is updated in TLB

¾ Has high hit ratio (why?)

f 1 20 109 p o 1 16109 f o Physical Addresses Virtual Addresses CPU Key Value ? 14 Page Table TLB f Key Value p p f

X

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Dealing With Large Page Tables

Multi-level paging

Add additional levels of indirection to the page table by sub-dividing page number into kparts

¾ Create a “tree” of page tables

¾ TLB still used, just not shown Second-Level Page Tables

¾ The architecture determines the number of levels of page table

p

2

o

Virtual Address

p

3 Page Tables

p

1

p

2 15 Third-Level Page Tables First-Level Page Table

p

1

p

3

Dealing With Large Page Tables

Multi-level paging

Example: Two-level paging

CPU Memory 1 20 16 10

p

1

o

1 16 10

f

o

Physical Addresses Virtual Addresses CPU

p

2 Memory 16 Second-Level Page Table First-Level Page Table page table

p

2 f

p

1 PTBR + +

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The Problem of Large Address Spaces

With large address spaces (64-bits) forward mapped page tables become cumbersome.

¾ E.g. 5 levels of tables.g

Instead of making tables proportional to size of virtual address space, make them proportional to the size of physical address space.

¾ Virtual address space is growing faster than physical.

Use one entry for each physical page with a hash table

17 Use one entry for each physical page with a hash table

¾ Size of translation table occupies a very small fraction of physical memory

¾ Size of translation table is independent of VM size

Virtual Address Translation

Using Page Registers (aka Inverted Page Tables)

Each frame is associated with a register containing

¾ Residence bit: whether or not the frame is occupied

¾ Occupier: page number of the page occupying frame

¾ Occupier: page number of the page occupying frame

¾ Protection bits

Page registers: an example

¾ Physical memory size: 16 MB

¾ Page size: 4096 bytes

¾ Number of frames: 4096

¾ Space used for page registers (assuming 8 bytes/register): 32

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¾ Space used for page registers (assuming 8 bytes/register): 32 Kbytes

¾ Percentage overhead introduced by page registers: 0.2%

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Page Registers

How does a virtual address become a physical address?

CPU generates virtual addresses, where is the

physical page?

¾H h th i t l dd ¾Hash the virtual address ¾Must deal with conflicts

TLB caches recent translations, so page lookup can

take several steps

¾Hash the address

¾Check the tag of the entry

¾Possibly rehash/traverse list of conflicting entries

19 ¾Possibly rehash/traverse list of conflicting entries

TLB is limited in size

¾Difficult to make large and accessible in a single cycle. ¾They consume a lot of power (27% of on-chip for

StrongARM)

Dealing With Large Inverted Page Tables

Using Hash Tables

Hash page numbers to find corresponding frame number

¾ Page frame number is not explicitly stored (1 frame per entry)

¾ Protection, dirty, used, resident bits also in entry

1 20 9 p o 1 16 9 f o Physical Addresses Virtual Address CPU Hash Memory g running PID =? =? =?=? tag check 20

h

(

PID

,

p

)

PTBR

PID

Inverted Page Table 1 0

page

0 fmax– 1 fmax– 2 + 1

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Searching Inverted Page Tables

Using Hash Tables

Page registers are placed in an array

Page

i

is placed in slot

f(i) where f

is an agreed-upon

hash function

To lookup page

i

, perform the following

:

¾Compute f(i)and use it as an index into the table of page registers

21 ¾Extract the corresponding page register

¾Check if the register tag contains i,if so, we have a hit ¾Otherwise, we have a miss

Searching the Inverted Page Table

Using Hash Tables (Cont’d.)

Minor complication

¾ Since the number of pages is usually larger than the number of slots in a hash table, two or more items mayhash to the same l ti

location

Two different entries that map to same location are said to collide

Many standard techniques for dealing with collisions

¾ Use a linked list of items that hash to a particular table entry

¾ Rehash index until the key is found or an empty table entry is

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¾ Rehash index until the key is found or an empty table entry is reached (open hashing)

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Questions

Why use inverted page tables?

¾A. Forward mapped page tables are too slow.

¾B F d d t bl d ’t l t l i t l

¾B. Forward mapped page tables don’t scale to larger virtual address spaces.

¾C. Inverted pages tables have a simpler lookup algorithm, so the hardware that implements them is simpler.

¾D. Inverted page tables allow a virtual page to be anywhere in physical memory.

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Virtual Memory (Paging)

The bigger picture

A process’s VAS is its context ¾ Contains its code, data, and stack

Code pages are stored in a user’s file on disk

Code Data Stack Code pages are stored in a user s file on disk

¾ Some are currently residing in memory; most are not

Data and stack pages are also stored in a file ¾ Although this file is typically not visible to users

¾ File only exists while a program is executing

OS determines which portions of a process’s VAS

d i t ti

File System (Disk)

24 are mapped in memory at any one time

OS/MMU

Physical Memory

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Virtual Memory

Page fault handling

References to non-mapped pages generate a page fault CPU Physical Memory P CPU Page Table 0

OS resumes/initiates some other process Read of page completes

Page fault handling steps:

Processor runs the interrupt handler OS blocks the running process OS starts read of the unmapped page

25 Program

P’s VAS

Disk OS maps the missing page into memory

OS restart the faulting process

Virtual Memory Performance

Page fault handling analysis

To understand the overhead of paging, compute the effective memory access time(EAT)

¾ EAT = memory access time×probability of a page hit + page fault service time×probability of a page fault

Example:

¾ Memory access time: 60 ns

¾ Disk access time: 25 ms

¾ Let p= the probability of a page fault

¾ EAT =60(1–p) +25,000,000p

26

( p) , , p

To realize an EAT within 5% of minimum, what is the largest value of pwe can tolerate?

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Vista reading from the pagefile

27

Vista writing to the pagefile

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Virtual Memory

Summary

Physical and virtual memory partitioned into equal

size units

Size of VAS unrelated to size of physical memory

Virtual

pages

are mapped to physical

frames

Simple placement strategy

There is no external fragmentation

29

g

Key to good performance is minimizing page faults

Segmentation vs. Paging

Segmentation has what advantages over paging?

¾A. Fine-grained protection.

¾B E i t t f f t t /f th di k

¾B. Easier to manage transfer of segments to/from the disk. ¾C. Requires less hardware support

¾D. No external fragmentation

Paging has what advantages over segmentation?

¾A. Fine-grained protection.

¾B. Easier to manage transfer of pages to/from the disk. ¾C Requires less hardware support

30 ¾C. Requires less hardware support.

Figure

Updating...

References

Related subjects : Near-Memory Address Translation