Note: Within nine months of the publication of the mention of the grant of the European patent in the European Patent Bulletin, any person may give notice to the European Patent Office of opposition to that patent, in accordance with the
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EUROPEAN PATENT SPECIFICATION
(45) Date of publication and mention of the grant of the patent:
26.11.2014 Bulletin 2014/48
(21) Application number: 08744214.1
(22) Date of filing: 21.03.2008
(51) Int Cl.:
G11C 5/14(2006.01) G11C 7/10(2006.01) (86) International application number:
PCT/US2008/057920
(87) International publication number:
WO 2008/118816 (02.10.2008 Gazette 2008/40)
(54) PROGRESSIVE POWER CONTROL OF A MULTI-PORT MEMORY DEVICE
PROGRESSIVE LEISTUNGSSTEUERUNG EINER SPEICHERVORRICHTUNG MIT MEHREREN ANSCHLÜSSEN
CONTRÔLE D’ÉNERGIE PROGRESSIF D’UN DISPOSITIF DE MÉMOIRE À PORTS MULTIPLES (84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR
(30) Priority: 23.03.2007 US 690642
(43) Date of publication of application:
23.12.2009 Bulletin 2009/52
(73) Proprietor: Silicon Image, Inc. Sunnyvale, CA 94085 (US)
(72) Inventors:
• KIM, Sungjoon
Cupertino, CA 95014 (US)
• LEE, Dongyun
San Jose, CA 95129 (US) • KIM, Edward
Palo Alto, CA (US)
(74) Representative: Viering, Jentschura & Partner Patent- und Rechtsanwälte
Am Brauhaus 8 01099 Dresden (DE) (56) References cited: EP-A2- 0 490 679 EP-A2- 1 220 226 US-A- 5 987 614 US-A1- 2002 104 031 US-A1- 2003 120 896 US-A1- 2004 107 307 US-A1- 2004 141 404 US-B1- 6 560 160
5 10 15 20 25 30 35 40 45 50 55 Description BACKGROUND
[0001] The communications links across which com-puters-or parts of computers-talk to one another may be either serial or parallel. A parallel link transmits several streams of data (perhaps representing particular bits of a stream of bytes) along multiple channels (wires, printed circuit tracks, optical fibers, etc.), while a serial link trans-mits a single stream of data over only two wires (a positive and complementary signal). At first sight it would seem that a serial link must be inferior to a parallel one, because it can transmit less data on each clock tick. However, it is often the case that serial links can be clocked consid-erably faster than parallel links and can achieve a higher data rate. A number of factors allow serial links to be clocked at a greater rate. First, clock skew between dif-ferent channels is not an issue (for un-clocked serial links). Second, a serial connection requires fewer inter-connecting cables (e.g. wires/fibers) and hence occupies less space hallowing for better isolation of the channel from its surroundings. Finally, crosstalk is less of an issue because there are fewer conductors in proximity. In many cases, serial links are a better option because they are less expensive to implement. Many integrated circuits (ICs) have serial interfaces, as opposed to parallel ones, so that they have fewer pins and are therefore more eco-nomical.
[0002] Despite their advantages, serial links tend to use more power than parallel links. In particular, when transmitting or receiving data, a serial link changes states very rapidly (called toggling). A small amount of power is consumed by each state change, thereby adding up to large power consumption over time. Serial links are also typically terminated on each end by a termination resistor and bias resistors. Without termination resistors, reflections of fast driver edges can cause multiple data edges that can cause data corruption. Termination resis-tors also reduce electrical noise sensitivity due to the lower impedance. The bias resistors bias the lines apart when the lines are not being driven. Without biasing re-sistors, the signal falls to zero (where electrical noise sensitivity is greatest) when no data is being transmitted. Both termination and bias resistors are therefore neces-sary; however, the additional resistance causes the link to consume a constant amount of power to keep the link alive.
[0003] Consumers demand higher and higher speeds from electronic devices, but the higher the speed of the device the more power the device consumes. This is par-ticularly a problem for mobile devices that have limited power available through on-board batteries. To provide the most benefit, these devices must have a long battery life while still providing consumers with a high degree of functionality. Previous attempts at power reduction have attempted to power down the device or place it into a lower power state when it is not in use, and then rapidly
return it to full power when the user of the device wants to perform a function. However, this technique is not ef-fective when a device is frequently in use and can still result in significant power being consumed.
[0004] European Patent Application Publication No. EP1220226 A2 of Fujitsu Limited, entitled "Multi-Port Memory Based on DRAM Core", regards a semiconduc-tor memory device including a plurality of external ports receiving commands, including a cell array comprised of dynamic-type memory cells, where a refresh command may be internally generated when a port is deactivated.
[0005] European Patent Application Publication No. EP0490679 A2 of SGS-Thomson Microelectronics, Inc, entitled "A Semiconductor Memory With Separate Time-out Control for Read and Write Operations", regards sem-iconductor memory circuits having time-out control for certain circuitry, the control circuit including delay stages of different lengths, a shorter delay stage to define the time-out for a read operation and a longer delay stage to define the time-out for a write operation.
[0006] According to the present invention, there is pro-vided a method of progressively reducing power con-sumption according to claim 1 and a power control sys-tem according to claim 9.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007]
Figure 1 is a circuit diagram illustrating the compo-nents of a power control system in a serial port mem-ory device.
Figure 2 is a state machine that illustrates the states of a single port of the serial port memory device. Figure 3 is a state machine that illustrates the states of a host attached to a single port of the serial port memory device.
Figure 4 is a state diagram illustrating the power-down modes available to each bank of the serial port memory device.
Figure 5 is a circuit diagram that illustrates the ter-mination of a serial link attached to a port.
DETAILED DESCRIPTION
[0008] A method and system for progressively reduc-ing the power consumption of a serial memory device is provided (the "power control system"). A multi-port serial memory device is described in U.S. Patent Application No. 10/045,297, entitled "COMMUNICATlONS ARCHI-TECTURE FOR MEMORY-BASED DEVICES," (Attor-ney Docket No. 54972.8812.US00). The power control system configures the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port
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basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consump-tion of the overall serial port memory is significantly re-duced. Each port may be connected to a different host that accesses the device. Because ports can be shut down individually, hosts may still access the serial mem-ory to perform certain functions using some ports while other ports are in a low-power state. In this way, the power control system reduces the power consumption of a de-vice progressively, while still making the functionality of the device available for certain accessing hosts.
[0009] In some embodiments, the power control sys-tem detects that a port is not in use based on a shut-off criteria (e.g., the activity of the port). For example, if the port is not transmitting or receiving, then the power con-trol system will shut the port down. The power concon-trol system may wait for the expiration of a timeout based on the last time that data was received by the port to deter-mine that the port is not active. The power control system may also receive a command from the host that indicates that no new data will be transmitted for a period, and the power control system may shut down the port in response to the command.
[0010] In some embodiments, the power control sys-tem removes the port clock signal and power for a shut down port. The port clock switches rapidly and consumes power that is not needed when the port is not in use. By removing the port clock and power to a port, the power control system further reduces power consumption. When the port is needed again, the power and the clock signal can be reapplied and the port returned to an op-erational state. For example, when powered down the power control system may detect a change in the signal state on the line that indicates that the port is needed again by a host. Upon detecting the change in signal state, the power control system powers the port back up by reversing the steps taken to power the port down.
[0011] In some embodiments, if all ports are shut down, then the power control system lowers the core power including the clock generator and PLL to further reduce power consumption. The core power supplies each of the ports as well as common support circuitry. By remov-ing the core power, the power control system achieves additional power savings. Since the clock generator and PLL can often consume a significant amount of power required by a circuit, shutting down the clock generator and PLL can result in significant power savings.
[0012] In some embodiments, the power control sys-tem shuts down ports by removing termination at the port. The port is placed into common mode so that the voltage of the positive and complementary signals is the same. Removing the termination reduces power consumed. Moreover, neither the host nor the memory device is transmitting when a port is shut down, so both the host and memory device save power.
[0013] Figure 1 is a circuit diagram illustrating the com-ponents of the power control system and the serial mem-ory device in one embodiment. The serial memmem-ory device contains a phase-locked loop (PLL) 105, multiple banks of memory 110 and 115, four ports 120, 125, 130, and 135, a clock line 140 for each port, and a power line 155 for each port. The multiple banks of memory 110 and 115 are coupled to the four serial ports 120, 125, 130, and 135, thereby making the banks of memory accessible by one or more host devices that are connected to the ports. While the memory device is depicted as having only eight banks in two groups of four and four ports in Figure 1, the memory device may have any number of banks and ports. The number of banks and ports are typically de-termined by the number of accessing hosts and the par-ticular application for which the memory device is being used. The power control system comprises an activity detection line 145, a clock switch 170, and a power switch 175 for each port, as well as power control logic 160, and a core power control module 165. The activity detection line 145 for each port is coupled to the clock switch 170, the power switch 175, and the power control logic 160. In some embodiments, the power control logic performs a logical AND operation on the activity detection line from each of the ports. The output from the power control logic 160 is coupled to the power control module 165. While Figure 1 depicts a certain switch configuration and power control logic, it will be appreciated that other configura-tions and construcconfigura-tions may perform similar funcconfigura-tions to achieve the same result. For example, the power control logic may be implemented in software rather than in hard-ware, and the control signals used to trigger the power switch and the clock switch may be received from a cen-tral controller. As another example, the power control log-ic may be more complex depending on the number of ports that are contained in the memory device.
[0014] A variety of power-saving techniques are imple-mented by the power control system in order to minimize the power consumption of the serial memory device. An activity detection line 145 is coupled to each port of the memory device, and carries a signal indicating when the port is active and when the port is inactive. The signal on the activity detection line is used to trigger various power-saving modes. For example, when the signal on the ac-tivity detection line indicates that a port is inactive, the power on power line 155 is disconnected from the port by switching off the power switch 175. Removing power from the port reduces the power consumption of the memory device. As another example, when a port is in-active the clock signal on clock line 140 is disabled for the port by switching off the clock switch 170. Shutting down the clock for the port reduces toggling and associ-ated power consumption. As still another example, if power control logic 160 detects from the signal on the activity detection lines that all of the device ports are in-active, the power control logic signals the core power control module 165. Upon receiving the signal that all ports are inactive, the core power control module may
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further reduce power consumption by shutting down the core clock (not shown) and power to the PLL 105. Re-moving the clock signal and power to each port, or shut-ting down the core clock and power to the PLL, may be done immediately after a port is detected to be inactive, or after the expiration of a timeout period. The timeout period may vary in length for each port, for all ports, based on the application in which the memory device is being used, etc.
[0015] Figure 2 is a state machine that illustrates the states of a single port of a serial port memory device. When the port is first activated, the port is in a system reset state 205. The port then moves to a link reset state 210. As long as no data signal is being received on the port, the port remains in this state. In the link reset state 210, the port is not driven, and the voltage of the positive and complementary lines is the same due to termination. In order to minimize power, the clock and power to the port may also be removed as described above. When a signal is received on the port, the port moves to a frame search state 215. If the power and/or clock to the port are off when a signal is received, then the power and/or clock are turned back on. In the frame search state 215, the port is driven and the positive and complementary lines carry complementary signals. The port waits for a SYNC message from the host and transmits a SYNC2 message to the host. If the port stops receiving a signal, the port returns to the link reset state 210. If a SYNC message is detected from the host, then the port moves to an operational mode state 220. In the operational mode state 220, data is sent and received from the host. If the port stops receiving data, then the port can be powered down and returns to the link reset state 210. If any errors are detected during transmission, the port returns to the frame search state 215 to resynchronize with the host.
[0016] Figure 3 is a state machine that illustrates the states of a host attached to a single port of a serial port memory device. When the host is first activated, the host is in a system reset state 305. The host then moves to a link reset state 310. As long as nothing is being sent, the host remains in this state. In the link reset state 310, the link is not terminated, and the voltage of the positive and complementary lines is the same (i.e., the lines are in squelch mode). When the host wants to send additional data, the host moves to a frame search state 315. In the frame search state 315, the link is terminated and the positive and complementary lines carry complementary signals. The host waits for a SYNC2 message from the port and transmits a SYNC message to the port. If the host decides to disable the link (e.g., by a timeout expiring or error parity), then the host returns to the link reset state 310. If a SYNC message is detected from the port, then the host moves to an operational mode state 320, else if a SYNC2 message is received, then the host waits for a SYNC message from the port. In the operational mode state 320, data is sent and received to the port. If at any point the host detects that the port is disabled, then the link can be powered down and the host returns to the link
reset state 310. If any errors are detected during trans-mission, the host also returns to the link reset state 310 to resynchronize with the port.
[0017] In some embodiments, the serial port memory may implement additional power saving modes at the bank level. For example, it is not necessary to refresh banks with no data in them. Refreshing banks consumes power, so avoiding a refresh of a bank saves power. In some embodiments, the serial port memory has four power-down modes, described as follows.
• Self-refresh - To enter the self-refresh mode, all ports are set by the power control system to idle state with no banks active. The PLL 105 is stopped, and the external : reference clock (not shown) may be stopped. All other clocks are gated off to save power. All peripheral circuitry is disabled to save power as well. All banks are precharged before entering this mode. The core provides its own refresh timing, so this mode can be sustained indefinitely. The refer-ence clock should be stable before exiting this mode. Links are retrained after exiting this mode.
• Precharge Power Down - To enter the precharge power down mode, all ports are set by the power control system to idle state with no banks active. The PLL 105 is stopped, and the reference clock (not shown) may be stopped. All other clocks are gated off to save power. All peripheral circuitry is disabled to save power as well. All banks are precharged be-fore entering this mode. No other operations are per-formed, so this mode should be exited before the next refresh cycle. The reference clock should be stable before exiting this mode. Links are retrained after exiting this mode.
• Active Power Down - To enter the active power down mode, all ports are set by the power control system to idle state with some banks active. The PLL 105 continues to run, and the reference clock remains stable. All peripheral circuitry is disabled to save power. No other operations are performed, so this mode should be exited before the next refresh cycle. Links are retrained after exiting this mode.
• Idle - When a link enters idle state, that link ceases to use power. The link is retrained when the link is brought back up.
[0018] Figure 4 is a state diagram illustrating the pow-er-down modes available to each bank in some embod-iments. The bank is initially in a power on state 405. The bank then moves to a set all MRS state 410. In the set all MRS state 410 each component is sent a reset indi-cation. The bank then moves to a precharge all state 415. In the precharge all state 415, the dynamic random ac-cess memory (DRAM) that composes the bank is pre-charged. The bank then moves to an idle state 420. If any link is active, then the bank moves to a self-refresh state 425, described above. If all links are inactive, the bank moves to a precharge power down state 430, also
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described above. If a refresh message (REF) is received while in the idle state, then the bank moves from the idle state to an auto refresh state 435 and to a precharge state 470. If an activation message (ACT) is received while in the idle state, then the bank moves from the idle state 420 to an active state 440. From the active state 440, if all links are down, then the bank moves to an active power down state 445, described above. From the active state 440, reads and writes are processed. When a read is received, the bank moves to a read state 455, and/or to a read auto precharge state 465. When a write is received, the bank moves to a write state 450 and/or to a write auto precharge state 460. When the read or write is complete, the bank moves to a precharge state 470, and then back to the idle state 420. The bank con-tinues this cycle until power is removed.
[0019] Figure 5 is a circuit diagram that illustrates the termination of the serial link. The host side of the link contains a termination detector 505, a differential driver 510, a beacon driver 515, and a termination circuit 520. The termination detector 505 detects when termination is in effect on the memory side of the link. The differential driver 510 drives a differential signal over the positive and complementary lines of the serial link. The beacon driver 515 signals the memory side of the link that data is about to be transmitted so that the memory side of the link can engage the termination circuit 560. The memory side of the serial link contains a differential sampler 550, a beacon detector 555, and a termination circuit 560. The differential sampler 550 detects a differential voltage sig-nal on the serial link. The beacon detector 555 detects the beacon signal sent by the beacon driver 515. The termination circuit 560 terminates the link when the link is active. The termination resistor can be off when the link is inactive and on when the link is active.
[0020] The power control system can be used in a va-riety of environments such as memory devices or other environments that use serial memory. The power control system is particularly applicable to low-power applica-tions such as cell phones, digital cameras, and other de-vices where battery life and power consumption are im-portant concerns.
[0021] From the foregoing, it will be appreciated that specific embodiments of the power control system have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
Claims
1. A method of progressively reducing power consump-tion in a multi-port memory device having a plurality of serial ports, the method comprising:
monitoring the transmission and reception of
da-ta on a plurality of serial ports (120-135) in a memory device using separate activity detection lines (145) each coupled to a corresponding se-rial port of the plurality of sese-rial ports;
determining if any serial port of the plurality of serial ports is inactive for data transmission and reception based, at least in part, on the activity detection line for the serial port;
for each of the monitored plurality of serial ports, detecting when a shut-off criteria is satisfied at the serial port, the shut-off criteria including a period of inactivity for data transmission and re-ception at the serial port; and
when the shut-off criteria is satisfied at any serial port of the plurality of serial ports, selectively powering down the each serial port meeting the shut-off criteria without affecting the operation of the plurality of other serial ports of the memory device; and
upon determining that data transmission and re-ception has ceased for all of the plurality of serial ports of the memory device for a threshold pe-riod based, at least in part, on the activity detec-tion lines for the plurality of serial ports, perform-ing one or more of switchperform-ing off core power to the memory device or switching off a clock gen-erator to the memory device.
2. The method of claim 1 wherein powering down the each serial port comprises one or more of removing termination from the serial port, removing the clock signal from the serial port, or removing power from the serial port.
3. The method of claim 1 further comprising:
upon detecting a transmission to any serial port of the plurality of serials ports that has been pow-ered down, powering up the serial port to receive the transmission; and
upon detecting a differential voltage applied to any serial port of the plurality of serials ports that has been powered down, powering up the serial port.
4. The method of claim 1 wherein a clock for operating each of the plurality of serial ports of the memory device is provided by a phased-locked loop.
5. The method of claim 1 wherein each of the plurality of ports is coupled to one of a plurality of memory banks of the memory device.
6. The method of claim 1 wherein the shut-off criteria is further includes a command received from a host, wherein the command indicates that no data will be transferred for a time period.
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7. The method of claim 1 further comprising:
detecting when a power-on criteria is satisfied at any powered down serial port of the plurality of serial ports; and
when the power-on criteria is satisfied at the powered down serial port, selectively powering up the serial port without affecting the operation of the plurality of other serial ports of the memory device.
8. The method of claim 7, wherein the power-on criteria for a serial port includes detection of a change in a signal state on the detection line for the serial port.
9. A power control system for progressively reducing the power consumption of a memory device having a plurality of serial ports, comprising:
power control logic (160) configured to detect the activity of each of a plurality of serial ports (120-135) of the memory device using a sepa-rate activity detection line (145) for each of the serial ports, the power control logic to determine if a shut-off criteria for any of the plurality of serial ports is satisfied based, at least in part, on inac-tivity of the serial port for data transmission and reception for a timeout period;
a port power-down component (170-175) cou-pled to the power control logic and configured to selectively power down each serial port of the memory device based on the shutoff criteria for each serial port; and
a core power control component (165) coupled to the power control logic and configured to pow-er down core circuitry of the spow-erial port memory device in response to detected inactivity in data transmission and reception on all the plurality of serial ports for a threshold time period.
10. The system of claim 9 wherein powering down each serial port comprises removing a termination from the port.
11. The system of claim 9, further comprising a clock line (140) for each serial port to carry a clock signal, wherein the port power-down component for each serial port is a clock switch (170) coupled to the clock line for the serial port, and wherein powering down each serial port comprises removing the clock signal from the serial port.
12. The system of claim 9, further comprising a power line (155) for each serial port to provide power to the serial port, wherein the port power-down component for each serial port is a power switch (175) coupled to the power line for the serial port, and wherein pow-ering down each serial port comprises removing
power from the serial port.
13. The system of claim 9 wherein the core circuitry in-cludes one or more of:
circuitry that provides core power to the memory device; or
a clock generator for the memory device.
14. The system of claim 9 wherein the power control logic is further configured to selectively power up any powered down serial port of the plurality of serial ports of the memory device upon detecting activity on the activity detection line of the serial port.
Patentansprüche
1. Verfahren zum fortschreitenden Reduzieren des En-ergieverbrauchs in einer Speichervorrichtung mit mehreren Ports, wobei das Verfahren aufweist:
Überwachen der Übertragung und des Emp-fangs von Daten auf einer Mehrzahl von seriel-len Ports (120-135) in einer Speichervorrichtung unter Verwendung von separaten Aktivitätsde-tektionsleitungen (145), wobei jede mit einem zugehörigen seriellen Port der Mehrzahl von se-riellen Ports verbunden ist;
Ermitteln, ob irgendein serieller Port der Mehr-zahl von seriellen Ports für eine Datenübertra-gung oder einen Datenempfang inaktiv ist, ba-sierend, zumindest teilweise, auf der Aktivitäts-detektionsleitung für den seriellen Port; für jeden der überwachten seriellen Ports, De-tektieren, wenn ein Abschaltkriterium an dem seriellen Port erfüllt ist, wobei das Abschaltkri-terium eine Inaktivitätsdauer für die Datenüber-tragung und den Datenempfang an dem seriel-len Port aufweist; und
wenn das Ausschaltkriterium für irgendeinen se-riellen Port der Mehrzahl von sese-riellen Ports er-füllt ist, selektives Ausschalten jedes seriellen Ports, der das Abschaltkriterium erfüllt, ohne den Betrieb der Mehrzahl von anderen seriellen Ports der Speichervorrichtung zu beeinflussen; und
wenn ermittelt wird, dass die Datenübertragung und der Datenempfang für alle seriellen Ports der Speichervorrichtung für eine Schwellendau-er aufgehört hat, basiSchwellendau-erend, zumindest teilwei-se, auf den Aktivitätsdetektionsleitungen für die Mehrzahl von seriellen Ports, Durchführen von einem oder mehreren aus Abschalten der Grun-denergiezufuhr zu der Speichervorrichtung oder Abschalten eines Taktgenerators der Speicher-vorrichtung.
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2. Verfahren gemäß Anspruch 1, wobei Ausschalten jedes seriellen Ports ein oder mehreres aus Entfer-nen der Endenabschlusses des seriellen Ports, Ent-fernen des Taktsignals von dem seriellen Port oder Entfernen der Stromversorgung von dem seriellen Port aufweist.
3. Verfahren gemäß Anspruch 1, ferner aufweisend: Bei Detektieren einer Übertragung an irgendei-nen seriellen Port der Mehrzahl von seriellen Ports, der ausgeschaltet wurde, Anschalten des seriellen Ports zum Empfangen der Übertra-gung und
bei Detektieren, dass irgendeinem seriellen Port der Mehrzahl von seriellen Ports, der ausge-schaltet wurde, eine differentielle Spannung zu-geführt wird, Anschalten des seriellen Ports.
4. Verfahren gemäß Anspruch 1, wobei ein Takt zum Betreiben jedes der Mehrzahl von seriellen Ports der Speichervorrichtung von einer Phasenregelschleife bereitgestellt wird.
5. Verfahren gemäß Anspruch 1, wobei jeder der Mehr-zahl von Ports mit einer MehrMehr-zahl von Speicherbän-ken der Speichervorrichtung gekoppelt ist.
6. Verfahren gemäß Anspruch 1, wobei das Abschalt-kriterium ferner einen von einem Host empfangenen Befehl aufweist, wobei der Befehl angibt, dass keine Daten für eine Zeitdauer übertragen werden.
7. Verfahren gemäß Anspruch 1 ferner aufweisend: Detektieren, wenn ein Anschaltkriterium an ir-gendeinem ausgeschalteten seriellen Port der Mehrzahl von seriellen Ports erfüllt ist; und wenn das Anschaltkriterium an dem ausge-schalteten seriellen Port erfüllt ist, selektives An-schalten des seriellen Ports ohne den Betrieb der Mehrzahl von anderen seriellen Ports der Speichervorrichtung zu beeinflussen.
8. Verfahren gemäß Anspruch 7, wobei das Anschalt-kriterium für einen seriellen Port das Detektieren ei-ner Änderung des Signalzustands auf der Detekti-onsleitung für den seriellen Port aufweist.
9. Energiesteuersystem zum fortschreitenden Redu-zieren des Energieverbrauchs einer Speichervor-richtung mit mehreren Ports aufweisend:
eine Energiesteuerlogik (160) eingerichtet zum Detektieren der Aktivität jedes einer Mehrzahl von seriellen Ports (120-135) der Speichervor-richtung unter Verwendung einer separaten Ak-tivitätsdetektionsleitung (145) für jeden der
se-riellen Ports, wobei die Energiesteuerlogik er-mittelt, ob ein Abschaltkriterium für irgendeinen der Mehrzahl von seriellen Ports erfüllt ist, zu-mindest teilweise basierend auf der Inaktivität des seriellen Ports für Datenübertragung und Datenempfang für eine Zeitüberschreitungs-dauer;
eine Port-Ausschaltkomponente (170-175), die mit der Energiesteuerlogik gekoppelt ist und ein-gerichtet ist, jeden seriellen Port der Speicher-vorrichtung basierend auf dem Abschaltkriteri-um für jeden seriellen Port auszuschalten; und eine Grundenergiesteuerkomponente (165), die mit der Energiesteuerlogik gekoppelt ist und ein-gerichtet ist, eine Kernschaltung der Serielle-Ports-Speichervorrichtung in Antwort auf die de-tektierte Inaktivität bei der Datenübertragung und dem Datenempfang auf allen der Mehrzahl von seriellen Ports für eine Schwellenzeitdauer auszuschalten.
10. System gemäß Anspruch 9, wobei Ausschalten je-des seriellen Ports Entfernen je-des Endenabschlus-ses des Ports aufweist.
11. System gemäß Anspruch 9, ferner aufweisend eine Taktleitung (140) für jeden seriellen Port zum Führen eine Taktsignals, wobei die Port-Ausschaltkompo-nente für jeden seriellen Port ein Taktschalter (170) ist, der mit der Taktleitung für den seriellen Port ge-koppelt ist, und wobei Ausschalten eines seriellen Ports Entfernen des Taktsignals von dem seriellen Port aufweist.
12. System gemäß Anspruch 9, ferner aufweisend eine Energieleitung (155) für jeden seriellen Port zum Be-reitstellen von Energie für den seriellen Port, wobei die Port-Ausschaltkomponente für jeden seriellen Port ein Energieschalter (175) ist, der mit der Ener-gieleitung für den seriellen Port verbunden ist, und wobei Ausschalten eines seriellen Ports Entfernen der Energie von dem seriellen Port aufweist.
13. System gemäß Anspruch 9, wobei die Kernschal-tung eines oder mehrere aufweist von:
einer Schaltung, die der Speichervorrichtung Grundenergie bereitstellt; oder
einem Taktgenerator für die Speichervorrich-tung.
14. System gemäß Anspruch 9, wobei die Energiesteu-erlogik ferner eingerichtet ist, selektiv jeden seriellen Port der Mehrzahl von seriellen Ports der Speicher-vorrichtung einzuschalten, wenn auf der Aktivitäts-detektionsleitung des seriellen Ports Aktivität detek-tiert wird.
5 10 15 20 25 30 35 40 45 50 55 Revendications
1. Procédé de réduction progressive de la consomma-tion de puissance dans un dispositif de mémoire mul-tiport ayant une pluralité de ports série, le procédé comprenant :
la surveillance de la transmission et de la récep-tion de données sur une pluralité de ports série (120-135) dans un dispositif de mémoire en uti-lisant des lignes de détection d’activité distinctes (145) chacune couplée à un port série corres-pondant de la pluralité de ports série ;
la détermination de si un quelconque port série de la pluralité de ports série est inactif pour la transmission et la réception de données sur la base, au moins en partie, de la ligne de détection d’activité pour le port série ;
pour chacun de la pluralité de ports série sur-veillée, la détection de quand un critère d’arrêt est satisfait au niveau du port série, le critère d’arrêt comprenant une période d’inactivité pour la transmission et la réception de données au niveau du port série ; et
lorsque le critère d’arrêt est satisfait au niveau d’un quelconque port série de la pluralité de ports série, la mise hors tension sélective de chaque port série remplissant le critère d’arrêt sans affecter le fonctionnement de la pluralité d’autres ports série du dispositif de mémoire ; et lors de la détermination selon laquelle la trans-mission et la réception de données a cessé pour la totalité de la pluralité de ports série du dispo-sitif de mémoire pendant une période seuil sur la base, au moins en partie, des lignes de dé-tection d’activité pour la pluralité de ports série, l’exécution d’un ou plusieurs parmi le blocage de la puissance de coeur vers le dispositif de mémoire ou le blocage d’un générateur d’horlo-ge vers le dispositif de mémoire.
2. Procédé selon la revendication 1, caractérisé en ce que la mise hors tension dudit chaque port série comprend un ou plusieurs parmi la suppression de la terminaison du port série, la suppression du signal d’horloge du port série, ou la suppression de la puis-sance du port.
3. Procédé selon la revendication 1, comprenant en outre :
lors de la détection d’une transmission à un quel-conque port série de la pluralité de ports série qui a été mis hors tension, la mise sous tension du port série pour recevoir la transmission ; et lors de la détection d’une tension différentielle appliquée à un quelconque port série de la plu-ralité de ports série qui a été mis hors tension,
la mise sous tension du port série.
4. Procédé selon la revendication 1, dans lequel une horloge pour faire fonctionner chacun de la pluralité de ports série du dispositif de mémoire est fournie par une boucle à phase asservie.
5. Procédé selon la revendication 1, dans lequel cha-cun de la pluralité de ports est couplé à un d’une pluralité de bancs de mémoire du dispositif de mé-moire.
6. Procédé selon la revendication 1, dans lequel le cri-tère d’arrêt comprend en outre une commande reçue d’un hôte, dans lequel la commande indique qu’aucune donnée ne sera transférée pendant une période de temps.
7. Procédé selon la revendication 1, comprenant en outre :
la détection de quand un critère de mise sous tension est satisfait au niveau d’un quelconque port série mis hors tension de la pluralité de ports série ; et
lorsque le critère de mise sous tension est sa-tisfait au niveau du port série mis hors tension, la mise sous tension sélective du port série sans affecter le fonctionnement de la pluralité d’autres ports série du dispositif de mémoire.
8. Procédé selon la revendication 7, dans lequel le cri-tère de mise sous tension pour un port série com-prend la détection d’un changement d’un état de si-gnal sur la ligne de détection pour le port série.
9. Système de commande de puissance pour réduire progressivement la consommation de puissance d’un dispositif de mémoire ayant une pluralité de ports série, comprenant :
une logique de commande de puissance (160) configurée pour détecter l’activité de chacun d’une pluralité de ports série (120-135) du dis-positif de mémoire en utilisant une ligne de dé-tection d’activité distincte (145) pour chacun des ports série, la logique de commande de puis-sance destinée à déterminer si un critère d’arrêt pour l’un quelconque de la pluralité de ports sé-rie est satisfait sur la base, au moins en partie, de l’inactivité du port série pour la transmission et la réception de données pendant une période de temporisation ;
un composant de mise hors tension de port (170-175) couplé à la logique de commande de puissance et configuré pour mettre hors tension sélectivement chaque port série du dispositif de mémoire sur la base du critère d’arrêt pour
cha-5 10 15 20 25 30 35 40 45 50 55
que port série ; et
un composant de commande de puissance de coeur (165) couplé à la logique de commande de puissance et configuré pour mettre hors ten-sion un ensemble de circuits de coeur du dispo-sitif de mémoire à port série en réponse à l’inac-tivité détectée dans la transmission et la récep-tion de données sur la totalité de la pluralité de ports série pendant une période de temps seuil.
10. Système selon la revendication 9, dans lequel la mi-se hors tension de chaque port série comprend la suppression d’une terminaison du port.
11. Système selon la revendication 9, comprenant en outre une ligne d’horloge (140) pour chaque port sé-rie pour acheminer un signal d’horloge, dans lequel le composant de mise hors tension de port pour cha-que port série est un commutateur d’horloge (170) couplé à la ligne d’horloge pour le port série, et dans lequel la mise hors tension de chaque port série com-prend la suppression du signal d’horloge du port sé-rie.
12. Système selon la revendication 9, comprenant en outre une ligne de puissance (155) pour chaque port série pour fournir de la puissance au port série, dans lequel le composant de mise hors tension de port pour chaque port série est un commutateur de puis-sance (175) couplé à la ligne de puispuis-sance pour le port série, et dans lequel la mise hors tension de chaque port série comprend la suppression de la puissance du port série.
13. Système selon la revendication 9, dans lequel l’en-semble de circuits de coeur comprend un ou plu-sieurs parmi :
un ensemble de circuits qui fournit de la puis-sance de coeur au dispositif de mémoire ; ou un générateur d’horloge pour le dispositif de mé-moire.
14. Système selon la revendication 9, dans lequel la lo-gique de commande de puissance est en outre con-figurée pour mettre sous tension sélectivement un quelconque port série mis hors tension de la pluralité de ports série du dispositif de mémoire lors de la détection d’activité sur la ligne de détection d’activité du port série.
REFERENCES CITED IN THE DESCRIPTION
This list of references cited by the applicant is for the reader’s convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.
Patent documents cited in the description • EP 1220226 A2 [0004]
• EP 0490679 A2 [0005]