Front-End Card Interface of the RCU
(Bernardo Mota & Carmen Gonzalez Gutierrez)ALTRO Interface
Block diagram
Memories and Functionality Macro Instructions
“Microcontroller” Code FEC debugging capabilities
Board Controller Interface
Block diagram Table of Registers
FEC Interface:
Block Diagram
Slow
Control
Design
Focus
DDLrcu_data 32 rcu_add 16 exec abort busy rcu_re rcu_valid interrupt cstb writeb ackb dstb trsfb errorb 40 bd Decoder Counter Table Register Table
R
C
U
M
as
te
r
ALTRO BUS
data_valid xoff 40 data Instruction MEM Result MEM ASSEMBLER & DDL Data MEM 1 Data MEM 2FSM
Pattern MEM L1, L2Instruction Memory DI DO AD 23 bit WE INCLK 256 DI DO AD 20 bit WE INCLK 128
Result Memory Data Memory x 2
256 DI DO AD 10 bit WE INCLK 1024 Pattern Memory WE DI DO AD 40 bit INCLK OUTCLK
0 4’h1 19 RS_STATUS 16’hxxxx 0 4’h2 19 RS_L1CNT 16’hxxxx 0 4’h3 19 RS_L2CNT 16’hxxxx 0 4’h9 19 END 16’hxxxx 0 4’h4 19 LOOP N cycles 15 8 7 16 8’hxx 0 4’h0 19 JUMP Add. 15 8 7 16 8’hxx 0 4’h5 19 RETURN Add. 15 8 7 16 8’hxx 0 4’h6 19 CHRDO 16’hxxxx 0 4’h7 19
PMREAD channel add.
15 12 11 16 4’hx 0 4’h8 19
PMWRITE chann.add.
15 13 11 16
3’hx
12
bcast
ALTRO Interface:
RCU Macro Instructions
0 4’ha
19
WAIT Nbr. Cycles CLK
0 19 RPINC CHRDO (Readout) WPINC (L2) WAIT SWTRG (L1) *END*
Testing Multi-Event Buffer & Readout 0 19 CONFIG PMREAD PMWRITE READ ‘N’ REG WRITE ‘N’ REG *END* LOOP RETURN JUMP
Testing Registers and Memories of the ALTROs & Configuration
0 19 RPINC CHRDO (Readout) *END* Normal Trigger sequence
BC Interface:
Block Diagram
ALTRO BUS
INTERFACE SlaveI2C
I2C Master Register Block mux scl sda we we D AD AD D AD D we Trigger counters L1 L2 Board Controller RCU I2C Master scl sda_ in sda_ out 40 2 1 16 5 clr_cnt Dout 16 oti 16 ALTRO BUS Master BD write,cstb ack decoder L1_cnt L2_cnt ADC I2C Slave
BC Interface:
Table of Registers
Number of Data Strobe in the last ReadOut N/A
R 8
Data Strobe Counter DSTBCNT
13
Sampling Clock counter N/A R 16 Sampling clk counter SCLKCNT 12
Number of L2 Trigger Received N/A R 16 L2 Counter L2CNT 11
Number of L1 Trigger Received N/A R 16 L1 Counter L1CNT 10
Digital Current Value N/A R 10 Digital Current DC 0C
Digital Voltage Value N/A R 10 Digital Voltage DV 0B
Analog Current Value N/A R 10 Analog Current AC 0A
Analog Voltage Value N/A R 10 Analog Voltage AV 09 Temperature Value N/A R 10 Temperature TEMP 08
Maximum Digital Current Threshold Y R/W 10 DC threshold DC_TH 05
Minimum Digital Voltage Threshold Y R/W 10 DV threshold DV_TH 04
Maximum Analog Current Threshold Y R/W 10 AC threshold AC_TH 03
Minimum Analog Voltage Threshold Y R/W 10 AV threshold AV_TH 02
Maximum Temperature Threshold Y R/W 10 Temperature Thr. T_TH 01 Meaning Allow Bcas t Acc. Mod e Width Reg. Name Mnemonic Reg. Addr.
THRESHOLDS
MEASURABLES
COUNTERS
Start Conversion / Read Out Monitor ADC Y
W
-Start Conversion mADC STCNV
1D
Reset Board Controller Y W -BC Reset BCRST 1C
Reset all the ALTROs Y W -ALTRO Reset ALRST 1B
Clear Error Status Register Y
W
-Conf. St. Reg 1 Clear CSR1CLR 1A Clear L1, L2, SCLK counters Y W -Counters Clear CNTCLR 19 Latch L1, L2, SCLK counters Y W -Counters Latch CNTLAT 18
BC Interface:
Table of Registers
Card Configuration Status Register R/W
16 Configuration Status 2
CSR2 16
Error Status Register R
14 Configuration Status 1
CSR1 15
Interrupt - Mask Register R/W
14 Configuration Status 0
CSR0 14
Each TPC Sector is served by 6 Readout Subsystems
Overall TPC: 4356 Front End Card 216 Readout Control Unit FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch CONF. & R/ O MON. & CTR L FEC CONTROLLER DATA PROC. DATA MEMORY DAQ INT (DDL-SIU) DCS INT (PROFIB, ETHER, ...) TRIGGER INT (TTC-RX)
CONFIG. & READOUT NETWORK (100 MB / s) DCS NETWORK 1 2 25 RCU CRX UX INT I2C bus {SDA,SCL}
The control network shares
the same back-plane as the ALTRO bus, using the same GTL transceivers.
The Electrical implementation of the I2C bus consists of 3 unidirectional lines instead of 2 bi-directional links.
THE FRONT-END CARD (FEC) Shaping Amplifiers (PASAs) ALTROs Current monitoring & supervision voltage regulators power connector control bus connector readout bus connectors GTL transceivers (back side) 190 mm 5-channel 10bit ADC FPGA hosting Board Controller logic and register set
I2C Bus
I2C Bus
•Transmission rate up to 3.4Mbit/sec in High Speed mode
•Worldwide standard protocol developed by Philips
•Maximum allowed bus capacitance of 400pF
•FECs can be connected or disconnected without disturbing the network functioning
•Bi-directional 8-bit serial data transfer
•Multi-master protocol with Arbitration
Present Status
Board Controller Interface
BC ADC : Design completed, simulated and tested
RCU BC (I2C + ALTRO bus): integration and test missing
√
√
ALTRO Interface
IP design completed and simulated
Testing in PLDA board: End of October
Additional macro instructions and active channel list to be included