Computer Installation, Maintenance and Repairing
IT (2012)
for
Second Semester
Sample Question
1. Explain Hand Drive Physical Installation. (20 Marks)
2. Describe Hard Disk Installation Produces. Explain Hard Drive Physical Installation. (20 Marks)
3. Describe High-Level (Operating System) Formatting. (10 Marks) 4. Explain FDISK and FORMAT limitations. (10 Marks)
5. Explain BIOS Hardware/Software. (15 marks) 6. Briefly explain ROM, PROM, EPROM, EEPROM /Flash ROM.
(20 marks)
7. Describe system components and explain processor, floppy disk and removable drives, CD/DVD-ROM drive, keyboard and pointing device (Mouse), Video card and Display, sound card and speakers. (20 marks)
8. Explain about motherboard installation. (20 marks)
9. Describe connect of the power supply, replacement of the cover and connection of
the external cables. (10 marks)
10. Explain connect I/O and other cable to the motherboard. (20 marks) 11. Explain running the Motherboard BIOS setup program. (CMOS setup)
(20 marks)
12. Explain troubleshooting new installations. (20 marks)
13. How are POST errors displayed? (20 marks)
14. Explain Hardware Diagnostics. (20 marks)
15. Explain Hardware Boot Process. (10 marks)
16. What are sample weekly and monthly maintenance procedures? (10 marks)
17. What are the problems during POST? (10 marks)
Computer Installation, Maintenance and Repairing
IT (2012)
for
Second Semester
Sample Answer & Question
1. Explain Hand Drive Physical Installation. (20 Marks)
The step-by-step procedures for installing a hard drive are as follows: * Check computer for an unused IDE connector. Typical Pentium-class and above PCs have provision for four IDE devices; if you have less, add your drive to an unused 40-pin connector on an IDE cable.
* Double-check the pin configuration. The colored (normally red or red- flecked) stripe on one edge of the cable goes to pin 1 of the hard drive’s data connector. Reverse this, and the drive won’t be capable goes to pin 1 of the hard drive’s data connector. Reverse this, and the drive won’t be capable of accepting identify, FDISK, or FORMAT. Most cable will be keyed to prevent improper installation.
* Slide the drive carefully into a drive bay of the correct size. Most hard drives, expect for a few very high-capacity SCSI drives meant for servers and the Quantum Bigfoot series, are 3 1/2 –inch wide and 1-inch high. Some case designs require that you attach rails to the side of the hard drive. If so, attach them to the drive using the screws supplied with either the case or the drive.
Then slide the drive into the bay in the case until the rails latch into place.
* Attach the existing data cable connector to the back of the drive. In that case, attach the cable to the drive before you slide it into the drive bay and fasten it into place.
* Attach the appropriate power connector to the drive.
* Turn on the computer and listen for the new hard disk to spin up. If you don’t hear anything from the drive, double-check the data and power cables.
* Restart the computer and access the BIOS setup screens to configure the new hard disk. At a minimum, you’ll need to detect. If your BIOS has an auto type setting, I recommend you use it as it will configure most parameters automatically. For IDE hard drives above 528 million bytes, need to set LBA translation to access the drive’s full capacity. Many systems have a Peripherals Configuration screen, which also allows you to set UDMA, PIO, and block
mode configurations for maximum drive performance. See your drive’s documentation for the correct settings. Save the BIOS configuration, and exit the BIOS setup screen to continue.
* Restart the computer, and prepare to run FDISK to prepare the hard drive for formatting and use. Or you can use drive partitioning software.
2. Describe Hard Disk Installation Produces. Explain Hard Drive Physical Installation. (20 Marks)
To install a hard drive in a PC, you must perform some or all of the following procedures:
* Configure the drive
* Configure the host adapter
* Physically install the drive
* Configure the system
* Partition the drive
* High-level format the drive.
The step-by-step procedures for installing a hard drive are as follows:
* Check computer for an unused IDE connector. Typical Pentium-class and above PCs have provision for four IDE devices; if you have less, add your drive to an unused 40-pin connector on an IDE cable.
* Double-check the pin configuration. The colored (normally red or red- flecked) stripe on one edge of the cable goes to pin 1 of the hard drive’s data connector. Reverse this, and the drive won’t be capable goes to pin 1 of the hard drive’s data connector. Reverse this, and the drive won’t be capable of accepting identify, FDISK, or FORMAT. Most cable will be keyed to prevent improper installation.
* Slide the drive carefully into a drive bay of the correct size. Most hard drives, expect for a few very high-capacity SCSI drives meant for servers and the Quantum Bigfoot series, are 3 1/2 –inch wide and 1-inch high. Some case
designs require that you attach rails to the side of the hard drive. If so, attach them to the drive using the screws supplied with either the case or the drive.
Then slide the drive into the bay in the case until the rails latch into place.
* Attach the existing data cable connector to the back of the drive. In that case, attach the cable to the drive before you slide it into the drive bay and fasten it into place.
* Attach the appropriate power connector to the drive.
* Turn on the computer and listen for the new hard disk to spin up. If you don’t hear anything from the drive, double-check the data and power cables.
* Restart the computer and access the BIOS setup screens to configure the new hard disk. At a minimum, you’ll need to detect. If your BIOS has an auto type setting, I recommend you use it as it will configure most parameters automatically. For IDE hard drives above 528 million bytes, need to set LBA translation to access the drive’s full capacity. Many systems have a Peripherals Configuration screen, which also allows you to set UDMA, PIO, and block mode configurations for maximum drive performance. See your drive’s documentation for the correct settings. Save the BIOS configuration, and exit the BIOS setup screen to continue.
* Restart the computer, and prepare to run FDISK to prepare the hard drive for formatting and use. Or you can use drive partitioning software.
3. Describe High-Level (Operating System) Formatting. (10 Marks)
The final step in the installation of a hard disk drive is the high-level format. The high-level format is specific to the file system. On Windows 9x and DOS systems, the primary functions of the high-level format is to create a FAT and a directory system on the disk so the operating system can manage files.
Each drive letter created by FDISK must be formatted before it can be used for data storage. Usually, you perform the high-level format with the FORMAT.
COM program or the formatting utility in Windows 9x Explorer.
FORMAT.COM uses the following syntax:
FORMAT C: /S/V
This command high-level formats drive C:, writes the hidden operating system files in the first part of the partition, and prompts for the entry of a volume label to be stored on the disk. The FAT high-level format program performs the following functions and procedures:
1. Scans the disk (read only) for tracks and sectors marked as bad during the LLF, and notes these tracks as being unreadable.
2. Returns the drive heads to the first cylinder of the partition, and at cylinder (Head 1, Sector 1) writes a DOS volume boot sector.
3. Writes a FAT at Head 1, Sector 2. Immediately after this FAT, it writes a second copy of the FAT. These FATs essentially are blank except for bad-cluster marks noting areas of the disk that were found to be unreadable during the marked-defect scan.
4. Writes a blank boot directory.
5. If the /S parameter is specified, prompts the user for a volume label, which is written as the fourth file entry in the root directory.
If the /V parameter is speciafied, prompts the user for a volume label, which is written as the fourth file entry in the root directory.
4. Explain FDISK and FORMAT limitations. (10 Marks)
For using FDISK with care, but there are other limitations you should keep in mind:
* FDISK doesn’t provide any help with issues of drive letter changes.
* FDISK requires FORMAT before the drive is ready for use.
* FORMAT must check the entire drive before making it ready for use.
* FDISK and FORMAT are designed for a single operating system environment, with no provision for multiboot options (Windows 9x and NT or Windows 9x and Linux, for example).
* DSISK and FORMAT offer no procedure for migrating data to a new drive, and XCOPY is tricky to use
* FDISK and FORMAT might cause conflicts with existing CD-ROM drives, which often use the next available drive letter after the existing hard drive
Typical features of automatic disk installation programs include the following:
• Replacement for SDISK and FORMAT.
• Database of drive jumpers for major brands and models
• Drive copy function.
• CD-ROM drive letter relocation utility.
• Menu-driven or wizard-driven process for installing new hard drive Optional override of BIOS limitation of large hard drives.
Explain Floppy Drive Installation Produces. (10 Marks) A floppy drive is one of the simplest types of drives to install. In most cases, installing a floppy disk drive is a matter the drive to the computer chassis or case, and then plugging the power and signal cables into the drive. Some type of bracket and screws are normally required to attach the drive to the chassis are designed to accept the drive with no brackets at all. Any brackets, if needed, are normally included with the chassis or case itself. When you connect a drive, make sure the power able is installed properly. The cable is normally keyed so you cannot plug it in backward. Also, install the data and control cable. If there is no key is in this cable, use the colored wire in the cable as a guide to the position of pin 1. this cable is oriented correctly when you plug it in so the colored wire is plugged into the disk drive connector toward the cut-out notch in the drive edge connector. If the drive LED stays on continuously when the system is running, that is a sure sign you have the floppy cable on backward.
Chapter 5: BIOS BASICS
5. Explain BIOS Hardware/Software.
(15marks)
6. Briefly explain ROM, PROM, EPROM, EEPROM /Flash ROM.
(20 marks)
ROM ( True or Mask ROM)
Most ROMs were manufactured with the binary data already “cast in” or integrated into the die. The die represents the actual silicon chips . These are called Mask ROMs because the data is formed into the mask from which the ROM die is photolithographically produced.
Mask ROM are exactly to pre recorded CD- ROMs . CD-ROM is fast manufactured as a blank and then the data is written to it by laser.
PROM
PROMs are a type of ROM that is blank when new and that must be programmed with data .The PROM has been avabiable in size from 1 KB (8 KB) to 2MB (16MB) or more.
They can be identified by path numbers which are 27 nnnn-where the 27 indecates the TI type PROM and the nnnn indicates the size of the chips in KB (not bytes) .
Although these chips are blank when new, they are preloaded with binary 1’s A blank PROM can be programmed . This requires a special machine call a device programmer .
Each binary 1 –bit can be thought of as a fuse, which is intact. Most chips run on 5 volts, but when a PROM is programmed , a higher voltage is placed at the various addresses with the chip.
PROM chips are used at OTP chips . The act of programming a PROM takes anywhere from a few seconds to a few minutes , depending on the size of the chip and the algorithm used by the programming device. A typical PROM programmer has multiple sockets .This is called gang programmer and can program several chips at once.
EPROM
An EPROM is a PROM that is erasable. An EPROM chip can be easily recognized by the clear quartz crystal window set in the chip package over the die.
The purpose of the window is to allow the ultraviolet light to reach the chip die because the EPROM is exposure to intense UV light. The window is quartz crystal.
The UV light erase the chip by causing a chemical reaction .To work , the UV exposure must be at a specific wave length (2,537 Angstroms) , at a fairly high intensity (12,000 uw/cm2) ,in close proximity (2 cm-3cm, or about when 1 inch ) ,unless and last for between 5 and 15 minutes duration.
Professional type EPROM eraser that can handle up to 50 chips at a time. The quartz crystal window on an EPROM is covered by type, which prevent accidental exposure to UV light.
7. Describe system components and explain processor, floppy disk and removable drives, CD/DVD-ROM drive, keyboard and pointing device (Mouse), Video card and Display, sound card and speakers. (20 marks)
System Components
The components used in building a typical PC are fuse and power supply, Motherboard, Processors with heat sink.
Memory Video card and display
Floppy drive Sound card and speakers Hard disk drive cooling fans
CD-ROM/DVD drive cables
Keyboard Hardware (nuts, bolts, screw and brackets) Pointing device (mouse) Operation system software
Processors
The motherboard should have one of the following processor sockets or slots:
Super 7: Supports the Intel Pentium, Pentium MMX, AMD K5, K6, K6-2, K6-3 Cyrix 6x86, 6x8xMx and MII Processors.
Socket 370 (also called PGA 370): Supports the socket versions of the Intel Celeron processor.
Slot 1 (also called SC-242): Support the slot versions of the Intel Celeron, Intel Pentium II and Pentium III processors
Slot 2 (also called SC-330): Supports the Intel Pentium II Xeon and Pentium Xeon processors.
Floppy Disk and Removable Drives
Since the advent of the CD-ROM, the floppy disk drive has largely been relegated to a minor role as an alternative system boot service.
LS-120(Super Disk) drives, which is a floppy drive that can read and write not only the standard 720kB and 1.44MB formats but a high capacity 120MB format as well.
Super Disk drive functions don’t need a standard floppy. Zip drive need to install a conventional floppy for backward compatibility, system configuration and system maintenance issues.
CD/DVD-ROM Drive
A CD/DVD-ROM drive should be considered a mandatory item in any PC construction. This is because virtually all software is now being distributed on CD- ROM, and many newer titles are on DVD. DVD drives can read CD-ROM drives as well as DVD-ROMs, so they are more flexible.
DVD-ROM is a high-density data storage format that uses a CD sized disc to store a great deal more data than a CD-ROM from 4.7 – 17GB, depending on the format.
These drives can read standard drums and audio CDs as well as the higher capacity DVD data and video discs.
Keyboard and Pointing Device (Mouse)
Two types of keyboard connectors are found in systems today. The purchasing keyboard must be matched with the connectors on the motherboard.
8. Explain about motherboard installation. (20 marks) When order the motherboard with a processor or memory, it will normally be installed on the board but may also be included separately.
Preparing the new motherboard
Before install the new motherboard, it should install the processor and memory.
This normally be much easier to do before the board is installed in the chassis.
Most processors today run hot enough to require to some form of heat sink to dissipate heat from the processor. To install the heat sink, use the following prodedures:
1. Take the new motherboard out of the anti-static bag it was supplied in and set it on the bag or the anti-static mat.
2. Install the processor. There are two procedures, one for socketed processors, and the other for slot based processor.
Socketed processors
The procedure is as follows:
Find the pin 1 on the processor. Next, find the corresponding pin 1 of the ZIF socket for the CUP on the motherboard or there may be a bevel on one corner of the socket. Insert the CUP into the ZIF socket by lifting the release lever until it is vertical. Then align the pins on the processor with the holes in the socket and drop it down into place.
If the processor does not go all the way into socket, check for possible interface or pin alignment problem but make sure it is fully seated and there is no gap between the bottom of the processor with the holes in the socket and drop it down into place.
Check for proper alignment and any possibly bent pins. If necessary, use a small needle nose pliers to carefully straighten to any pins.
Don’t bend them too much or they will break off. When the processor is fully seated in the socket, push the locking lever on the socket down until it latches to secure the processor.
Slot based processor
Start by positioning the two universal retention mechanism brackets on either side of the processor slot so that the holes in the brackets line up with the holes in the motherboard. Push the included fasteners through the mounting holes in the retention bracket and motherboard until it snaps into place.
3. If the CPU does not already have a heat sink attached to it, attach it now.
Most heat sinks will either clip directly to the CPU or to the socket with one or more retainer clips. Be careful when attaching the clip to the socket.
In most cases, it is a good idea to put a dab of heat sink thermal transfer compound on the CPU before installing the heat sink.
This prevents any air gaps and allows the heat sink to work more efficiently.
4. Refer to the motherboard manufacturer’s to set the jumpers, if any, to match the CPU going to install. Look for the diagram of the motherboard to find the jumper location and look for the tables for the right settings for CPU.
If the CPU was supplied already installed on the motherboard, the jumpers should already be correctly set, but it is still a good idea to check them.
9. Describe connect of the power supply, replacement of the cover and connection
of the external cables. (10 marks)
To attach the power connector from the power supply to the motherboard, do the following:
1. If the system uses a single ATX style power connector, plug it in, it can go on only one way. If two separate six-wire connectors are used, the two black ground wires on the ends of the connectors must meet in the middle. Align the power connectors such that the black ground wires are adjacent to each other and plug in the connectors. Consult the documentation with your board to make sure the power supply connection is correct.
2. Plug in the power lead for the CPU fan if one is used. The fan will either connect to the power supply via a disk drive power connector or it may connect directly to a fan power connector on the motherboard.
Replace the cover and connect external cables
Use the following procedures to complete the assembly:
1. Side the cover onto the case.
2. Before powering up the system, connect any external cabels
3. Plug the 15-pin monitor cable into the video card female connector.
4. Attach the phone cord to the modem.
5. Plug the round keyboard cable into the keyboard connector and plug the mouse into the mouse port or serial port.
10. Explain connect I/O and other cable to the motherboard. (20 marks)
There are several connections that must be made between a motherboard and the case. If the motherboard has onboard I/O, use the following procedures to connect the cables:
1. Connect the floppy cable between the floppy drives and the 34 pin floppy controller connector to the motherboard.
2. Connect the IDE cables between the hard disk, IDE CD-ROM, and athe 40- pin primary and secondary IDE connectors on the motherboard.
3. On non-ATA boards, a 25-pin female cable port brackets in normally used for the parallel port.
4. If the ports don’t have card slot-type brackets, the essential expansion slots may be port knockouts on the back of the case that can use instead.
5. Advanced motherboards include a built-in mouse port. The connector for this port is not built into the back of the motherboard. In that case, plug the cable into the motherboard mouse connector and then attach the external mouse connector bracket to the case.
6. Attach the front panel switch, LED, and internal speaker wires from the case front panel to the motherboard.
11. Explain running the Motherboard BIOS setup program. (CMOS setup) (20 marks)
Now that everything is connect, the system will also test itself to determine whether there are any problems:
1. Power on the monitor first, and then the system unit, observe the operation via the screen and listen for any beeps from the system speakers.
2. The system should automatically go through a power-on self-test (POST) consisting of video BIOS checking, RAM testing and usually an installed component report. If there is a fatal error during the POST, you may not see anything on screen and the system might beep several times, indicating a specific problem. Check the motherboard BIOS documentation to determine what the beep bodes mean.
3. If there are no fatal errors, you should see the POST display on screen.
Depending on the type of motherboard, press a key or series of keys to interrupt the normal boot sequence and get to the setup program screen that allow you to enter the important system information. Normally, the system will indicate via the onscreen display which key to press to activate the BIOS setup program during the POST, check the motherboard manual for the key to press to enter the BIOS setup.
4. After the setup program is running, use the setup program menus to enter the current data and time, your hard drive settings, floppy drive types, video cards, keyboard settings and so on. Most new motherboard enters any parameters for it.
5. Once you gave checked over all the setting in the BIOS setup, follow the instructions on the screen or in the motherboard manual to save the settings and exit the setup menu.
12. Explain troubleshooting new installations. (20 marks)
At this point, the system should reset and attempt to boot normally from either a floppy disk or hard disk. The system should boot from Drive A and either reaches an installation menu or an A: prompt. If there are any problems, there are some basic items to check.
If the system won’t power up at all, check the power cord. If the cord is plugged into a power strip, make sure the strip is switched on. There is usually a power switch on the front of the case, but some power supplies have a switch on the back as well.
Check to see if the power switch is connected properly inside the case. There is a connection from the switch to the motherboard, check both ends to see that they are connected properly.
Check the main power connector from the supply to the board. Make sure the connection are seated fully and if the motherboard is a Baby-AT type, make sure they are plugged in with the correct orientation and sequence.
If the system appears to be running but you don’t see anything on the display, check the monitor to ensure that it is plugged in, turned on, and properly connected to the video card.
Make sure the monitor cord is securely plugged into the cord. Check the video card to be sure it is fully seated in the motherboard slot. Remove and reseat the video card and possibly try a different slot if it is a PCI card.
If the system beeps more than once, the BIOS is reporting a fatal error of some kind, look in the BIOS section for a table of beep codes.
13. How are POST errors displayed? (20 marks)
The POST-tests normally provided three types of output messages: audio codes, onscreen text messages, and hexadecimal numeric codes that are sent to an I/O port address.
POST errors can be displayed in the following three ways:
• Beep codes – Heard through the speaker attached to the motherboard
• POST checkpoint codes – A special card plugged into either an ISA or a PCI card slot is required to view these codes.
• Onscreen messages – Error messages displayed onscreen after the video adapter is initialized.
BIOS POST Beep Codes
Beep codes are used for fatal errors only, which are errors that occur so early in the process that the video card and other devices are not yet functional.
Because no display is available, these codes take the form of a series of beeps that identify the faulty component. When your computer is functioning normally you should hear one short beep when the system starts up at the completion of the POST.
BIOS POST Checkpoint Codes
POST checkpoint codes can be used to track the system progress through the boot process from power-on right up to the point at which the bootstrap loader runs. When placing a POST code reader card into a slot, during the POST, will see two digit hexadecimal numbers flash on the card’s display. If the system stops unexpectedly or hangs, can identify the test that was in progress during the hang from the two-digit code. This step usually helps to identify the malfunctioning component.
BIOS POST Onscreen Messages
Onscreen messages are brief messages that attempt to indicate a specific failure. These messages can be displayed only after the point at which the video adapter card and display have been initialized.
Most POST-code cards come with documentation listing the POST
checkpoint code for various BIOS versions. If your BIOS is different from what I have listed here, consult the documentation for your BIOS or the information that come with your particular POST card.
14. Explain Hardware Diagnostics. (20 marks)
Many types of diagnostic software are used with specific hardware products.
SCSI Diagnostics
SCSI is an add-on technology, and most SCSI host adapters contain their own BIOS that enable you to boot the system from a SCSI hard drive. The SCSI BIOS contains configuration software for the adapter’s various features and diagnostics software as well.
For SCSI adapters that use direct memory access (DMA) a Host adapter diagnostics feature is available which tests the communication between the adapter and the main system memory array by performing a series of DMA transfer. It this test fails, you are instructed how to configure the adapter to use a lower DMA transfer rate.
Network Interface Diagnostics
Network adapters have testing capabilities –
• Register Access test
• EEPROM vital data test
• EEPROM configurable data test
• FIFO loopback test
• Interrupt test
• Ethernet core loopback test
• Encoder/ Decoder loopback test
• Echo exchange test
15. Explain Hardware Boot Process. (10 marks)
The term boot comes from the word bootstrap and describes the method by which the PC becomes operational. Just as you pull on a large boot by the small strap attached to the back, a PC loads a large operating system by first loading a small program that can then pull the operating system into memory. The chain of events begins with the application of power and finally results in a fully functional computer system with software loaded and running. Each event is triggered by the event before it can initiate the event after it.
Error messages displayed during the boot process and those displayed during normal system operation can be hard to decipher.
OS Independent OS Dependent
- Motherboard ROM BIOS - System files
- Adapter card ROM BIOS extensions - Device drivers
- Master boot record - Shell program
- Volume boot record - Program run by autoexec.bat, the window startup group and the Registry
- Window (win.com)
16. What are sample weekly and monthly maintenance procedures? (10 marks)
The following is a sample weekly disk maintenance checklist.
- Backup any data or important files.
- Delete all temporary files, such as .tmp, ~.*, *.chk, web browser history and temporary Internet files.
- Empty the Recycle Bin.
- Finally run the defragmenting program.
The following are some monthly maintenance procedures should perform:
- Create an operating system startup disk.
- Check for and install any updated drivers for video cards, modems and other devices.
- Check for and install any operating system updates.
- Check for and install antivirus software updates.
- Clean the system, including the monitor screen, keyboard, CD/DVD drives, floppy drives, mouse and so on.
- Check that all system fans are operating properly, including the CPU heat sink, power supply and any chassis fans.
17. What are the problems during POST? (10 marks)
Problems that occur during the POST are usually caused by incorrect hardware configuration or installation. Actual hardware failure is a far less- frequent cause. If you have a POST error, check the following:
1. Are all cables correctly connected and secured?
2. Are the configuration settings correct in setup for the devices you have installed? In particular ensure the processor, memory and hard drive settings are correct.
3. Are all drives properly installed?
4. Are switches and jumpers on the baseboard correct, if changed from the default settings?
5. Are all resource settings on add-in boards and peripheral devices set so that no conflicts exist for example, two add-in boards sharing the same interrupt?
6. Is the power supply set to the proper input voltage?
7. Are adapter boards and disk drives installed correctly?
8. Is a keyboard attached?
9. Is a bootable hard disk installed?
10. Do the BIOS support the drive you have installed, and if so, are the parameters entered correctly?
11. Is a bootable floppy disk installed in drive A?
12. Is all memory SIMMs or DIMMs installed correctly? Try reseating them.
13. Do the operating system properly installed?
Microprocessor Programming
IT (2013)
for
Second Semester
Sample Question
PART (I)
1. Write the short notes about device selection signal. (10marks)
2. (a)What is the read and write signal. (10marks)
(b) Briefly explain about using read and write signals. (10marks)
3. Explain other control signals. (10marks)
4. Design a circuit to generate four active low control signals to allow an 8086 microprocessor to communicate with memory mapped or input/output mapped devices.
The signals should permit the processor to read from or write to these devices
individually. (10 marks)
5. Design a circuit to generate four active low control signals to allow an Z80 microprocessor to communicate with memory mapped or input/output mapped devices.
The signals should permit the processor to read from or write to these devices
individually. (10 marks)
6. Design a circuit to allow a 6800 microprocessor to specify whether it wishes to read
from or / and write to add-on devices. (10 marks)
7. Describe how to device two active-low addressing signals from a microcomputer. Only one of the two signals needs to be activated at any instant of time and used to address an add-on device. Assume that the area between locations 8000H and 9FFFH is available for
addressing by 16 address lines. (10 marks)
8. Modify the circuit so that a smaller addressing area is reserve for the two addressing signals.
8. (a)Assume address
8700H Æ 87FFH
(10 marks)
(b)
Assume address
9FF8 H Æ 9FFF H (10 marks)
9. Design a circuit to provide an 8086 microprocessor with the ability to read from two add-ons using I/o mapping. Assume that the area between 8700H to 87FFH. (10marks) 10. Derive two active-low device-selection signal to read from two add-ons to 8086 microprocessor by using input/output mapping. Assume that the addressing area between A7C8H to A7CFH can be used. (10 marks)
11. Discuss for using address decoder and its advantages? (20 marks) 12. Write the short notes folloing anytwo with diagram.
(i) input ports (ii) out put ports (iii) address and data buffers. (20 marks)
PART (II)
13. (a) Why an IT learns Assembly Language? (10-marks) (b) DEBUG the following simple programs. (10-marks)
1. mov ax,5 2. add ax,10h 3. add ax,20h 4. mov sum, ax 5. int 20
14. What is debugger? Explain the debug commands. (20 marks)
15. Trace the instructions using DEBUG and write down the final contents of AX and
BX registers. (20 marks)
16. Describe the CPU registers and explain the data registers with diagram. (20 marks)
17. (a) What is the Segment Registers? (10 marks)
(b) Describe the Index Registers. (10 marks)
18. Explain the conditions of control flags and status flags. (20 marks) 19. (a) Draw the IBM PC-XT/AT memory map.
(b) Demonstrate the data exchange the two variables from memory. (20-marks) 20. (a) If any of the following MOV statements are illegal, explain why:(10-marks) (b) What will be the hexadecimal value of the destination operand after each of the
following moves? (If any instruction is illegal, write the word ILLEGAL as the answer.) (10-marks)
21. (a) What will be the hexadecimal value of the destination operand after each of the following Statements has executed? You may assume that var1 is a word variable and that count and var2 are byte variables. If any instruction is illegal, write the word ILLEGAL as the answer. (10-marks) (b) As each of the following instructions is executed, fill in the hexadecimal value of
the operand listed on the right-hand side: (10-marks) 22. Explain direct addressing mode and indirect addressing mode. (20 marks)
Microprocessor Interfacing & Programming
IT (2013)
for
Second Semester
Sample Answer & Question
(Part I)
1. Write the short notes about device selection signal.(10marks)
Device-selection signals
When interfacing add-ons to a microcomputer, each add-on needs to be given a unique address . A logic circuit is required to produce a pulse only when that address is supplied by the microcomputer . This pulse selects ( enables) an add-on to communicate with the microcomputer . During communication, the selected add-on supplies
information to the microcomputer, or read information from it.
The microprocessor selects the device it wants to communicate with by supplying a suitable "device – selection " pulse to the device's enable line. The interface of add-ons to a microprocessor creates the need for a flexible decoding arrangement to produce an efficient interface and to permit the use of additional add-ons in future.
Memory mapping is the microcomputer deals with a device as one or more memory locations . The communication is achieved by executing instructions such as ' move to ' or 'load from ' memory , ( Input/Output mapping , which is support by some , but not all, microprocessors . The microprocessor executes IN and OUT instructions to produce an address of an input or an output device.
There are different ways of deriving selection signals . They depend on the type of microprocessor and the available ( unused ) addresses . Generating ( device- selection signals is combining two types of signals produced by a microprocessor. The first is the device-control signal and the second signal is the addressing signal.
device – control signal + addressing signal = device –selection signal 2. (a)What is the read and write signal.(10marks)
Read and write signals
The read and write signals permit a microprocessor to indicate whether it wishes to read from an input source or to write to an output destination.
Intel 8086 and 80186 and the zilop z80, the read and write signals appear on two separate active low lines. In other microprocessors, such as the Motorola 68000, both the read and write signals are issued from one line. A logic 1 on that line indicates a read command, and a logic 0 indicates a write command. If required, the two signals can be separated by using an inverting gate.
Figure: : Separating the read and write signals
2. (b) Briefly explain about using read and write signals. (10marks)
Explain Read & Write siganls are supplied to the Decading circuit
The microprocessor reads information from device A and write information to device B. Signal CS, can therefore be active by supplying a unique address and activating the read line. This signal enables device A to supply information to the data bus. Device A can be the source of the information, or it can act as carrier can activate signal CS2 in the same way expect for activating the writing rather than the read line. This resc in enabling device B to accept information can be used by device B, or passed or an external circuit or system.
Fig. Interfacing devices to a microcomputers
3. Explain other control signals.(10marks)
Other control signals
Some microprocessors include one or two control signals to permite supporting input / output mapping and memory mapping. It is at a logic 0 state during input/output mapping and at a logic1 state during memory mapping. In the Intel 8086 and 80186, this line is called the to/m line. It is at a logic1 state in input/output mapping.
Zilog z80 microprocessor identifies the type of mapping by using two output lines. The first os the TORQ (Input/Output ReQuest) line which is set to a logic 0 state when the microprocessor addresses a device using input/output mapping. The second line is the MEMRQ(memory request) line which is set to a logic 0 when the microprocessor addresses a memory mapped device. These signal can be included as inputs to a circuit generating device-selection signals.
The Motorola 68000 microprocessor uses the memory-mapping method and thus add are addressed in the same way as memory devices. One of the control signals provided in the same way as 68000, the AS (address strobe) . It is set to a logic 0 state when the address line contains a valid address. The DTACK (data acknowledge) line, to accept an acknowledge from external devices.
4. Design a circuit to generate four active low control signals to allow an 8086 microprocessor to communicate with memory mapped or input/output mapped devices.
microcomputer device
A
device B address and
control lines
CS2 CS1
data line
decoding circuit
The signals should permit the processor to read from or write to these devices individually.(10 marks)
Answer:
The requirement can be satisfied by using three control lines from the processors, namely RD ,WR and M/IO line is low for input/output mapping and high for memory mapping The required output signals are normally referred to as:
MEMR (MEMORY READ) MEMW (MEMORY WRITE ) IOR (INPUT / OUTPUT READ) IOW(INPUT / OUTPUT WRITE )
The MEMR and MEMW signals are used to identify the aim of the microprocessor to communicate (read or write) by using the memory-mapping method .On the other hand ,IOR and IOW signals indicate whether the microprocessor wants to read from or write to a device by using the input/output-mapping method .The circuit in figure uses two ICS,
1. 74ls32 (quad 2 input OR gate 2c) and
2. 2.74LS14 (hex schmitt-trigger inverting gates)
.
Fig . Generating device-control signals using the 8086.
5. Design a circuit to generate four active low control signals to allow an Z80 microprocessor to communicate with memory mapped or input/output mapped devices.
The signals should permit the processor to read from or write to these devices individually.(10 marks)
Answer:
The z80 provides one line for the input/output request(IORQ) and another for the memory request(MEMRQ) when the z80 wants to receive information from an external source, it activates either of these lines and sets the read line (RD) to a logic 0 state.
Similarty , writing to an external destination is performed by activating either of these lines and the write line (WR).
RD
MEMR
WR
MEMW M/IO
IOR
IOW
o
The required four signals can be produced by using these two lines with the read and write lines, where all the signals are active-low. So the circuit in figure use only one TC (1 74LS32 (quad 2input OR gate IC).
.
Fig: Generating device-control signal using the Z80.
Let us now consider generating device-control signals from the 68000 microprocessor.
Answer:
Since 6800 microprocessor uses memory mapping, reading from or writing to add-one is treated as a memory read or a memory write respectively. Both the read and write signals are supplied on a single line and can be separated by using a single inverting gate to produce active low read and write signals.
Fig: Generating device – control signals using the 68000 microprocessor
6. Design a circuit to allow a 6800 microprocessor to specify whether it wishes to read from or / and write to add-on devices.(10 marks)
Answer
A simple circuit which can be used to allow the microprocessor to send information (write) to the add-on. Once the device receives the information, it activates the DTACK line informing the micro- processor of the reception of data.
If the aim of the interface is to receive data from the add-on (read), then an inverting gate is required to invert the R/W signal before supplying it to the input of the OR gate.
RD
MEMR
WR
MEMW MEMRQ
IOR IORQ
IOW
o
R/W R
MEMR
W
MEMW MEM
Fig. Interfacing to the 68000 microprocessor acknowledgement from device.
7. Describe how to device two active-low addressing signals from a microcomputer. Only one of the two signals needs to be activated at any instant of time and used to address an add-on device. Assume that the area between locations 8000H and 9FFFH is available for addressing by 16 address lines.(10 marks)
Answer
The two addressing signals can be generated by decoding some or all of the 16 address lines to generate two signals, each identifying the area reserved the area reserved for addressing one of the two devices.
Required address, 8000H 9FFFH
Signal X1 will be low when A15 is high white A14 and A13 are low.
For X1,
100x xxxx xxxx xxxx
8000H 9FFFH
68000
AS
W DTACK
device En Ack decoding
circuit
o data bus
address bus 68000
AS
R DTACK
device En Ack decoding
circuit
o data bus
address bus
Reserving area is
9FFFH – 8000H = 1FFFH = 2
13
= 8 KB
-Since X1 is low, the state of each output depends on the state of A12
X2 will be low (active) when X1 and A12 are low.
For X2,
1000 xxxx xxxx xxxx
8000H 9FFFH Reserving area is
8FFFH – 8000H = FFFH = 12bit = 212 = 4 KB
X3 will be low (active) when X1 is low and A12 is high For X3,
1001 xxxx xxxx xxxx
9000H 9FFFH Reserving area is
9FFFH – 9000H = FFFH = 12 bit = 2
12
= 4 KB
8. Modify the circuit presented in Example 2.4 so that a smaller addressing area is reserve
for the two addressing signals. (10 marks)
8. (a)Assume address
8700H Æ 87FFH
1000 0111 1111 1111
Signal X1 will be low, when A15 and A3 to A10 are high while A11, A12, A13, and A14 are low.
For X1,
1000 0111 1111 1xxx
87F8H Æ 87FFH
Reserving area is
o
o A15
A14 A13
A12
X1
X3 X2
2-input OR - 4 Inverter -2
87FFH – 87F8H = 7F =111=23= 8 bytes
Since X1 is low , the state of each output depends on the state of A2. X2 will be low ( active ) when X1 and A2 are low.
For X2,
1000 0111 1111 10xx
87F8H Æ87FB H
Reserving area is
87FBH – 87F8H = 3 H = 11 = 22 = 4 bytes X3 will be low ( active ) when X1 is low and A2 is high . For X3,
1000 0111 1111 11xx
87FCH Æ 87FFH
Reserving area is
87FFH – 87FCH = 3H = 11 = 22 = 4 bytes
o
o
o
o
X1
X2
X3
2-input OR -8 3-input NAND - 3 Inverter
A14 A13 A12 A11
A10 A9 A8
A7 A6 A5
A4 A3 A15 A2
8. (b)
Assume address
9FF8 H Æ 9FFF H
Signal X1 will be low, when A15 and A3 to A12 are high while A13, and A14 are low.
For X1,
1001 1111 1111 1xxx
9FF8 H Æ 9FFF H Reserving area is
9FFF H Æ 9FF8 H = 7H =111=23= 8 bytes
Since X1 is low , the state of each output depends on the state of A2. X2 will be low ( active ) when X1 and A2 are low.
For X2,
1001 1111 1111 10xx
9FF8 H Æ 9FFB H
Reserving area is
9FFB H – 9FF8 H = 3 H = 11 = 22 = 4 bytes X3 will be low when X1 is low and A2 is high .
For X3,
1000 0111 1111 11xx
9FFCH Æ 9FFFH
Reserving area is
9FFFH – 9FFC = 3H = 11 = 22 = 4 bytes o
o o o o
o A14
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A15
A2
X1
X2
X3
2-input OR - 2 13-input NAND - 1 Inverter - 5
To reduce the reserved addressing area, a simpler circuit can be
constructed by connecting lines A15, AA14, …,A3 to the inputs of a 13-input NAND gate , where lines A14 and A13 are inverted before their connections to the input of the NAND gate.
9. Design a circuit to provide an 8086 microprocessor with the ability to read from two add-ons using I/o mapping. Assume that the area between 8700H to 87FFH.(10marks) Derive Read signal by using Input / Out mapping
Both Read line and Input/output mapping line are zero, IOR is active-low state.
1 2 input OR gate Derive addressing signal
Let address locations are between 8700H to 87FFH.
o
o o
o A15
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3
A2
X1
X2
X3
R IOR
IO
1 13- input NAND gate 2 2-input OR gate
5 inverting gate
For X1,
A3 to A15 are inputs to the 13-input NAND gate,
A11 to A14 are low , so they are inverted before they connected to the input of NAND gate. A3 to A10 as well as A15 are high.
Locations are
1000 0111 1111 1xxx
( x is don't care ) ( 87F8H to 87FFH ) Reserving area are
( 87FFH – 87F8H = 7H = 111 =23 =8 bytes ) A2 is selection time , so X2 and X3 depend on it .
When X2 is low active, both X1 and A2 are low . Location are
1000 0111 1111 10xx
( 87F8 H to 87FB H ) Reserving area are
(87FB H – 87F8= 3H =11 =22 = 4 bytes) when A2 is high and X1 is low, X3 is low active . Location are
1000 0111 1111 11xx
(87FC H to 87FF H ) Reserving area are
( 87FFH – 87FC H = 3H = 11 =22 =4 bytes ) Deriving device – selection signal
o
o o
o A15
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3
A2
X1
X2
X3 o
o
o X2
CS1
IOR CS2
2 2 input OR gate
when IOR is low, CS1and CS2 depend on that X2 and X3 Both CS1 and CS2
are low active . The reserved addressing of both CS1 and CS2 are 4 byte.
10. Derive two active-low device-selection signal to read from two add-ons to 8086 microprocessor by using input/output mapping. Assume that the addressing area between A7C8H to A7CFH can be used.(10 marks)
Assume addressing area between
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A7CHH = 1 0 1 0 0 1 1 1 1 1 0 0 1 0 0 0 A7CFH = 1 0 1 0 0 1 1 1 1 1 0 0 1 1 1 1 It means 1010 0111 1100 xxxx. So that a circuit to derive addressing signal is
Using A2 line to divide two addressing signal X1 and X2 from X which occupied given addressing area each. These area are
X = A7C8H to A7CFH = 8 bytes X1 = A7C8H to A7CBH = 4 bytes and X2 = A7CCH to A7CFH = 4 bytes occupied.
The given control signals from 8086 up are RD, WR and M/IO. The required control signal IOR is derived by combining RD and IO signals.
Required device-selection signals can be combined by addressing signals and device control signal.
X3
D.S.S = A.S + D.C.S
C.S1 = X1 = IOR and C.S2 = X2 + IOR The designed circuit is using following ICs.
1. One 74LS133(13 input NAND) IC 2. Two 74LS32 (quad 2 input Ors) ICs and 3. Two 74LS14 (hex inverting gates)ICs.
11. Discuss for using address decoder and its advantagaes ?(20 marks) Using an address decoder
Producing addressing signals normally requires the use of several logic gates.
Instead of using such gates, one or more address decoder ICs can be employed. 74LS138 3-to-8 line decoder is one of the most widely used decoders. It has six input lines, three of which ( A,B and C ) are binary. weighted selection lines, and three of which ( G1,G2 and G3 ) are enable lines. It provides eight output lines ( Y0 to Y7 ), only one of which is activated ( logic 0 ) at one time . The activated output is the one whose address is the binary combination of the three selection lines. This can only take place if the output is enabled by setting G1=1 , G2 = 0, and G3=0. 74LS154 is a 4 – to – 16 lines decoder. It is a 24 pins to providing four selection lines (A ,B, C and D ) . Two active-low enable lines ( G1 and G2 ) and 16 output lines ( Y0 to Y15 ).
Fig: Address decoders ( a) two 74LS138 ICS
74LS138 IC is used to produce eight addressing signals Y0 to Y7. Address lines A13 , A14 and A15 of the controlling microprocessor are connected to the enable lines G1, G2 and G3 respectively .The decoder is enabled when lines A13,A14 and A15 are 1,0 and 0 respectively. Lines A10,A11 and A12 are used as channel selection lines by connecting them to inputs A,B and C of the IC. Address ranging from 2000H to 3FFFH, so reserving area is 3FFFH-2000H =1FFFH =213 =8 kilobytes . For each device reserves 1 kilobyte.
The addressing area reserved for each device is reduced by using a second 74 LS138 decoder which is enabled when A8 is high and both of address line A9 and output Y0 of the first decoder are low. For Y0 of second decoder the area 2100H to 21FFh . so reserving area is 21FFH-210FH=FF H =8 bit=28=256 bytes . Each device reserve 32 bytes.
+5V +5V
16 16
14 12
8 OV 8 OV A10 1
A11 2 A12 3 A13 6
A14 5 A15 4
A B C
G1 G2 G3
Y0 15
Y1 14 Y2 13 Y3 12 Y4 11 Y5 10
Y6 9 Y7 7
A5 1 A6 2
A7 3 A8 6 A9 5
4
A B C G1
G2 G3
Y0 Y1 Y2
Y3 Y4 Y5
Y6 Y7
15
14 13
12 11 10 9
The addressing area reserved per signal is 1 kilobyte for outputs Y1 to Y7 of the first decoder and 32 bytes for output Y0 to Y7 of the second decoder.
The advantage of using address decoders: they permit multi-device decoding without increasing the complexity, cost or size of the interfacing circuit and without sacrificing addressing area.
12. Write the short notes folloing anytwo with diagram.
(i) input ports (ii) out put ports (iii) address and data buffers.(20 marks)
(i) Input ports
An input port is a 3 state buffer whose output is equal to its input only when enabled by a controlling device, such as a microprocessor. It consists of several channels.
An input port can be formed from using one of many ICS.74LS244 is an 8 line 3 state buffer which contains two active low enable signals (1G and 2G). Each of these signals control four buffer lines. Line 1G controls the four lines whose inputs are A1,A2,A3 and A4whose output are C1,C2,C3and C4. Similarly, line 2G controls the four lines B1,B2,B3 and B4 whose outputs are D1,D2,D3 and D4.An output line is at the same logic state as its corresponding input when its control line is activated (logic 0 state)
By supplying the same command signal to both 1G and 2G.Lines, the IC will act as an 8 bit port. The eight buffers of the IC are non-latching which makes the IC suitable for use as input parts. An enabled input port supplies information to a data bus which is time shared by several devices and accepts signals from one device at a time IC is required for connection to an 8 bit data bus where as a 16 bit data bus requires two such Ics to receive 16 bit information.
Each of these Ics contains four buffers, each of which can be enabled or disabled independently of the others. The difference between the two Ics is in the state of the enable line . It is active low in the 74LS125 and active high in the 74LS126.
1G VCC A1 2G D4 C1 A2 B4 D3 C2 A3 B3 D2 C3 A4 B2 D 1 C4 GND B1 1
2 3
4 5 6 7 8
9 10
20 19 18
17 16 15 14 13
12 11
Fig 2.11 These state non latching buffers (a) the 74LS244 octal bufferI
(ii)Output ports
The requirement imposed on an output part is different from that imposed on an input part. Input part needs to put signals on the data bus only for a very shart period of time. The output port is supplied with signals from the data bus for a very short time and is required to latch those signals so that the output will be available as long as the buffer is supplied with power An output port consists of 3 state latches
A widely used IC is the 74LS374 octal D type latch. It contains eight 3-state edge- triggered flip-flops and provides two control lines, the first (pin 1) is the output enable line, while the second (pin11) is the clock line D and Q represent the input and the output . When the IC is utilized as an output part, the output enable line is connected to the o-v rails so that the output is always enabled when the clock line changes from a logic 0 to a logic1 state, each of the outputs is latched to the same logic state as its corresponding input. The IC can be connected to the data bus when the microprocessor wants to transfer information to the output it delivers the information to the data bus and alters the state of the clock line to command the 74LS374 IC to accept and latch information.
CE VCC Q0 Q7 D0 D7 D1 D6 Q1 Q6 Q2 Q5 D2 D5 D3 D4 Q3 Q4 GND CU 1
2 3
4 5 6 7 8
9 10
20 19 18
17 16 15 14 13
12 11
