Vol. 28, No. 16, (2019), pp. 1804 – 1809
Design and Verification of Half Adder using Look Up Table (LUT) in Quantum Dot Cellular Automata (QCA)
Chella Santhosh
1*, R. S. Ernest Ravindran
2*, Uday Bhanu
PrakashVulchi
3,VenkateshThumati
4, Mohammad ShifathulGufran
5,D. Bhavana
6, Sree Vardhan Cheerla
7*Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
E-mail: 1 [email protected], 2 [email protected], 3 [email protected], 4 [email protected], 5
[email protected], 6[email protected], 7 [email protected]
Abstract
Addition is the basic arithmetic operation that is used to perform complex operations. CMOS based chips, uses the transistor voltages to obtain the outputs are very efficient for these operations. In this research a new design of half adder circuit is implemented using look up tables, as LUT’s decrease the processing time and produce better output swings. Half adder circuit using LUT is designed by less cell count that reduce the area of the entire HA thereby reducing the delay and increasing the efficiency of the whole circuit. Half Adder circuit is implemented using QCADesigner Software tool.
Keywords: half adder, quantum cellular automata, logic gates, multiplexer, look-up table.
1. Introduction
Quantum cellular automata (QCA) is a technology that provides a platform that is very powerful than CMOS. It reflects data by electrons polarization. The size, speed, highly scalable, higher switching frequency and low power consumption make it attractive than CMOS technology. QCA may take over CMOS in the future due to its significant advantages.
This paper uses lookup tables to focus on Half Adder's implementation and simulation results of the projects. Comparative analysis of QCA design and CMOS is carried out in order to mea sure performance analysis in the covered area (size) [1].
John von Neumann suggested quantum cellular automata for the application of classic cellular automata with nanostructures. The term has been changed to QuantumPoint Cellular Automa ta (QCA) to differentiate this approach from models of quantum automata to perform quantum computation. To be more precise, QCA is like playing with electrons in their transition states[1]. The advantages are high speed, high device density, and low-power dissipation. QCA has attracted many research analysts because of its very small size (at the molecular or even atomic scale) and itslow power consumption, makes it a better replacement for CMOS technology.
2. QCA Cell and Multiplexer
The basic unit in the QCA circuit is a QCA cell with four quantum dots and a square pattern.
Zhang et al claimed that, by means of a clocking process, the cell is formed with two
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electrons that can move through the tunnels between the quantum dots. As a result of their mutual repulsion, these electrons tend to occupy the opposite polar sites.
Because of the coulombic force of repulsion is less in between two diametrically opposite quantum dots when compared to two adjacent quantum dots. In simple words, two electrons will not occupy the adjacent quantum dots. They tend to occupy the longest distance possible.
Hence by tunnelling process, those electrons occupy the diametrically opposite quantum dots.
The electrons are not capable of coming out of the quantum cell, but they can tunnel between the potential wells. The electrons can tunnel between the quantum wells through tunnel junctions.
𝑃 = 𝜌1 + 𝜌3 − (𝜌2 + 𝜌4) (𝜌1 + 𝜌2 + 𝜌3 + 𝜌4)
From the above equation where p stands for polarization in QCA, whereas p1 is polarization of 1st dot, p2 is polarization of 2nd dot, p3 is polarization of 3rd dot and p4 is the polarization of 4th dot in QCA to get the accurate result of the circuit and as well as waveform to the circuit[8].
A multiplexer (mux) is a combination circuit, also known as a selector of data. Mux is a device that selects the inputs and forwards them into a single output line. A 2^k input multiplexer has k select lines for selecting which input line to send to the output.Multiplexers are mainly used to increase the amount of data that can be sent over the network, that reduces time[2].
The multiplexer shown in Fig.2, selects which input to be sent to its output either A or B depending on the value of S. This is the general combinational circuit for a 2:1 Mux, It just has an inverter, 2 AND gates and 1 OR gate.
Fig. 1 Combinational Logic for 2:1MUX
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3. Proposed MUX Circuit
Fig. 2 Combinational Logic for 2:1MUX using QCA
Look Up Table that we usually call as LUT is a table that decides any input output. It is the truth table in the context of combinational logic. It is widely used for providing the appropriate performance with SRAM bits and multiplexers. A LUT can implement any function of k inputs with only SRAM bits and a multiplexer of 2^k:1 required. [4].
Processing time for outputs in LUTs is very low, as the SRAM bits are predefined, and the circuit doesn’t perform any arithmetic operations. This is the reason why LUTs standout in all other logic blocks[4]. Coming to the drawbacks in the LUT there is a much delay in the multiplexer which placed far from the input compared to near the input which leads to glitches in the design.
A look up table is an essentially an array that contains the outputs of a function that is being implemented on it. It is important to note that a LUT DOES NOT perform any calculations to obtain the output. This is the primary reason for its flexibility. If a LUT has n inputs, it can implement 2^n Boolean functions[4].
A half adder is a combinational electronic circuit where numbers are added. The half adder can add twobinary digits and provide a carry value for the output. The half-adder truth table is given in Table 1 Using a XOR logic gate and an AND logic gate is the standard representationof Half Adder Combinational circuit [6].
Adder deals by combining basic logic gate operations, using an XOR and an AND gate with the simplest form. This can be turned into a circuit that only has gates AND, OR and NOT.
This is useful as these integrated circuits with three simpler logic gates are more popular and available than the XOR IC., though this might result in a bigger circuit since three different chips are used instead of just one[7]. The Combinational logic and the look up table logic for half adder are verified using Logisim Software viz., Fig.3 and 4.
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A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Table.1 Half Adder Truth Table
Fig. 3 Combinational Logic for Half Adder
Fig. 4 Look Up Table Based Half Adder Logic
4. Proposed Half Adder QCA Circuit
The circuit of half adder in QCA using the general logic gate logic is quite complex. As all the gates are to be designed separately and both sum and carry outputs are obtained at distant places which also increase the delay with which the circuit operates. The proposed MUX design is very simple to understand as its just a combination of majority gates. If in these majority gates some cells are removed it functions as a ring of inverters and this inverter ring acts as an SRAM bit as in figure 5 and it forwards the input logic as soon as it changes at the
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takes place within the Look up Table logic and the outputs are just forwarded from one end to another end. The half adder logic is verified in figure 6.
Fig. 5 Proposed Look Up Table Based Half Adder Logic using QCA
Fig. 6 Combinational Logic for Half Adder
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5. Conclusion
Design of Multiplexer in QCA is very complicated as we must design inverters firstly then AND, OR gates and then derive those outputs. But our design is very new and easy to understand as it just a combination of two majority gates. LUT is very useful as it takes very less time for processing the outputs. QCA is the future of computing and these logics can help better once the fabrication units are set up.
6. References
1. Kranth, G & Sai, Naveen & R S, Ernest Ravindran. (2019). Study and Analysis of 3 -Input Logic Gates by Using Quantum Dot Cellular Automata. [2277-3878].
2. Firdous Ahmad, An Optimal Design of QCA Based 2n:1/1:2n Multiplexer/Demultiplexer and Its Efficient Digital Logic Realization, Microprocessors and Microsystems (2017).
3. M. A. Amiri, M. Mahdavi and S. Mirzakuchaki, "QCA implementation of a MUX-Based FPGA CLB," 2008 International Conference on Nanoscience and Nanotechnology, Melbourne, Vic., 2008, pp. [141-144].
4. G. Pavan, N. Chandrasekar and N. S. Kumar, "Implementation of Look up tables (LUTs) using Quantum-Dots," IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012), Nagapattinam, Tamil Nadu, 2012, pp. [275- 278].
5. D. Abedi and G. Jaberipur, "Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol.
65, no. 1, pp. 106-110, Jan. 2018.
6. Basu, Subhashee, Aditi Bal and Supriyo Sengupta. “A Novel Design of Half and Full Adder using Basic QCA Gates.” (2014).
7. Kamothe, India. (2017). DesignofUltra Low Power Look upTableusing Quantum Dot Cellular Automatafor Nano Scale Communication SANDEEP THAKUR. 36-42.
8. Yinchuan Xia, and Keying Qui, “Design and Application of Universal Logic Gate based on Quantum-Dot Cellular Automata”, 2008, 11th IEEE International conference on communication technology proceedings.
