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NOVAL 32 KBYTE HEMORY CARD

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WARRANTY

NOVAL 32 KBYTE MEMORY CARD

Three months warranty is to be assumed by the Dealer/ Distributor. NOVAL Inc. will sell memory chips to the warrantor at $5.00 per chip. If the card cannot be

repaired by replacing chips, NOVAL Inc. will assume warranty repair responsibilities during the first three months after delivery to the Deale~. For this p~rpose

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IMPORTANT

The NOVAL 32K memory board as shipped is strapped to occupy the second, third, fourth and fifth 8K blocks of a 64K

system (Hex addresses 2000-9FFF). Information

on ~odifying these assignmeQts is included in.

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NOVAL 32 KBYTE MEMORY CARD (Assembly No. 860-0042).

, ADVANCE INFORMATION (Preliminary)

The NOVAL 32Kmemory board provides 32 KBytes of dynamic memory on an S-LOO compatible PC board. .Principle features include low power operation (typically less than one static 8K memory board), foolproof refresh operation (invisible to 8080 CPU. maintained during wait states, halt, long interrupt responses) , and low cost. Every board is' factory assembled and tested, and all ICs are socketed for each service. Memory timing is fully synchronous, eliminating adjustments ..

JUMPER OPTIONS

The board as shipped from the factory has jumpers in the follow-ing positions:

1. E4 to E6.

2. El to E3.

This selects the MK41lS-4l 8K

RAM

part. In the event that i t is desired to use MK4ll5-40 parts, the jumper would be removed and a jumper would be connected between E5 and E6. ALL 32 MEMORY PARTS (U1-U32) MUST BE OF THE S~~E

TYPE (Either -40 or -41).

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NOVAL 32 KBYTE MEMORY~ CARD

2. El to E3.

3. BI B2 B3 B4

(Continued) Pad E2 is the S-lOO MWRITE signal. This jumper option is provided because some early 8-100 machines put the the gate which derives the MWRITE signal on the front panel. Since not all systems can be guaranteed to have a front pane1~

i t is always safer to derive the memory °write signal. Since the derived strobe

signal is not fed back into the bus, the El tooE3°jumper has no detrimental effect on

system operation~ If you have an overwhelming reason to use the MWRITE strobe directly (pin 68) then change the jumper to EI-E2.

These pads (upper right corner of PCB) control the paging of the memory board_ Slightly to the right and down from these pads are eight pads labelled 0 through 7. These correspond to the eight possible starting addresses in the

~ystem, according to the following table:

o

OOOO-lFFF

1 2000-3FFF

2 4000-5FFF

3 6000-7FFF

4 8000-9FFF

5 AOOO-BFFF

6 COOO-DFFF

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NOVAL 32 KBYTE MEMORY CARD

3. (Continued)

The B1-B4 pads select banks 1 through

4

of the memory array, each bank being 8K of memory. B1 corresponds to U1'thru U8;

B2 is U9 - U16; B3 is U17 - U24; B4 is U25 - U32. As shipped from the factory, the board is ~trapped to occupy the 32K from

2000 to 9FFF (HEX). To disable any 8K bank, i t is only necessary to remove the appropriate "B" jumper. This electrically removes an 8K bank from the system, so if' desired an 8K bank may be disabled without physically removing the RAM parts from their sockets.

The above information indicates that the memory board is actually four indep~ndent memory sections, each section being strappable to any 8K boundary. An example will clarify this point. Suppose your ~ystem has RAM at OOOO-,'IFFF, and at 8000-BFFF. To fill the, 8K gaps from 2000 through 7FFF, connect one B jumper to 1'1", another to "2", and another to "3". This'implements 24K from

2000 through 7FFF. The remaining 8K can be unused (the remaining B jumper unconnected), or strapped for a higher 8K block, (above BFFF) .

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NaVAL 32 KBYTE MEMORY CARD

Also, removing the B jumper for any 8K bank disables the S-lOO bus drivers for that bank, so a plugged-in but disabled bank of 8 RA.f\iS does not interfere wi th proper bus opera tion.·

SYSTEM COMPATIBILITY

The NaVAL RAH card should run in any 2 MHz S-lOO' system. Proper operaticin of the card depends on the following bus signals:

¢l (pin 25) ¢2 (pin 24) PSYNC (pin 76) SOUT (pin 45) WR' (pin· 77) MEMR (pin 47)

Data input bus (8 lines) Data output bus (8 lines) Address bus (16" lines),.

Any CPU c~rd which uses the 8224 clock generator for timing generation should work without a hitch. Also, any CPU card

which derives its own 8080 timing (which must meet the 8080 spec), will work. A possible exception in compatibility is an 8-100

CPU card which uses a processor other than the 8080 (or 80S0A).

The reason for this is that theS-lOO bus is defined for·specific 8080 signals, and any other processor design must emulate these signals to insure S-lOO compatibility. To take a specific

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NOVAL 32 KBYTE MEMORY CARD

SYSTEM COMPATIBILITY (Continued)

clock, and times its input and output operations ~lightly

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