10 BIT s Current Mode Pipelined ADC

10 BIT’s Current Mode Pipelined ADC

Abstract— This paper proposes the current mode pipelined ADC which is useful in integration on digital

CMOS technology. In CMOS technology in order to reduce the effective area and power dissipation the scaling of supply voltage is done, as the supply voltage is scaled down, the scaling of threshold voltage to the same level is difficult, decrease in supply voltage results in the degradation of conversion rate of ADC. So the current mode techniques are used which are less sensitive to the supply voltage. Two ADC’s are presented here , one with the basic current mirror and another with the feedback and regulated body driven current mirror which are of ten bit pipelined ADC designed and simulated in CADENCE SPECTRE tool in GPDK 90nm CMOS process, The converter architecture consists of a low resolution flash employing high-speed current comparators, a thermometer-weighted current-mode DAC and a simple current subtractor and amplifier for generating the residue current. By using pipelining concept, thermometer encoder and current subtractor cum amplifier will work in parallel and thus increasing the speed of the complete circuit. The power consumed by the 1st pipelined ADC would be 1.12milliwatts and where as the second ADC is 0.6684milliwatts.

Keywords- Pipelined ADC, Current mode, Analog to digital converter ,Cadence .

I. Introduction

As the demand for the mixed signal VLSI is growing day by day , the integrating components required for a chip , low power , high speed ADC’s (analog to digital converters) using CMOS has increased [1]. By using CMOS technology the size of the transistors can be scaled down and supply voltage (VDD) levels are also reduced so that the effective area and power is reduced. As the supply voltage is scaled down the scaling of the threshold voltage to the same level is the major concern. The difference between the supply voltage and the threshold voltage has a great impact on the design of the ADC. As the difference increases the output voltage swing is going to increase, leads to the higher reduction of maximum possible excess gate voltage. For low power dissipation, high device reliability and short channel effects in deep sub micron CMOS devices needs a supply voltage reduction from one technology to next scaled technology [1].

Generally flash ADC’s has the higher conversion rate, but if it exceeds more than 6 bits the area occupancy will be more and power dissipation will be more. So by using pipelined ADC the power dissipation is less and high

throughput is achieved.

Current mode ADC is a counterpart of voltage mode pipelined ADC, but the current mode pipelined ADC’s are not much explored so there is a requirement to examine potential performance parameters one can achieve using these type of converters. The current mode ADC is similar to the voltage mode , but in this case input will be

Block diagram of ADC

II. BASIC BLOCKS OF ADC:

A. Basics of Current mirrors:

The current mirror is basic crucial block for designing of ADC. These current mirrors are used in building the comparator and current subtractor cum amplifier and these are used in constructing the pipelined ADC. In a simple current mirror the output impedance is very low, so by varying the output node voltage the output current will also vary, so we use some advanced current mirror techniques. By using the feedback current mirror

the accuracy is more and the output impedance is more for regulated gate cascode current mirror. In this paper, the new current mirror is proposed which improves both accuracy and the output impedance.

Current mirror circuits:

As far as traditional current mirror circuit which is shown in fig A.1 is concerned, for the design of analog circuits the output resistance as to be more. As Current flows through M1 is corresponding to VGS1. VGS1=VGS2 so that same current flows through the M2 and M2 should be in the saturation region. But in this case the output resistance is very low, to improve output resistance the feedback current mirror technique is used

which is shown in fig A.2. In this technique the M0, M2, M10 forms a two stage cascode current mirror, M7-M9 is used to improve the accuracy and M3-M13 will increase the output impedance and as the number of

stages is increases the output impedance will increase.

One more type of current mirror is based on regulated gate cascode current mirror which is shown in the fig A.3. The output impedance is increased without using any compensation and biasing circuits. The Mn1-Mn4 is used as the two stage cascode mirror. The Mp1-Mp4 is used for matching accuracy Mn7 and Mn8 will increase the output impedance of the circuit. The good current mirror can be defined where input and output current should almost match. In this technique the aspect ratio of the Mn5 and Mn7 are same and can be found out by VGS5=VGS7, and then VDS6=VDS8 which in turn make VGS6=VGS8. As of VGS6=VGS2=VDS2 and

VGS6=VDS4, it’s easy to find VDS2=VDS4 and we can find Iin =I out.

swept from 5µA to 100µAmps. The supply voltage is 1.2 V. Due to the feed back in FCM the power dissipation is more compared to regular gate cascode current mirror (RGC).

Figure :A.1 Basic current mirror

differences of input currents to large variations in the output voltage. The source follower is present at the starting stage. The reference current is mirrored by PMOS current mirror (PCM), where as the input current is mirrored by NMOS current mirror (NCM). When Iin is less than the Iref then PCM go into the deep triode region in the absence of the inverter, now PCM has to drive the NCM and the output voltage at the node V (n1) will be VDD. In the same way if Iin is greater than the Iref then the output voltage will be VSS. So therefore the voltage at the node V (n1) will switch between the VDD and VSS. If the range of V (n1) is large then the delay is more and the settling time is more. So by placing the resistor in parallel with the inverter the switching activity at the node V(n1) can be reduced. By placing the resistor feedback inverter the PCM and NCM can be in the mirroring mode either by sourcing Iin-Iref when Iin>Iref or by sinking Iref-Iin when Iref>Iin [1]. To amplify the voltage at the node V (n2) the transistors are placed which are M1, M2, M3, and M4. The two inverters are placed after the four transistors to get the logic level at the output node. Inverter 3 is placed to get the high logic level when Iin<Iref, and logic low is obtained when Iin>Iref.

Figure:B.1 current comparator

C.CURRENT SUBTRACTOR CUM AMPLIFIER (CSA):

In subtractor cum amplifier will amplify the current which is passed to the CSA , and the same current has to be subtracted before the output appears out. In CSA the MN1 is the block which mirrors the Iin, MP1 is the block which mirrors current Iref which should be subtracted from Iin if Iin is greater than Iref, and the transistor MSW acts like a switch, when Iref is to be subtracted from Iin when MP1 is switched on. MP is one more module which mirrors the Iin when the switch MSW is switched off and when the MSW is switched on the subtraction of Iin and Iref is done and the amplification can be achieved by doubling the width of the MP block.

Figure : c.1 current subtractor cum amplifier III. CURRENT MODE PIPELINED ADC :

A.In this current mode pipelined ADC the input quantity is current and the comparison is done on the currents and the output bits of ADC are logic voltages. Here the comparator and subtractor cum amplifier are designed by using the basic current mirror. On the other hand the comparator and subtractor cum amplifier are designed by using the feedback current mirror and regulated gate cascode mirror. The major concern about the second architechture is the power. Each ADC will have the two bit flash ADC and three levels CSA and the thermometer encoder. The reference current will be shifted by the 10µamps from the input current as it’s not possible to mirror the current with 0µamps. CSA will amplify the 10µamps every time as Iin passes through the amplifier. Before sending it out the same current has to be subtracted from the CSA. Thermometer encoder will convert the 3 bits into the two equivalent bits. When the current comparator will generate the logic low, that many times the current has to be subtracted from the Iin . Comparator output will directly control the CSA output. Concurrent encoding and current subtraction allows the encoder and CSA to work parallel as it increases the speed of the circuit.

Figure A.1.1 : Internal structure of ADC

B. DIGITAL ERROR CORRECTION (DEC):

DEC is used to address the mirroring error and offset error of comparator. In correction unit we generate the two bits instead of one bit. DEC consists of all half adders and full adders and MSB of each ADC is used for output bit of the stage and LSB will correct the error. Hence the generated output will have one bit and a gain of 2 is obtained from the CSA amplifier. When the input current is passed to the next stage is doubled, the bits which are generated will be right shifted by one bit before adding to the bits of 1st stage. Digitally corrected bits of the ADC are obtained by adding these bits, which is implemented by using adders [1]

Figure B.1 Block diagram of pipelined ADC

IV. SIMULATION RESULTS AND CONCLUSION:

Two ADC’s are simulated, one by using normal basic current mirror and another ADC by taking the feedback current mirror as the comparator and subtractor cum amplifier is designed by using the regulated gate cascaded current mirror. These are designed in 90nm GPDK technology. The simulations are done by using the cadence design tool and simulated by using spectre. Simulated outputs are shown in table 4.1 and power dissipation is less in the second ADC compared to the first ADC. First ADC power dissipation was around 1.13milli watts and the second ADC as a power dissipation of 0.6684milli watts

Table 1 : Comparison of the performance parameters of the designed ADC

Performance parameters Using basic current mirrors Fcm and bdcm based current mirrors

Architecture pipelined pipelined

Technology 90nm 90nm

Supply voltage 1.2V 1.2V

resolution 10bits 10bits

Current range 0-100µamps 0-100µamps

Power dissipation 1.12milliwatts 0.6684milliwatts

Results:

Figure:A.2 transient analysis of the fcm and bdcm current mirror ADC ACKNOWLEDGMENT

The author would like to thank P.Jayakrishnan at the University of VIT for useful discussions about the pipelining concept.

REFERENCES:

[1] Siva R.Krishna , Maryam shojaei Baghini “Current Mode Pipelined ADC” 978-1-4244-3861-7 ©2009 IEEE 205 [2] R.Jacob Baker , Harry W.Li, David E.Boyce “CMOS Cicruit Design , Layout, And Simulation” ,2005

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