Preliminary Product Brief
December 1998
Description
The Ethernet Media Access Controller (MAC) core is a high-performance core with a low gate count, dual operating speeds of 10 and 100 Mbps, options to support physical layer devices, and many other features that make it attractive for use in a custom ASIC design (Figure 1). The MAC core design, designed in Verilog® with a nominal core size of approximately 11,000 gates, may be synthesized in 0.8-micron CMOS process technology or better.Features
‰ 10- or 100-Mbps MIl-based PHY device support • 10BASE-T• 100BASE-TX • 100BASE-FX • 100BASE-T4
‰ Optional interface cores: RMII, ENDEC, or PMD
‰ Optimized for switching and multiport applications
‰ 802.3x full- and half-duplex flow control
‰ Optional bus interface
Figure 1. Functional Block Diagram
Applications
The 10-/100-Mbps MAC core is optimized for applications using multiple Ethernet MACs, including switches, multiport bridges, and routers.‰ Network interface designs
‰ Ethernet switching designs
‰ Test equipment designs
The MAC core consists of six subcores, three for MAC functions and three for network I/O functions (Figure 2). The subcores, together with the additional cores, may be connected together to make a dual-speed (100 Mbps and 10 Mbps) Ethernet controller.
Verilog is a registered trademark of Cadence Design Systems.
Data
Customer ASIC Including High-Level Functions
Management Host Data Streams 98YL-0219A (12/98) Host CPU Access Signals Network Device 10/100 MII PHY Dual-Speed MAC
Figure 2. Internal Block Diagram
Management Statistics The transmit and receive functions of the MAC core are not instrumented with numerous counters for statistics collection. Instead the device uses a vector generation method that simplifies the timing of many asynchronous events and is more efficient in multiple MAC systems because statistics can be accumulated centrally for all of the MACs, reducing gate count and improving processing efficiency. The statistics-gathering mechanism is created outside the MAC on a case-by-case basis.
Statistics Gathering and Vectors
Most activity in a MAC is focused on major events such as completion of packet reception or transmission attempts. For each major event, the MAC generates a statistics vector
summarizing the results of the event and then latches it into a statistics collection block. There are generally two different vectors, one for receive and one for transmit. Vectors may be designed to include or exclude as many different parameters as a design requires (Table 1).
Transmit MII Data Host Transmit Byte Stream 98YL-0220A (12/98) TFUN Transmit Function Receive MII Data RFUN Receive Function MIIM MIIM MII PHY Device MACCTL 802.3x Flow Control Module
Host CPU Access Signals Host Receive Byte Stream Host Interface Clock Reset
Table 1. Statistics Example
Transmit Status Receive Status
Bit Description Bit Description
51 Transmit VLAN tag detect
50 Transmit back pressure previous packet 49 Transmit pause control frame
48 Transmit control frame 30 Receive VLAN tag detected
47-32 Total bytes transmitted on wire 29 Receive unsupported opcode
31 Transmit under run 28 Receive pause frame statistics
The vector approach reduces the requirement for individual synchronization of many individual events and also reduces gate count by eliminating the need for flip-flops throughout the MAC design. When multiple MAC designs are involved, using a statistics collecting block common to all MACs is easier than distributed gathering for parsing cumulative and derivative statistics.
Switch Building Block The MAC core is optimized for use in multiple MAC applications, including switches, multiport interface cards, and routers. Figure 3 shows a typical application where the MAC core is used as a building block for an eight-port switch.
Figure 3. Eight-Port Ethernet Switch Application
The exact nature of the common sections for system data transport, address recognition, and statistics will be application-dependent. The MAC core has built-in flexibility to accommodate almost any system design.
The physical (PHY) devices may be internal to the design or external. With the internal PHY, the MII may be a logical implementation without line driving capability, and the ports may be dual-speed or fixed at one dual-speed. The MAC core can be adapted to each of these variations in design. 98YL-0221A (12/98) MII PHY 10/100 MAC Common System Transport, Address Recognition, and Statistics MII PHY 10/100 MAC MII PHY 10/100 MAC MII PHY 10/100 MAC MII PHY 10/100 MAC MII PHY 10/100 MAC MII PHY 10/100 MAC MII PHY 10/100 MAC
Network Interface Controller
Figure 4 shows the MAC core implemented in a network controller chip used to create a PCI-based network controller for PCs.
Figure 4. Single MAC Core Implementation
Management statistics are generated as vectors by the MAC core. A mechanism creates and collects the vectors and then parses the information appropriately. The generalized byte date streams may interface to almost any bus type, including IISA, PCI, MCA, VLB, S-Bus, Nubus, SCSI, Multibus, and others. Depending on the sophistication of the bus, the bus interface core implementation can range from simple to complex.
Host Interface
The 10-/100-Mbps MAC connects to any one of a number of host system types. In a switching system, the host is generally the embedded CPU, or the backplane switching fabric (Figure 5). In a general network interface, the host might be a general-purpose computer communicating over the computer bus.Many different types of host interfaces may be used, including sophisticated bus mastering types such as PCI, shared memory, ring buffer, DMA and FIFO-based designs. FIFOs are useful for implementing the MAC core in an ASIC since the ASIC vendor’s cell library may include appropriate FIFO cells.
Figure 5. Interface to Host System
98YL-0222A (12/98) Host Bus Interface Module End Station Bus Address Recognition Statistics Gathering PHY 10/100 MAC • • • • • • • • • • • • Address Recognition Logic Receive Byte Stream Logic
MII Interface
The MAC core communicates with external PHY devices through the logical MII interface, which is divided into two signal sets (Figure 6). One set handles data transmission and reception, while the second set handles MII management functions.Figure 6. MII Data and Management Signal Sets
Within the MAC core, the data functions are handled by the TFUN and RFUN cores. The MII management set is handled by the MIIM core. Host access to the management interface in on a word basis through the normal host interface. The interface between the MIIM and the external PHY is a clocked serial interface as defined by the IEEE 802.3u specification.
98YL-0223A (12/98) MII PHY 10/100 MAC Host System MII Data MII Management
