Analysis and design of a 900 MHz Doherty Power Amplifier

(1)

Doherty Power Amplifier”

by

Nam Tran Pham

in Partial Fulfillment of the Requirements for the Degree

of

Bachelor of Engineering

at the Konstanz University of Applied Sciences

Faculty of Electrical and Information Technology

August 14, 2011

Thesis Supervisors:

Prof. Dr. Christoph Schick

(2)

In the late 1930s Radio became the dominant mass media in industrial nations and with it there was a demand for higher power levels in broadcasting. At that time most of the RF power amplifiers had very low efficiency, which in-creased the expense for operating a broadcast station in power consumption and cooling system. In September 1936 William H. Doherty introduced a new method to increase the efficiency of power amplifiers, this technique was able to increase the efficiency up to nearly 80%, later it was widely used in medium-and high-power RF amplifiers.

Nearly 60 years later energy-efficiency becomes more and more important, especially in new wireless transmitters such as cellular telephones, in which battery life is one of the key features of the device, the Doherty power ampli-fier architecture has become the ”ampliampli-fier of choice”.

There have been many improvements since the first publication of the Do-herty amplifier; this thesis, however, only introduces the basic ideal of DoDo-herty architecture. The basic functionality will be discussed and finally a Doherty amplifier is implemented at 900 MHz, both in simulation and hardware.

(3)

I wish to express my sincere gratitude and appreciation to my advisor, Prof. Dr. Christoph Schick, for introducing me to this challenging and interesting topic. I have significantly benefited from his broad range of expertise.

I would also like to thank to my committee members for all of the time they spent to review my thesis and their helpful comments. Special thanks to Prof. Edmund Z¨ahringer for his advices on working with transistor at high frequency. My gratefulness is directed to all the technical engineers at faculty of Electrical and Information Technology, HTWG Konstanz and to all my friends, who supported me during the research for this thesis.

Finally, I am grateful and indebted to the continuous love, understanding and supporting from my family. Love you all.

(4)

I declare that this thesis was composed by myself, that the work contained herein is my own except where explicitly stated otherwise in the text, and that this work has not been submitted for any other degree or professional qualification except as specified.

Konstanz, August 14, 2011

(5)

Table of contents iv List of figures vi List of tables ix Abbreviation x 1. Introduction 1 1.1. Introduction . . . 1 1.2. Thesis organization . . . 2

2. Doherty Amplifier Architecture 3 2.1. Power Amplifier Classes . . . 3

2.2. Doherty Load Modulation . . . 5

2.3. Analysis of the Doherty Amplifier Architecture . . . 8

2.3.1. Classical Doherty Amplifier . . . 8

2.3.2. Low-Power Operation . . . 10

2.3.3. Peak-Power Operation . . . 11

2.3.4. Medium-Power Operation . . . 12

2.3.5. Summary of Operation . . . 13

3. Design with analytic method 15 3.1. Design Parameters . . . 15

3.2. Input and output design . . . 19

3.2.1. Input design . . . 19

3.2.2. Output design . . . 23

3.3. Carry Amplifier design . . . 25

3.4. Peak Amplifier design . . . 26

3.5. Design review . . . 27

4. Design with Load-Pull technique 31 4.1. Quality factor Q . . . 31

4.2. Power Amplifier design with Load-Pull Technique . . . 33

4.3. Design parameters . . . 34

4.4. Amplifier design . . . 36

4.4.1. Carry amplifier V4 . . . 36

4.4.2. Carry amplifier V5, Peak amplifier V4 and Doherty amplifier 40 4.5. Performance review . . . 44

4.5.1. DC current behavior . . . 44

4.5.2. Carry amplifier . . . 44

(6)

4.5.4. Doherty amplifier . . . 48

5. Conclusions and Recommendations 52

5.1. Conclusions . . . 52 5.2. Recommendations . . . 53

A. Load pull simulation results 54

B. Schematics and layouts 59

C. Data sheet 65

(7)

2.1. Ideal class B amplifier circuit . . . 3

2.2. Conduction angles for a class A, B or C amplifier . . . 4

2.3. Collector current and voltage with power dissipation . . . 5

2.4. Transistor amplifier in common emitter circuit . . . 6

2.5. Active load-pull concept . . . 7

2.6. Doherty amplifier architecture . . . 7

2.7. Output voltage and current of classical Doherty amplifier[6] . . . 8

2.8. Efficiency of classical Doherty amplifier[6] . . . 9

2.9. Comparision of real Doherty amplifier with class A and AB amplifier[20] 10 2.10. Doherty amplifier architecture . . . 10

2.11. Ideal efficiency of Doherty amplifier vs. output power[5] . . . 14

3.1. Simplified transistor circuit . . . 15

3.2. Collector current and voltage of class B transistor . . . 16

3.3. Peak value of collector voltage at 50mW output . . . 17

3.4. Fundamental and peak value of collector current at 50mW output . 17 3.5. Collector voltage at 25mW output . . . 18

3.6. Current through load and collector at 25mW output . . . 18

3.7. Doherty amplifier architecture . . . 19

3.8. Hybrid divider . . . 20

3.9. Wilkinson coupler . . . 21

3.10. Input circuit . . . 21

3.11. Return loss and Insertion loss of the input circuit . . . 22

3.12. Phase delay and isolation of the input circuit . . . 22

3.13. Output circuit . . . 23

3.14. Phase of output signal . . . 24

3.15. Insertion loss and Isolation from P1 and P2 . . . 24

3.16. Collector current of AT42086 with Vcc = 2.7V . . . 25

3.17. Carry-Amplifier circuit simulation . . . 26

3.18. Peak-Amplifier simulation circuit . . . 26

3.19. Doherty Amplifier Simulation . . . 27

3.20. Collector efficiency of the simulation circuit . . . 27

3.21. Carry- and Peak-Transistor at transition point Pin = 3dBm . . . 28

3.22. Carry- and Peak-Transistor at max input power Pin = 6dBm . . . . 28

3.23. Summary of collector current and voltage in simulation (line - carry, dashed - peak), peak value of the fundamental frequency . . . 29

3.24. Waveform of collector current at the Carry- and Peak-Transistor . . 29

3.25. PAE and Gain of Doherty amplifier . . . 29

3.26. Output power, PAE, Gain versus input power [10] . . . 30

(8)

4.2. Insertion loss of capacitor [Murata-Data sheet] . . . 32

4.3. Measurement the 220nF capacitor . . . 32

4.4. Block diagram of a load-pull system[19] . . . 33

4.5. Results of load-pull technique . . . 34

4.6. Measurement results from test device Carry-V4B, measurement 1 . . 35

4.7. Measurement results from test device Carry-V4B, measurement 2 . . 35

4.8. Schematic of input matching for carry V4 . . . 37

4.9. Comparison between software simulation and hardware measurement of the carry input matching network V4 , Simulation-Line, Hardware-Symbol . . . 37

4.10. Layout and S-Parameter simulation result of the carry input matching network V4 . . . 38

4.11. Schematic of the output matching network for carry amplifier V4D . 38 4.12. Layout and S-Parameter simulation of the carry output matching net-work V4D . . . 39

4.13. Stability factor of the carry amplifier V4 . . . 39

4.14. Schematic of the input network for the carry amplifier V5 . . . 40

4.15. Layout and S-Parameter simulation results of the input network for the carry amplifier V5 . . . 41

4.16. Schematic of the output network for the carry amplifier V5 . . . 41

4.17. Layout and S-Parameter simulation results of the output network for the carry amplifier V5 . . . 42

4.18. Schematic of the input network for the peak amplifier V4 . . . 42

4.19. Layout and S-Parameter simulation results of the input network for the peak amplifier V4 . . . 42

4.20. Schematic of the output network for the peak amplifier V4 . . . 43

4.21. Layout and S-Parameter simulation results of the output network for the peak amplifier V4 . . . 43

4.22. Collector current versus base voltage of AT42086, with 2.7V Vcc supply 44 4.23. Measurement setup . . . 44

4.24. Measurement results from test device Carry-V4B . . . 45

4.25. Measurement results from test device Carry-V5A with 5V supply volt-age . . . 45

4.26. Measurement results from test device Carry-V5A with different sup-ply voltages, Pin= 3dBm . . . 45

4.27. Measurement results from test device Carry-V5A with different sup-ply voltages, Pin= 6dBm . . . 46

4.28. Measurement results from test device Peak-V4 with different bias volt-ages . . . 47

4.29. Measurement results of Doherty amplifier V1B . . . 49

A.1. Load pull contour with 0.7V bias and 2.7 V supply . . . 54

A.2. Source and Load impedance with 0.7V bias and 2.7V supply . . . . 54

A.3. Load pull contour with 0.3V bias and 2.7V supply . . . 55

(9)

A.5. Load pull contour with 0.7V bias and 5V supply . . . 56

A.6. Source and Load impedance with 0.7V bias and 5V supply . . . 56

A.8. Source and Load impedance with 0.3V bias and 5V supply . . . 57

A.10.Source and Load impedance with 0.5V bias and 5V supply . . . 58

B.1. Carry amplifier schematic with 0.7V bias and 2.7V supply, V4B . . . 60

B.2. Carry amplifier schematic with 0.7V bias and 2.7V supply, V4D . . . 61

B.3. Carry amplifier schematic with 0.7V bias and 5V supply, V5A . . . . 62

B.4. Peak amplifier schematic with 0.5V bias and 5V supply, V4 . . . 63

B.5. Layout of the Doherty amplifier V1B . . . 64

(10)

2.1. Summary of class A, AB, B and C amplifier . . . 5 4.1. Summary of source and load impedance for design . . . 36

(11)

ADS . . . Advanced Design System BJT . . . Bipolar Junction Transistor CAD . . . Computer Aided Design CAE . . . Computer-Aided Engineering CDMA . . . Code Division Multiple Access DUT . . . Device Under Test

ESR . . . Equivalent Series Resistance FET . . . Field Effect Transistor

HBT . . . Heterojunction Bipolar Transistor HTN . . . Harmonic Termination Network LSSP . . . Large-Signal S-Parameter PA . . . Power Amplifier

PAE . . . Power Added Efficiency PCB . . . Printed Circuit Board PEP . . . Peak Envelope Power PSK . . . Phase Shift Key

QAM . . . Quadrature Amplitude Modulation RF . . . Radio Frequency

(12)

1.1. Introduction

For the last decade the phenomenal growth of wireless communications has made remarkable impacts on the modern life. It began with the radio in the late 1930s and nowadays billions of people use mobile cellular phones everyday with the massive coverage around the world, which requires a signal with higher power level as well as high dynamic range. In order to communicate with the base station and among each other, every mobile device needs a RF power amplifier, which is a circuit for converting DC supply power into a significant amount of RF output power. In case of cellular telephone, the DC supply comes from the battery and the time it takes to discharge the battery while on call is an important metric to the success of a phone. Hence, there is an increasing demand for highly efficient RF power amplifier to meet the growing need for power saving, compact and low cost solutions. RF power am-plifier with high efficiency is able to extend the battery life and produce less heat, which means smaller heat sinks, this allows the cellular phone to have smaller size. Likewise for cellular base stations, high efficiency power amplifier is the key to save operation supply power, lower the cooling system cost and reduce thermal stress on active devices.

The instantaneous efficiency for the most power amplifiers is at its highest at its peak envelope power and decreases as output power decreases. In modern digital communication for maximum spectrum efficiency the modulation techniques like Phase Shift Key (PSK) or Quadrature Amplitude Modulation (QAM) are used in modulated signals such as W-CDMA. This results in a very large peak to average ratios of between 6 dB and 13 dB in the output power of signal [3], it means the power amplifier are often operated in low efficiency area. There are many methods to increase the efficiency of power amplifier for large range of output power like the Kahn Envelope Elimination and Restoration method [16] or the Chireix-outphasing transmitter [8], but they require a complicated circuitry. The Doherty amplifier is the best candidate, as a relatively simple efficiency enhancement technique.

The first goal in this thesis is to analyze the functionality and performance of the classical Doherty amplifier architecture. The second one is to design, manufacture and evaluate a classical Doherty amplifier, which is capable of deliver 20 dBm max-imum output power at 900 MHz.

(13)

1.2. Thesis organization

The thesis is organized as follows:

• Chapter 1 is a short introduction on the topic of power amplifier and the need for high efficiency amplifier. The main objects of this thesis are given at the end of the chapter.

• Chapter 2 starts with a brief review of the classes of power amplifiers and their maximum available efficiencies. This is followed by the principle of Doherty’s solution to increase the efficiency of the power amplifier. At the end is the review of the ideal Doherty power amplifier. This chapter provides the support theory for the power amplifier design process.

• Chapter 3 explains in detail the design and implementation of a Doherty power amplifier using the analytic method or load-line technique. A discussion on the advantages and disadvantages of this design is given at the end of the chapter.

• Chapter 4 discusses the new approach on design of a Doherty amplifier with load-pull technique. The problem with the implementation from simulation into hardware using the lumped component is explained at the begin of the chapter. This is followed by the introduction of the load-pull technique, after that the detail of using of using load-pull technique in designing Doherty am-plifier is given. At the end a short review of the performance and measurement results is provided.

• Finally the conclusions of this thesis and recommendations for further work are given in Chapter 5.

(14)

2.1. Power Amplifier Classes

Before going to the functionality of Doherty architecture, a short review of class A, B and C power amplifiers and the collector efficiency of a PA1 _{is in order.}

The class of a PA is defined by its conduction angle, which is defined as the portion of each RF2 sine wave the transistor is ”on”.

The simplified circuit in Figure 2.1 shows an example for PA class B: the input drive current I is assumed to be sinusoidal, the collector current maintains a sinusoidal shape when the transistor is ”on” and conducts no current when it is ”off”, all the harmonic currents are assumed to be shorted to ground by the ideal parallel resonant circuit at VCC. The resulting current I1 is sinusoidal and creates a sinusoidal voltage waveform as it terminates in the load resistance RL. The class B amplifier is defined as having a conduction angle of γ = π, which means that the transistor conducts for half of the RF cycle. The bias voltage VP C is configured for class B operation so that the base-emitter junction remains forward biased for half of the RF cycle.

Class A amplifier has a conduction angle of γ = 2π, it requires the bias voltage

Figure 2.1.: Ideal class B amplifier circuit

VP C to be sufficiently high to maintain forward base current throughout the RF cycle. Class C operation is defined as having any conduction angle less than π and amplifiers with conduction angle between π and 2π are referred to as class AB. Figure 2.2 shows resulting collector current IC with different amplifier class.

Collector efficiency η is defined as the ratio of the to load delivered RF power to the consumed DC power from collector voltage supply, as show in (2.1), where ˆIf 1

1_{Power Amplifier} 2_{Radio Frequency}

(15)

Figure 2.2.: Conduction angles for a class A, B or C amplifier

is the magnitude of the fundamental component of the collector current waveform:

η = Pout PDC,coll = ( ˆIf 1/ √ 2)2_R L IDC,collVcc = ˆ I_{f 1}2 RL 2IDC,collVcc (2.1) A class B amplifier example is used to demonstrate the calculation of efficiency, because of its ease of analysis and its application in Doherty architecture. Figure 2.3 displays the collector waveform current and voltage of a class B transistor (assuming all harmonic currents are terminated that the voltage at the load is a sinusoidal wave), the drawn line shows the transistor in saturation mode3, the dashed line shows the transistor out of saturation mode. The efficiency is directly related to the DC power dissipated in the transistor. Since the collector current IC is zero for half the conduction cycle, the instantaneous power dissipation in the transistor happens only during the lower half cycle of the voltage swing, where the product of IC and VC is non-zero. This area is shown in Figure 2.3 as a hashed area under the curve, and as the voltage swing is reduced, the ”area under the curve” goes up, therefore the efficiency of transistor is reduced.

The current waveform of a class B transistor is a half sine wave, its DC and fundamental values ˆIf 1 from the Fourier Series are:

IDC = IP eak π (2.2) ˆ If 1= IP eak 2 (2.3)

Substituting these into (2.1) gives

η = ˆ If 1IP eakRL 4 · π IP eakVcc (2.4) η = π 4 VL Vcc (2.5)

3_{Saturation: The condition, in which the minimum value of voltage swing at the collector}

(16)

Figure 2.3.: Collector current and voltage with power dissipation

which VL = ˆIf 1· RL is a magnitude of voltage swing at the load.At saturation, VL= Vccand η = π/4 = 78.5%, therefore the maxinum efficiency of class B transistor is 78.5%.

Table 2.1 shows the summary of different transistor classes versus conduction angles and ideal collector efficiencies.

Amplifier class Conduction angle Ideal collector efficiency

Class A γ = 2π 50%

Class AB π < γ < 2π 50% to 78.5%

Class B γ = π 78.5%

Class C γ < π 78.5% to 100%

Table 2.1.: Summary of class A, AB, B and C amplifier

2.2. Doherty Load Modulation

Figure 2.4 displays a transistor in common emitter circuit, the LC resonator at collector terminates all DC and harmonic frequency. UL is denoted as magnitude of voltage swing at the load and when the transistor is in saturation-mode UL reaches its maximum value. The basic idea of the load modulation is: an amplifier capable of delivering P1 to load R1 at its saturation ˆUL = ˆUL,max (high efficiency), if the load R1 can be reduced to R2 with R2 = α · R1(0 < α < 1), where α is a ratio between R1 and R2, and the amplifier still remains in saturation mode, then the

(17)

Figure 2.4.: Transistor amplifier in common emitter circuit

amplifier can deliver more output power at the same ˆUL,max and consequently the same efficiency. This can be derived as follow:

P1= ˆ U2 L,max 2 1 R1 (2.6) P2 = ˆ U_L,max2 2 1 R2 = P1 α > P1 (2.7)

To achieve this condition Doherty introduced the second current source into the circuit of amplifier, where current from the second transistor (or tube) is used to modify the load seen by the first device. This technique is called the ”active load-pull” concept[14], which is shown in Figure 2.5. Assume that I1 and I2 combine in-phase at RL, the relation between the impedances R1, R2 and currents I1, I2 is shown as follows: R1 = RL I1+ I2 I1 (2.8) R2 = RL I1+ I2 I2 (2.9) By using this effect, the current from one transistor can be used to manipulate the load resistance seen by the other. But the active load-pull concept illustrated in Figure 2.5 moves the load impedance seen by Q1 in the wrong way, as the current I2 increases so increases the impedance R1. So Doherty used an impedance inverter network at the output of the first transistor to reverse the active load-pull effect, this provides a reducing of R1 as I2 increases. If this reducing R1 is coupled with a rising RF drive to Q1, the saturation mode at Q1 is still assured, consequently the efficiency remains at maximum.

The impedance inverter in Figure 2.6 is realized by using a quarter wavelength line with characteristic impedance of ZIN V, the governing equation for the impedance inverters is:

(18)

Figure 2.5.: Active load-pull concept

Figure 2.6.: Doherty amplifier architecture

P1 is denoted as the output power delivered from Transistor T1 into the transmis-sion line and P1,T is the power out of the transmission line. Assuming a lossless transmission line, the current I1 at transistor’s side can be calculated as:

P1 = P1,T (2.11) I_{1,ef f}2 · R₁ = V 2 L,ef f R1,T (2.12) I_{1,ef f}2 · R1· R1,T = VL,ef f2 (2.13) Using (2.10) ⇒ I_{1,ef f} = VL,ef f IIN V (2.14) and the current I1,T at load’s side is:

I_{1,T ,ef f}2 · R_1,T = V 2 1,ef f R1 (2.15) I_{1,T ,ef f}2 · R_1,T · R₁ = V_{1,ef f}2 (2.16) ⇒ I_{1,T ,ef f} = V1,ef f ZIN V (2.17)

(19)

Note from (2.14) and (2.17) that the voltage on one side of the inverter is proportional to the current on the other side, but voltages are not directly related. This property allows V1 to remain fixed at saturation while VL is varied.

The impedance inverter at the output of transistor T1 introduces a 90o phase lag in the output current from T1, therefore the RF input of T2must also be delayed by 90o for I2 and I1,T to combine in phase. This can be achieved with a second impedance inverter at the input of transistor T2, in Figure 2.6 a second quarter wavelength transmission line is used.

2.3. Analysis of the Doherty Amplifier

Architecture

2.3.1. Classical Doherty Amplifier

Doherty chose both transistors to deliver half the power to the load at full output power: PT 1,max PL,max = PT 2,max PL,max = 1 2 (2.18)

this establishes a relation between R1,T, R2 and RL at full power as follows: V_L,max2 R1,T ,max = V 2 L,max R2,max = 1 2 V_L,max2 RL (2.19) R1,T ,max = R2,max = 2 · RL (2.20)

The characteristic impedance of the impedance inverter is also chosen to be 2 times the load impedance

ZIN V = 2 · RL (2.21)

These decisions result a region of high efficiency from full power to 6dB below full power. Doherty summarized the voltage and current relationships for the two de-vices in Figure 2.7 and the efficiency of the amplifier in Figure 2.8.

In the following paragraph, the term ”tube” is used, because at the time, when

Do-Figure 2.7.: Output voltage and current of classical Doherty amplifier[6]

(20)

Figure 2.8.: Efficiency of classical Doherty amplifier[6]

amplifier. Figure 2.9 shows the comparison of collector efficiency between classical Doherty amplifier and class A, B amplifiers [20]. Noted that the comparison is made with real components and a research [9] has confirmed the second ”peak” in effi-ciency at the transition point, the Doherty’s curve of effieffi-ciency in Figure 2.8 doesn’t show the second ”peak” at −6 dB under full power, therefore not fully satisfying the relationship of voltage and current in Figure 2.7. Note that tube 1 maintains constant RF plate voltage after transition point, which is defined as the point where tube 2 begins to conduct current. Both RF current curves are linear functions, but since the tube 2 turns on much later than tube 1 and ends up at the same value, the collector current’s slopes are different. This is one of the main problem during the design of Doherty Amplifier, Doherty solved this problem by using a class C amplifier, which turns later on and has higher slope than the class B amplifier.

The ratio α between R1 and R2 in Section 2.2 also designates the operation of the Doherty amplifier,which can be divided into 3 main areas, the next sub-sections are dedicated to review the working progress of Doherty amplifier in these areas:

• Low-Power area: 0 < V_L< αVcc • Medium-Power area: αV_cc< VL< Vcc • Peak-Power area: V_L= Vcc.

From this point on all the given AC values are peak values of the fundamental frequency and transistor T1 is referred as Carry-Transistor, transistor T2 as Peak-Transistor.

(21)

Figure 2.9.: Comparision of real Doherty amplifier with class A and AB amplifier[20]

2.3.2. Low-Power Operation

At low input power levels, the Peak-Transistor is ”off” (I2 = 0) and Carry-Transistor operates as a linear current source, the impedance R1,T according to (2.8) is

R1,T = RL (2.22)

Using (2.10) gives the impedance R1 seen by the Carry-Transistor R1(I2 = 0) = ZIN V2 R1,T = (2RL) 2 RL = 4RL (2.23)

(22)

trans-formation produced by the coupler is given by V_L2 2 · R1,T = V 2 1 2 · R1 (2.24) V2 1 V2 L = R1 R1,T (2.25) V1 VL = s R1 R1,T = 2 = 1 α (2.26)

The Carry-Transistor enters the saturation mode when V1= Vcc, therefore the satu-ration of Carry-Transistor occours at VL= α · Vcc. The RF-Output current delivered by the Carry-Transistor is derived as follows

I1V1 2 = I1,TVL 2 for I1,T = IL (2.27) I1 I1,T = VL V1 = α (2.28) I1= I1,T · α = VL· α R1,T (2.29) For an ideal B class transistor and relationships from (2.2) and (2.3) the DC-current is calculated as Idc= 2 π α · VL R1,T (2.30) hence, the efficiency of the amplifier is:

η = PAC PDC = V2 L 2·R1,T 2 π α·VL R1,T · Vcc (2.31) η = π 4α VL Vcc (2.32) When the Carry-Transistor reaches saturation and the Peak-Transistor remains cut-off VL = α · Vcc, the resultant efficiency is η = π/4 = 78.53%. This is the first peak of collector efficiency at −6 dB under maximum output power or −3 dB under maximum input power as shown in Figure 2.9.

2.3.3. Peak-Power Operation

In this area sufficient input power is provided to allow the Peak-Transistor to become saturated, collector voltages of the Carry-Transistor and the Peak-Transistor both swing from 0 < VCE < 2Vcc. According to (2.18) the currents from the Carry- and the Peak-Transistor are equal I1 = I2 = α · IL. Using the relation from (2.8) and (2.9) the impedances R1,T and R2 are given as follows

R1,T = R2 = 2 · RL (see Figure 2.10) (2.33) Since the characteristic impedance of the impedance inverter ZIN V = 2·RL, no trans-formation will occur, therefore the load impedance seen by the Carry-Transistor is

(23)

also R1= R1,T = 2·RL. Normally reducing load impedance tends to reduce the mag-nitude of voltage oscillation, but in this case with the rising input power the Carry-Transistor is able to deliver more output current, allowing the Carry-Carry-Transistor to remain saturated during the load modulation process. The Peak-Transistor has the same supply voltage Vcc like the Carry-Transistor, sees the same load impedance at collector and delivers the same amount of output current, resulting the Peak-Transistor is also saturated and has the maximum efficiency. This is the second peak of efficiency at full output and input power. The DC-Current from both tran-sistor is given Idc= Idc,1+ Idc,2 = 2 π VL RL (2.34) The resultant efficiency

η = V2 L 2·RL 2 π VL RL = π 4 (2.35)

is the same as the first peak efficiency in an ideal class B transistor.

The collector voltage of the Carry-Transistor is saturated, the same at the first peak efficiency, while the load impedance seen at the collector node is reduced to a half, as the result the output power of Carry-Transistor at second peak efficiency is two times its output power at the first peak efficiency. This accomplishes the goal of using load modulation, described at the beginning of section 2.2. The Carry- and the Peak-Transistor now deliver two times more output power than the maximum output power of the Carry-Transistor in low power region, hence, the sum of output power at peak power region is four times more than at low power, this explains the 6 dB distance between two ”peaks” of the collector efficiency versus the output power as mentioned in Section 2.3.1. And because the Peak-Transistor has the maximum efficiency of a B class amplifier, it appears that the biasing point of the Peak-Transistor is shifted from class C to class B, as shown in Figure 3.24(b) the Peak-Transistor at maximum output power has the same conduct angle γ = π like the Carry-Transistor in Figure 3.24(a).

2.3.4. Medium-Power Operation

At medium power levels, the Carry-Transistor is kept at verge of saturation and the Peak-Transistor operates as a linear current source. As displayed in Figure 2.7 the current I1,T is constant in the medium-power area, in spite of the rising current of I1, this can be proven by using the relation from (2.17)

I1,T = V1 ZIN V = Vcc ZIN V = α · Vcc RL (2.36) From (2.36), the RF current from Peak-Transistor to produce an output voltage VL is

I2 = IL− I1,T =

VL− α · Vcc RL

(2.37) Using (2.14), (2.17) and (2.36) the output current I1 of the Carry-Transistor is

I1= VL· I1,T V1 = α · VL RL for V1 = Vcc(saturated) (2.38)

(24)

For an ideal class B transistor, the total DC-input current is: IDC = 2 π (1 + α)VL− α · Vcc RL (2.39)

2.3.5. Summary of Operation

In the low-power region, the input power is insufficient to overcome the Peak-Transistor bias, hence the Peak-Peak-Transistor remains cut-off. The Carry-Peak-Transistor sees a constant load transformed by the quarter wavelength and operates as a nor-mal class-B amplifier. The efficiency of the system in this region is given

ηlow = π 4 VL α · Vcc for 0 < VL< α · Vcc (2.40) As the input power increases over the transition point, defined by VL = α · Vcc, the Carry-Transistor saturates and the Peak-Transistor begins to become active. The load R1 seen by Carry-Transistor is reduced by the additional current I2, the Carry-Transistor remains in saturation and acts as a voltage source, since the output voltage V1 saturates, it operates at peak efficiency but delivers an increasing amount of power. The efficiency in medium-power region is composited of collector efficiency from Carry- and Peak-Transistor, depending on which side is contributing more power at each point. Because the Peak-Transistor doesn’t have the benefit of load-modulation like Carry-Transistor, its efficiency is like a normal class-B amplifier

ηmid = π 4 VL/Vcc α(1 − Vcc/VL) + 1 for αVcc< VL< Vcc (2.41) At PEP4 output, both transistors see 2RL loads and deliver half of system output power. The efficiency is the same as class B amplifier.

ηpeak= π

4 for VL= Vcc (2.42)

Figure 2.11 shows the comparison of efficiency between Doherty amplifier with different α values and class-B Amplifier. The value of α = 0.25 is a modern approach with Doherty amplifier, called extended Doherty amplifier, where the first peak efficiency is −12 dB below full power, therefore the region of high efficiency is larger. But the ”dip” in efficiency with α = 0.25 is also deeper, because the efficiency of the Peak-Transistor in area near transition point is quite low. There are several researches ( [10],[21],[8],...) to reduce the ”dip” in efficiency with α = 0.25.

(25)

(26)

3.1. Design Parameters

Figure 3.1.: Simplified transistor circuit

Figure 3.1 shows a simplified common collector circuit for transistor with an RFC1 at the supply voltage. Figure 3.2 shows the resulting collector current and collector voltage of a class B transistor, the harmonic frequency is shorted to ground by an LC resonant circuit.

The requirement in this thesis is to design a Doherty amplifier with BJTs2_{capable of} delivering a power of 20 dBm or 100 mW at full output power.The design is based on the classical Doherty (section 2.3.1), therefore at peak output power each transistor delivers half of the output power 17 dBm or 50 mW. From (2.6) the amplitude of the voltage swing at the collector node as a function of output power Pf 1 and load impedance seen by collector RL is:

ˆ

VL=p2 · Pf 1· RL (3.1)

which is shown in Figure 3.3 for an output power P = 50 mW, also the fundamental frequency ˆIf 1 is calculated as ˆ If 1 = ˆ VL RL (3.2)

1_{Radio Frequency Choke} 2_{Bipolar Junction Transistor}

(27)

Figure 3.2.: Collector current and voltage of class B transistor

using (2.3) the peak value ˆIpeak of collector current is ˆ

Ipeak= 2 · ˆIf 1 (3.3)

The load impedance is chosen to be 50Ω, because the resulting voltage and collector current are in the limit range of the AT42086 BJT, and the 50Ω load impedance at full output power allows the design of Carry- and Peak-Transistor to be directly and individually tested with a spectrum analyzer without using any impedance converter network. Because at saturation the collector voltage is not zero, the saturation voltage for BJT normaly ranges from 0.3V to 0.5V , therefore the supply voltage is Vcc= ˆVL+ VCE,sat≈ 2.3 + 0.4 ≈ 2.7V (3.4) the value of ˆVL is acquired from Figure 3.3 for an 50 Ω impedance, also Figure 3.4 displays the peak values of the fundamental and maximal currents at the collector node for 50 mW output power. As for the low-power region, where Carry-Transistor delivers half of the output power compared to its output at full output power and Peak-Transistor remains cut-off, the output power is Pout,low = 25 mW, the Carry-Transistor sees a load impedance two times larger than in the peak-power region R1,low = 100Ω (section 2.3.2). The resulting collector current and voltage is shown in Figures 3.5, 3.6.

(28)

Figure 3.3.: Peak value of collector voltage at 50mW output

(29)

Figure 3.5.: Collector voltage at 25mW output

(30)

The concept circuit of Doherty amplifier in Figure 2.6 is repeated in Figure 3.7 for convenience.

Summary of design parameters:

• Supply voltage: V_cc= 2.7V

• At full output power: R₁ = R2= 50Ω.

• As derived in section 2.3.3, the load impedance R_L= 25Ω.

• The characteristic impedance of the impedance inverter Z_{IN V} = 50Ω. • At low-power region: R_1,low= 100Ω.

The bipolar-transistor AT-42086 from Avago-Technologies is used in the prototype design, because its high output power at high frequency (20dBm at 2GHz - Data sheet) and its available simulator model for CAE3 program. Agilent’s Advanced Design System(ADS) is used to simulate and to refine the prototype design. The FR4 substrate with 1 mm thickness, 35µm copper thickness, double side and = 4.3 was used.

3.2. Input and output design

3.2.1. Input design

Requirements for designing the input circuit are:

(31)

• The input power is to be equally divided between Carry- and Peak-Transistor. • The output ports should be isolated from the other to prevent cross-talk. • The output at port 3 is 90o _{phase lag compared to port 2.}

Figure 3.8.: Hybrid divider

Normally a hybrid-divider (Figure 3.8) can be used to fulfill these requirements, but a hybrid-divider requires a large physical space and is not flexible with respect to layout design. In this thesis the input is designed using the combination of a Wilkinson-divider and a microstrip line at the output of the Wilkinson-divider to create the phase-offset between the two output-ports of the input circuit, because the output signals of Wilkinson-coupler are in-phase. The benefit of using a microstrip line for phase-delay is, the length of the microstrip line can be simply adjusted to have different phase-offset other than 90o without any chance in power divide ratio between two transistors, because two transistor with different biasing are expected to have different phase-delay and regarding the influences of matching circuit at base and collector node of the transistors on phase-offset. The prototype is designed to work in a 50Ω-enviroment, so the ports P1, P2, P3 of the Wilkinson-coupler will see a Z0 = 50Ω impedance. The characteristic impedance of each ”arm” of the coupler is

Zarm= √

2 · Z0 ≈ 70.71Ω (3.5)

and the coupler resistor between two ”arms” is

Zcoupler = 2 · Z0 = 100Ω (3.6)

The Wilkison-coupler is designed using microstrip line for convenient PCB4 imple-mentation, and at 900MHz the quarter wavelength is short enough for small PCB

(32)

Figure 3.9.: Wilkinson coupler

layout. Using the mircostrip line calculation tool from ADS the parameters of the Wilkinson-coupler’s ”arm” are

W idth ≈ 1mm Length ≈ 47.8mm

A 50Ω quarter wavelength transmission line is used to insert the 90o phase lag between the output P2 and P3 while maintaining the matching condition for all ports. The design of the input circuit is shown in Figure 3.10 There are differences

Figure 3.10.: Input circuit

(33)

(a) Return loss (b) Insertion loss

Figure 3.11.: Return loss and Insertion loss of the input circuit

(a) Phase delay (b) Isolation between outputs

Figure 3.12.: Phase delay and isolation of the input circuit

different length of transmission lines and this also causes degradation in return loss (Figure 3.11(a)), but the difference is negligible. Figure 3.12 displays the resulting phase-offset between the two output ports of the input circuit. The 90o phase-lag between port P2 and P3 is temporary, because the phase delay of the Carry- and Peak-Transistor with different biasing is expected to be different, the length of the transmission line can be later adjusted for the optimal phase delay, which required for the outputs of the Carry- and Peak-Transistor to combine in-phase later. There is also a research on uneven power divider [12], in which the Peak-Transistor receives more input power than the Carry-Transistor to achieve the same output power. This can be useful, if the both transistor are the same type and it is difficult for the Peak-Transistor to have the same maximal output current like the Carry-Peak-Transistor.

(34)

3.2.2. Output design

As mentioned in the summary of the design paramters (section 3.1) the load impedance is RL= 25Ω, for the convenience of directly using a spectrum analyzer for measure-ment the output signal later, an impedance converter transformation is used to con-vert the 50Ω terminal impedance of the spectrum analyzer to 25Ω load impedance. The impedance converter is a quarter wavelength mircostrip line, its characteristic impedance is: Zoutput= p RL· Rterminal = √ 25 · 50 ≈ 35.35Ω (3.7)

Hence, the physical parameters of the mircostrip line at 900MHz are: W idth = 3.27mm

Length = 45.12mm The output circuit (Figure 3.13) consists of two parts:

• A 35Ω quarter wavelength microstrip line to transform the 50Ω terminal load to the 25Ω-load.

• A 50Ω quarter wavelength microstrip line acting as an impedance inverter between the output of the Carry-Transistor and the 25Ω load.

Figure 3.13.: Output circuit

The disadvantage of this design is, there is lack of isolation between Port P1 and Port P2 (Figure 3.15(b)), this may cause undesired ”talk over” between P1 and P2. There is also difference in insertion loss from P1 to P3 and from P2 to P3 because of the different length of transmission line. Figure 3.14 shows the 90o _phase-offset between the signal from P1 to P3 and the signal from P2 to P3.

(35)

Figure 3.14.: Phase of output signal

(a) Insertion loss (b) Isolation between input P1 and P2

(36)

3.3. Carry Amplifier design

Before the design of Carry amplifier begins, a simulation is made to determine the characteristic of the transistor AT42086. This information is used to design the bias network for the Carry-transistor. As mention in section 2.3.1 the Carry-transistor needs to be biased in class B mode, therefore from figure 3.16 the bias voltage to set to UBias,B= 0.7V. To improve the stability behavior of the transistor, a voltage

Figure 3.16.: Collector current of AT42086 with Vcc = 2.7V

feed-back circuit is deployed between the collector and the base node of the Carry-transistor, this will act as a controlled feed-back path between the collector and base node and the coupling resistance will suppress the unwanted influence from the collector node to the base node . The value of impedance in feed-back circuit is selected based on simulation experiment with the stability factor calculation function from ADS, goals are to achieve unconditionally stable and to maintain high-gain at 900 MHz.

The schematic of the Carry-Amplifier is shown in Figure 3.17,at the base node a matching network is used for matching purpose. This matching network is designed by using the LSSP5 function from ADS. A 50Ω quarter wavelength at the collector output terminates the harmonic frequencies to ground. The components in the simulation of the carry amplifier shown in Figure 3.17 are ideal components, with infinite quality factor. From simulation result the carry amplifier has 14 dB gain at 900 MHz, therefore the output reaches the transition point 14 dBm with 0 dBm input power.

(37)

Figure 3.17.: Carry-Amplifier circuit simulation

3.4. Peak Amplifier design

The design of Peak-amplifier is highly dependent on the operating point of the Carry-amplifier, in this case the bias voltage of the Peak-amplifier must be low enough so that at the transition point, 14 dBm output power, the Peak-transistor is in cut-off mode, but still high enough for the peak-transistor to achieve the same output power like the carry-transistor at max output power. Because at 900 MHz the AT-42086 is almost at its limit in the gain factor, and as discussed in section 2.3.1 the slope of the collector current from the peak-transistor is higher than the one from the carry-transistor, therefore a stabilization circuit for the Peak-transistor is removed as a trade-off for power gain. This decision can be accepted at this point, because the Peak-Transistor is biased very low, only conducts for short time. The input

Figure 3.18.: Peak-Amplifier simulation circuit

matching for Peak-Amplifier is based on LSSP-Simulation, and used to improve the power gain. The bias voltage of the Peak-Transistor is set to be 0.3V

(38)

3.5. Design review

Figure 3.19 shows the final stage of the Doherty amplifier in simulation. The simula-tion circuits of Carry- and Peak-Amplifier are combined with the input and output circuit. Figure 3.20 shows the resulting collector efficiency of the simulation circuit.

Figure 3.19.: Doherty Amplifier Simulation

As expected the first maximum efficiency is reached at Pin = 3 dBm or Pout = 14 dBm and the second maximum by Pin= 6 dBm or Pout= 20 dBm. The maximum efficiency is only about 50%, lower than the expected efficiency of 78.52% in Section 2.3, because of the saturated voltage VCE the collector voltage does not swing from 0 to 2Vcc and due to the mis-matched at output of the transistor the output power can not fully delivery to load.

Although the first maximum drifts to near Pout = 15 dBm in Figure 3.20(b), this can be explained by the performance of Carry- and Peak-Transistor at transition point Pin = 3 dBm in Figure 3.21. At Pin = 3 dBm the Carry-Transistor is almost at its saturation and the voltage at load is relatively high as well as the collector voltage of Peak-Transistor, because of Miller-effect[17] between the collector node and the base not, the base voltage of Transistor is shifted higher and the Peak-Transistor begins to conduct sooner than expected.

(a) (b)

(39)

(a) Carry-Transistor (b) Peak-Transistor

Figure 3.21.: Carry- and Peak-Transistor at transition point Pin = 3dBm

Figure 3.22.: Carry- and Peak-Transistor at max input power Pin = 6dBm

At Pin = 6 dBm both transistors are in saturation as expected (Figure 3.22) and the output power is Pout = 20 dBm, the amplifier reaches its maximum efficiency.

Figure 3.23 shows the summary performance of voltage and current in Carry- and Peak-Transistor dependent on Pin. There is a dip in collector voltage of the Carry-Transistor due to the non-linear slope of Peak-Carry-Transistor’s collector voltage. At high input power level the bias of Peak-Transistor is shifted from class C to class B, this explains the waveform of collector current in Figure 3.24(b), therefore the maximum efficiency of Doherty amplifier is equal the maximum efficiency of class B amplifier as predicted in Section 2.3.3.

Figure3.25(b) illustrates the gain factor of the Doherty amplifier in simulation, the gain factor has a non-linear progress in comparison with the result from [10], which displays in Figure 3.26, this result is caused because of the small collector current of the transistor, the collector current at its maximum value according to Figure 3.16, is still in the non-linear area. In order to improve the linearity the collector current must be large enough to overcome the non-linear area, in this case it is not recom-mended from the data sheet, because the maximum limit collector current of the AT42086 transistor is only 80 mA. The research in [22] is dedicated to improving the linearity of the Doherty Amplifier using Heterojunction Bipolar Transistor(HBT), which is a improvement of BJT for high frequency and high power application.

(40)

(a) Collector voltage (b) Collector current

Figure 3.23.: Summary of collector current and voltage in simulation (line -carry, dashed - peak), peak value of the fundamental frequency

Figure 3.24.: Waveform of collector current at the Carry- and Peak-Transistor

(a) PAE (b) Gain

(41)

Figure 3.26.: Output power, PAE, Gain versus input power [10]

The design in this section is quite easy to understand and straightforward, but this also has some disadvantages:

• Using the S-Paramter simulation is not particularly useful for designing high power amplifier.

• The performance of the design depends heavily on the accuracy of each discrete components.

• Realization with discrete components and microstrip lines can be a major challenge, because of the physical form of the components.

• The mircostrip lines between the discrete components are not taken in to account in the simulation, and may cause undesired effects on the performance. • The calculation of load impedance only concerns the resistive impedance, while at high frequency the imagine part of load impedance also has great influent on performance of the transistor.

• The HF-bypass capacitors have a value of 100 pF and at 900 MHz it is quite difficult to acquire a capacitor, which has this capacitance. The typical limit value for capacitor at this frequency is 10 pF.

• The quarter wavelength microstrip line filter at collector output can only fil-ter the even harmonic frequency and its effect reduces with the increasing frequency because of the inaccuracy of circuit fabrication.

(42)

technique

4.1. Quality factor Q

Quality factor is defined as the ratio of the stored energy and the average dissipated power multiplied by the frequency.

Q = ω0·

Estored Eloss

(4.1) Noted ω0 is the resonant frequency of a resonant circuit.Regarding a parallel config-uration with a resistor, a capacitor and an inductor in parallel, the equation for the Q is shown Qp = R pL/C = R ω0L = ω0RC (4.2)

and the Q factor for the configuration of RLC in series is Qs=

pL/C

R (4.3)

The Q Factor is very important at RF, where all the parasitic elements of package and environment have a significant influence on performance of the circuit. In Fig-ure 4.1 is models of capacitor and inductor at RF. The ESR denotes the resistive impedance of parasitic element. Each capacitor and inductor has a self-resonant frequency, where capacitor becomes inductor and inductor becomes capacitor be-cause of the parasitic capacitor and inductor. Figure 4.2 illustrates the insertion loss of capacitor depend on frequency, this leads to problem with choosing a usable

(a) Capacitor RF model (b) Inductor RF model

(43)

Figure 4.2.: Insertion loss of capacitor [Murata-Data sheet]

capacitor for the design in chapter 2, the lowest peak of insertion loss denotes the self-resonant frequency of capacitor. In Figure is a measurement result of a 220 nF capacitor, the result shows that at 900 MHz the capacitor is already a inductor.

(44)

4.2. Power Amplifier design with Load-Pull

Technique

For designing power amplifier, using the conjugated complex impedance with S-Parameter simulation to achieve low noise and maximal power is not so useful, be-cause the S-Parameter simulation only shows the small-signal response of amplifier in a 50Ω environment as a function of frequency and bias point. Due to non-ideal effects, including transistor parasitics, finite RF choke inductance and bias networks, classical design with S-Parameter can not predict well for realistic large-signal op-eration of RF PA device.

Design-key to achieve the maximal output power with power amplifier is to present a optimum source and load- impedance to the transistor amplifier. Load-pull analy-sis is a method for characterizing nonlinear behavior of high-power trananaly-sistor under large signal, this information is used to determine the optimum source and load-impedance for the desired performance.

The load-pull technique is essentially, a process of varying the impedance seen by

Figure 4.4.: Block diagram of a load-pull system[19]

the output of an active device to other than 50Ω in order to measure performance parameters. The data are plotted on a Smith chart as contours, which directly helps finding out the optimal load impedance, normally the decision is based on trade-off between the output power and PAE1, where the PAE is calculated as:

P AE = Pout− Pin PDC

(4.4) In Figure 4.4 is a simplified diagram of a load-pull system. The power transistor is placed at DUT2 , the bias voltage and supply voltage are set up as a desired working condition. A pair of tuner at input and output are used to vary the input

1_{Power Added Efficiency} 2_{Device Under Test}

(45)

and output impedance. The accuracy of load-pull measurement is highly depended on the tuner, for high repeatability measurement data a precision tuner is needed. The active transistor’s performance data will be acquired while the tuner varies its impedances, the entire process is controlled by a computer. The real hardware load-pull measurement is highly recommended for designing high frequency high power amplifier, which requires high reliable data, although this method is high cost and requires large amount of time.

There is a alternative for hardware load-pull measurement, in this thesis the ”vir-tual impedance tuner” embedded in the circuit simulator of Agilent’s ADS3 is used, while the Load-Pull Simulation in ADS does not calculate the collector efficiency, the PAE can be used to determine the desired collector efficiency. This load-pull simulation utilizes the fast computation power of EDA, but it depends on the accu-racy and availability of large-signal transistor model. This is a biggest disadvantage of virtual load-pull measurement, because most of the semiconductor manufacturer only provides the small-signal transistor model, and the large-signal model is not so accuracy.

With the load-pull method, the goal for design is concentrated on maximal output power, therefore the input and output matching maybe poor, because it is inten-tionally mismatched in order to achieve maximal RF power generation. The results from the Load-Pull simulation are the impedance of source ZS and the impedance of load ZL(Figure 4.5), which are needed to be presented at the base and the collector nodes of the transistor to achieve the desired output power and PAE.

Figure 4.5.: Results of load-pull technique

4.3. Design parameters

The Doherty amplifier design in this section is aimed to have the first peak of collector efficiency at 0 dBm input power and the second peak at 3 dBm input power like in the design with analytic method. Therefore, the bias voltage for the carry transistor remains the same 0.7V as in the previous chapter, as well as the supply voltage of 2.7 V. The result from load pull simulation in Figure A.1 shows that the carry transistor can deliver 17.89 dBm maximal output power and have the PAE of 50.2%

(46)

(a) Collector efficiency (b) Pout, Gain

Figure 4.6.: Measurement results from test device Carry-V4B, measurement 1

Figure 4.7.: Measurement results from test device Carry-V4B, measurement 2

at 3 dBm input power. At the maximal output power of the Doherty amplifier the carry transistor only needs to deliver 17 dBm output power at 3 dBm input power (Section 3.1), therefore the load impedance can be moved to further outside of the middle of the output power contour toward the center of the PAE contour. Figure A.2 shows the pair of source and load impedances, which are needed to present at the base and collector nodes of the transistor, is:

ZS,B,V 4 = 10.50 − j6.6[Ω] ZL,B,V 4 = 66.398 + j10.26[Ω]

Figure 4.6 shows that with ZS,B,V 4 and ZL,B,V 4 the carry amplifier can not able to deliver 17 dBm output power with 3 dBm input power and the collector efficiency is only about 35%. The supply voltage was varied to determine the new working condition for the amplifier. The new 5 V supply voltage was chosen, because of its high efficiency 30% and relatively high output power about 15 dBm. Figure A.5 displays the load pull simulation results with the new supply voltage, from Figure A.6 the new pair of source and load impedance for the carry amplifier is:

ZS,B,V 5 = 7.96 − j5.63[Ω] ZL,B,V 5 = 108.46 + j55.464[Ω]

The design for the peak amplifier is made before the measurement on the test device Carry-V4B and because of the time limit the design for the peak amplifier is not

(47)

optimized for the new supply voltage. The result in Figure A.3 shows with 0.3 V bias and 2.7 V supply voltage the peak transistor only deliver maximum -12.38 dBm output power with PAE of −37.97% at 3 dBm input power. The decision of source and load impedance is made based on the best possible combination of output power and PAE, therefore the chosen pair of source and load impedances is:

ZS,C,V 4= 6.97 − j69.01[Ω] ZL,C,V 4= 96.3 + j60.186[Ω]

The measurement experiments show that, the peak transistor can work with this configuration but only with higher bias and supply voltages. Table 4.1 shows the summary of the source and load impedances, which are used to design the amplifier, the values of bias and supply voltages are the ones, which are used in the load pull simulation.

Device ZS[Ω] ZL[Ω] Bias, sim[V] Supply, sim[V]

Carry-V4 10.50 -j6.6 66.398+j10.26 0.7 2.7

Carry-V5 7.96-j5.63 108.46+j55.46 0.7 5

Peak-V4 6.97-j69.01 96.3+j60.186 0.3 2.7

Table 4.1.: Summary of source and load impedance for design

4.4. Amplifier design

4.4.1. Carry amplifier V4

To start with the design of the input matching network, the source impedance ZS,B,V 4 = (10.50 − j6.6)Ω is conjugated, i.e. Z´S,B,V 4 = (10.50 + j6.6)Ω. Using the function SmithChart from ADS, the matching network is designed to trans-form a 50Ω to ´ZS,B,V 4. A DC-Block capacitor is integrated into the input matching network, with the visual advantage of the SmithChart the value of the DC-Block capacitor can be chosen, so that the variance of the capacitor value only has mini-mum affection on the accuracy of the matching network, in this case the value of the capacitor can range from 6 µF to 9 µF without causing any sufficient degradation on the matching network. The biasing network can also be a part of the input network, this can be useful in some circumstances. Using the function LineCal from ADS the input matching network is synthesized into a circuit, which shown in Figure 4.8. Later a physical layout of the input matching network is made (Figure 4.10(a)), there are some differences in the actually physical size of the elements in comparison with the ideal strip line model. The results in Figure 4.10(b) is from the simulation with the physical layout. A small input matching network is made to compare the accuracy of this design method with the actually hardware, the results in Figure 4.9 confirm the precision of the design process.

The design of the output matching network for the carry amplifier follows the same procedure like the input matching network, the conjugated load impedance

(48)

Figure 4.8.: Schematic of input matching for carry V4

Figure 4.9.: Comparison between software simulation and hardware measure-ment of the carry input matching network V4 , Simulation-Line, Hardware-Symbol

´

ZL,B,V 4 = (66.398 − j10.26)Ω is used to design the output matching network, ex-cepted that at the output network a filter for the harmonic frequencies is needed. The filter for the harmonic frequencies can be a part of the matching network or im-plemented separated as a Harmonic Termination Network(HTN), such network was used in the research [4] to achieve the optimum filter for the harmonic frequencies. Because the lack of time and to simplify the design process only a simple filter with quarter wavelength is used. Figure 4.11 shows the schematic of the output matching network, in Figure 4.12(a) is the physical layout of the matching network, and in Figure 4.12(b) is the S-Parameter simulation result. Even though the filter network is quite simple, its result is good enough to filter the second and third harmonic frequencies.

One of the aspect, which was not taken into account with the load pull simulation, is stability factor of the amplifier. Figure 4.13(a) displays the result of stability fac-tor calculation using the function StabFact from ADS, there is a major problem with the stability in the low frequency region, the early prototype of the Carry amplifier V4 also confirms this problem during the test measurement. Normally the open loop design of amplifier should not cause any problem with the stability factor, but in this case the Miller capacitor between the collector and the base and the parasitic elements of the transistor package cause the unwanted feed-back from the collector to the base. In the low frequency region the reactance of the 7 µF DC-Block capac-itor in the input and output network is too high, therefore the low frequency wave component can not be terminated to ground. To solve this problem a 470 nF and a

(49)

(a) Layout (b) Simulation results

Figure 4.10.: Layout and S-Parameter simulation result of the carry input matching network V4

Figure 4.11.: Schematic of the output matching network for carry amplifier V4D

1 nF are implemented into the input and output network, also the bias and supply network are enhanced with large capacitors to create a short-cut to ground for the low frequency wave. At high frequency region most of the new added capacitors have already lost the property of capacitor, therefore there is no unwanted effect on the accuracy of the matching networks. Figure 4.13(b) shows the improvement of the stability factor after stabilization procedure, the stability factor is now above 1 for all frequencies. The final design for the carry amplifier V4D is shown in Figure B.2.

(50)

Figure 4.12.: Layout and S-Parameter simulation of the carry output matching network V4D

(a) Before stabilization (b) After stabilization

(51)

4.4.2. Carry amplifier V5, Peak amplifier V4 and Doherty

amplifier

The designs of the carry amplifier V5 and the peak amplifier V4 follow the same procedure as one of the carry amplifier V4, but because of the time limit the output network of the peak amplifier V4 does not have any improvement on filter charac-teristic. Note that the improvements on the stability property of the amplifier for the carry amplifier V5 and the peak amplifier V4 are taken over from the design of the carry amplifier V4.

In Figures 4.14 and 4.16 are the schematics of the input and output networks

Figure 4.14.: Schematic of the input network for the carry amplifier V5

for the carry amplifier V5, their physical layout and S-Parameter simulations results are shown in Figure 4.15 and 4.17, respectively. The complete design for the carry amplifier V5 is shown in Figure B.3.

Figure 4.18 shows the schematic of the input network for the peak amplifier V4, while the schematic of the output network is shown in Figure 4.20. The physical layouts and S-Parameter simulation results of the peak amplifier’s input and output networks are illustrated in Figure 4.19 and Figure 4.21, in the order as mentioned. The final design of the peak amplifier V4 is displayed in Figure B.4.

The designs of the carry amplifier V4 and the peak amplifier V4 are combined using the input and output network of the Doherty amplifier (Section 3.2) to form the Doherty amplifier V1B, while the design of the Doherty amplifier V2B is created using the designs of the carry amplifier V5 and the peak amplifier V4. The phys-ical layouts of the Doherty amplifier V1B and V2B are shown in Figure B.5, B.6, respectively. Because the inaccuracy of the AT42086’s CAD model for high power signal, the performance of the designs can not be evaluated based on the simulation results, therefore both of these two designs are fabricated for hardware measurement and analysis.

(52)

Figure 4.15.: Layout and S-Parameter simulation results of the input network for the carry amplifier V5

(53)

Figure 4.17.: Layout and S-Parameter simulation results of the output network for the carry amplifier V5

Figure 4.18.: Schematic of the input network for the peak amplifier V4

Figure 4.19.: Layout and S-Parameter simulation results of the input network for the peak amplifier V4

(54)

Figure 4.20.: Schematic of the output network for the peak amplifier V4

Figure 4.21.: Layout and S-Parameter simulation results of the output network for the peak amplifier V4

(55)

4.5. Performance review

4.5.1. DC current behavior

Figure 4.22.: Collector current versus base voltage of AT42086, with 2.7V Vcc supply

A small test circuit is made to test the accuracy of the available CAD model of the AT42086 transistor. Figure 4.22 shows that the slopes of both collector currents are the same, but the real AT42086 has the lower ”knee” base voltage than the one from CAE model, hence, the real AT42086 offers better linearity character than the CAD model, this property is confirmed through all the measurements with hardware.

4.5.2. Carry amplifier

Figure 4.23.: Measurement setup

The measurement setup is shown in Figure 4.23, the spectrum analyzer has a 50 Ω input impedance. For convenient reason the measurement results of the carry amplifier V4 are plotted again in Figure 4.24. Figures 4.25(a) and 4.26(a) show, that the carry amplifier V5A reaches its maximum efficiency at Pin= 3 dBm and 5 V supply voltage as expected, but the output power is only 14dBm (Figure 4.25(b)), lower than the output power of 15.5 dBm shown in Figure 4.7(b). The comparison between the linearity of the carry amplifier V4 and the carry amplifier V5 in Figure 4.24(b) and Figure 4.25(b) shows that the version V4 has better linear property than the version V5. All the results of the collector efficiency measurements indicate, that

(56)

Figure 4.24.: Measurement results from test device Carry-V4B

Figure 4.25.: Measurement results from test device Carry-V5A with 5V supply voltage

Figure 4.26.: Measurement results from test device Carry-V5A with different supply voltages, Pin= 3dBm

(57)

Figure 4.27.: Measurement results from test device Carry-V5A with different supply voltages, Pin= 6dBm

the transistor AT42086 in class B configuration only has the maximum collector efficiency about 32%. According to the results shown in Figure 4.27, to achieve the 17 dBm output power the input power must be increased to 6 dBm and the supply voltage to 7.5 V.

4.5.3. Peak amplifier

The peak amplifier is designed to have its maximum collector efficiency at Pin = 3 dBm, therefore as shown in Figure 4.28 the bias voltage and the supply voltage are chosen to be 0.5 V and 5 V, respectively. Also the measurement results show that the maximum collector efficiency of the peak amplifier V4 is about 45%.

(58)

(a)

(b)

(c)

Figure 4.28.: Measurement results from test device Peak-V4 with different bias voltages

(59)

4.5.4. Doherty amplifier

Note that after the input network of the Doherty amplifier each amplifier only re-ceives the half of the input power, therefore if the amplifier is design to reach its maximum output power at 3 dBm in Section 4.4 then the actually input power of the Doherty amplifier must be at least 6 dBm. All the collector current values, which are measured, are DC-current values, but because of the relationship between the DC current and the AC current shown in (2.2) and (2.3) these values are still valid for the analysis.

The collector efficiencies in Figure 4.29 and Figure 4.30 have two peaks of efficiency with different values, the distance between the two peaks is exactly the same as predicted in Section 2.3.5, 3 dBm versus Pinand 6 dBm versus Pout, and the second peak of efficiency is not occurred at Pout = 20 dBm. With the reducing bias for the peak amplifier, the first peak of efficiency is increased, but the linearity and the second peak efficiency of the amplifier is reduced, also the carry amplifier’s collector current is able to reach a higher value. Figure 4.29(d) and Figure 4.30(d) show, there is a ”dip” in the course of the carry amplifier’s collector current, when the peak amplifier begins to conduct.

Figure 4.31(a) and 4.32(a) show, that the Doherty amplifier at Pin = 3 dBm has already reached its first peak efficiency, which is too soon, this explains the low values of the amplifier’s collector efficiency. This may be caused by the high bias of the peak amplifier, from Figure 4.31(d) and Figure 4.32(d) the peak amplifier begins to conduct before the carry amplifier’s collector current reaches its maximum values, unlike the behaviors of the collector current of the Doherty amplifier V1B in Figure 4.29(d) and 4.30(d). With the reduced bias voltage for the peak amplifier, the collector efficiency is able to reach the maximum value of 25% (Figure 4.33), but the development of the collector currents still does not have the characteristic of a Doherty amplifier. Overall the DC values of V2B amplifier’s collector current are too high in comparison with the DC values of the V1B amplifier’s collector currents. The version V2B has a lower gain factor than the gain factor of the version 1B, but the gain factors of both amplifiers V1B and V2B are still lower than expected, therefore the input power level must be higher in oder to reach the maximum output power level of 20 dBm. It appears that at high power level the transistor has reached the compression, because of the drop in the gain factor.

Compared the performance of the version V1B and V2B shows that the version V1B has a better controlled performance as calculated and a higher collector efficiency.

(60)

(a) (b)

(c) (d)

Figure 4.29.: Measurement results of Doherty amplifier V1B

(a) (b)

(c) (d)

(61)

(a) (b)

(c) (d)

Figure 4.31.: Measurement results of Doherty amplifier V2B

(a) (b)

(c) (d)

(62)

(a) (b)

(c) (d)

(63)

Recommendations

5.1. Conclusions

The objective of this thesis is to investigate the operation of the classical Doherty amplifier and the development of a 900 MHz Doherty amplifier, which is capable of delivering 20 dBm at its peak efficiency.

The functionality and support theory of the Doherty amplifier are first analyzed in Chapter 2. Analysis and design equation based on the classical assumption are given.

In Chapter 3 a design with the available CAD model is given using the analytic method. This design delivers a deeper understanding of the functionality of a tran-sistor with different bias configuration and the usage of the matching network in achieve matched condition between source and input of the amplifier for maximum output power. The relation between stability factor and gain shows a typical prob-lem with the design of amplifier, in the case of the carry amplifier a compromise was made to achieve a stability working behavior of the amplifier while ensure the high output power. A S-Parameter simulation is used to determine the effect of the matching network on phase response of the amplifier, this information was used to design the input network for the Doherty amplifier, to make sure that at the load impedance the signal from the carry and peak amplifier combine in-phase for the maximum output power. The problems with the leakage between the carry and peak amplifier as well as the finite saturated voltage VCE and their influent on the resulting collector efficiency of the amplifier are shown in the simulation result. The simulation design has a maximum collector efficiency above 50% and delivers 20 dBm output power with 6.5 dBm input power. The difficulty with the realization of simulation into hardware and the inaccuracy of S-Parameter simulation for high power signal have led to a new approach on the amplifier design in Chapter4. Amplifier design with load pull technique is one of the widely used methods in design a high power amplifier. It is used to determine the optimum working con-dition, in which the amplifier has its maximum output power with the optimum efficiency. Using the load pull technique on the amplifier device results in not only the real impedance part but also the imagine reactance part of the source and load impedance, which is very important in high power and high frequency power am-plifier. With the advance of knowing the exact impedances, which are needed to be presented to the transistor, the matching network can be designed to eliminate the unwanted influence of component’s tolerance while including some extra useful attributes like filter characteristic, but the design process requires more time