INTRODUCING THE LS1012A, THE WORLD'S SMALLEST AND LOWEST POWER 64-BIT PROCESSOR

JIM BRIDGEWATER PRESENTER TITLE NXPFTF-NET-N1865 DAY, MONTH, YEAR

NXPFTF-NET-N1865

INTRODUCING THE LS1012A, THE

WORLD'S SMALLEST AND LOWEST

POWER 64-BIT PROCESSOR

PUBLIC USE

1 PUBLIC USE #NXPFTF 1

AGENDA

•

Introduction to the LS1012A architecture and

schedule

•

Identify target markets and differentiating features

•

Describe NXP enablement plans

LS1012A Block Diagram

• Single ARMv8 64-bit Cortex-A53 processor

• 1840 DMIPS / 2240 Coremark @ 800MHz

• NEON Co-processor and DP FPU

• 256 KB L2 cache with ECC

• Memory Controller

• DDR3L up to 1000 MHz

• 16-bit data bus, 1 chip select

• High Speed Interconnect

• 1x PCI Express Gen2

• 1x SATA Gen3

• 1x USB 3.0 w/PHY

• 1x USB 2.0 w/ULPI

• Ethernet Packet Accelerator

• 2x GbE (2.5G or 1G)

• Datapath

• Packet Acceleration Engine (PPFE)

• Security acceleration engine (SEC)

• 2x SD 3.0/SDIO/eMMC

• QSPI, 1x SPI, 2x UART, 2x I2C

• 2x I2S, 5x SAI

CCI-400 Coherent Interconnect

Secure Boot Trust Zone Power Management 2x SD 3.0/SDIO/eMMC 2x I2C 2x I2S, 5x SAI QSPI, 1x SPI 2x UART 64-bit DDR2/3 Memory Controller 16-bit DDR3L Memory Controller 64KB SRAM GPIO, JTAG SEC 256KB L2 ARM Cortex-A53 32KB L1-D 32KB L1-I 1x USB3.0 + PHY 3-Lane 6GHz SERDES PCIe 2 .0 PPFE SAT A 3 .0 G b E G b E 1x USB2.0 Sec Monitor

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LS1012A High Level Features

• Processor Complex

− 64-bit ARM Cortex-A53 up to 800 MHz

 >2200 Coremarks under 2W

 NEON SimD / DP FPU

 32KB/32KB L1 Parity protected Cache & 256KB L2 Cache with ECC

• Data Interfaces (up to 2x 6GHz SerDes Lanes)

− 2x Gb Ethernet (2.5G/1G) − 1x USB3.0 w/PHY − 1x USB2.0 w/ULPI − 1x PCIe Gen2 (5 GHz) (x1) − 1x SATA-3 (6 GHz) • Memory Interfaces

− QSPI (NOR flash)

− 1x SPI − 2x SDIO 3.0 − DDR3L-1066 MHz (16b) • Control I/Os − 2x I2C, 1x SPI − 2x UARTs − 2x I2S, 5x SAI − Watchdog/Timers

− 16 dedicated GPIOs, 6 PWM Capable

• Packet Acceleration

− Packet Acceleration Engine

 2Gbps of PPPoE/NAT routing with 390B packets

 RSO/LRO offload

− Hardware Security Engine  400 MB/s block mode encryption

 AES256 CBC, ECB, XTS

 XOR

• Hardware/Silicon Security

− Secure Boot, JTAG Blocking, 8Kb OTP Memory

− ARM TrustZone + Trust Architecture

− DRM compliance • Battery Operation

− Dynamic Frequency Scaling (DFS) with integrated power management

LS1012A Packet Forwarding Engine - Performance Estimates

•

NAT routing targets should be achieved with minimal CPU impact for IPV4/6

acceleration

Ethernet to Ethernet: NAT Routing

Frame Size Bi-dir thruput (IPV4) – Mbps Bi-dir thruput (IPV6) -Mbps CPU utilization target 64 2000 2000 <5% 128 2000 2000 <5% 256 2000 2000 <5% 512 2000 2000 <5% 1024 2000 2000 <5%

TCP (ac) UPD (ac) TCP (n+ac) UDP (n+ac)

TX Target 850 956 1050 1200 RX Target 850 957 1050 1200 0 200 400 600 800 1000 1200 1400 T hrup ut M bp s WLAN to Ethernet

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LS1012A Ultra-low form-factor package

•

Innovative Laminate BGA Technology

−

Signal pins in outer two pad rows with 0.5mm pitch

−

Inner balls with 0.8mm pitch used only for power and ground

•

Supports cost-effective 4-layer PCB

•

Enables designs with severe space constraints

9.6mm

LS1012A Power Management Features

•

Packet-forwarding engine offloads CPU and reduces power consumption

•

Typical 1W power consumption when active

•

Dynamic Frequency Scaling

•

On-chip temperature monitor

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A53

Internal BootROM

Security Fuse Processor

PPFE DDRC TZASC SEC 5.5 IPsec ucode Security Monitor Secure Debug Ctrl HP_TMP PROG_SFP DESA AESA Job Queue Controller DECO DM A RT IC MDHA PKHA RNG

LS1012A Security & Trust Architecture Features

OCRAM T ZPC T ZM A

Security Capabilities Supported

• Secure boot – hardware root

of trust

• Secure key handling

• Tamper detection

• Secure manufacturing

• Secure debug

• ARM TrustZone

LS1012A Cryptographic Acceleration features

CHAs DESA AESA Job Queue Controller Descriptor Controller DMA RT IC MDHA PKHA RNG

Job Ring I/F

(1) Public Key Hardware Accelerator (PKHA)

•RSA and Diffie-Hellman (to 4096b) •Elliptic curve cryptography (1024b) •Supports Run Time Equalization

(1) Random Number Generator (RNG)

•NIST Certified

•RNGB in P1010, RNG4 in PSC9131

(1) Message Digest Hardware Accelerators (MDHA)

•SHA-1, SHA-2 256,384,512-bit digests • MD5 128-bit digest

•HMAC with all algorithms

(1) Advanced Encryption Standard Accelerators (AESA)

•Key lengths of 128-, 192-, and 256-bit

•ECB, CBC, CTR, CCM, GCM, CMAC, OFB, CFB, and XTS

(1) Data Encryption Standard Accelerators (DESA)

•DES, 3DES (2K, 3K) •ECB, CBC, OFB modes

Function Rate (Gbps)

AES 1.6

3DES 1.4

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LS1012A

LS1012A-RDB board

Features • 128MB NOR Flash • 256MB DDR3L DRAM • 2x GbE • 1x mPCIe • 1x SATA • USB3.0 • USB2.0 • KW41Z 2.4GHz radio

supports Thread & Bluetooth Low Energy

• Arduino Shield header for

expansion LS1012A KW41Z BLE / Thread SDHC2 eMMC memory SDIO Wi-Fi Module Arduino Shield Header RGMII 256MB 16b DRAM 128MB NOR Flash QuadSPI DDR3L PCIe Half-height mPCIe Connector GbE PHY I2_C1 SAI2 GbE SATA3 SATA SGMII GbE GbE PHY

USB2.0 & 3.0 USB

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LS1012A-RDB

mPCIe Slot 1 GbE 1 GbE SD card Slot Arduino Shield SATA WiFi US B KW41Z

LS1012A Software Offering

Software Platform Description Pricing Enables

SDK (Yocto-based) • General-purpose Linux SDK,

supporting all QorIQ processors • Yocto build environment

• Free of charge • Scalable networking,

industrial and consumer applications

• Migration from older QorIQ devices

Application Solution Kit (BHR)

• Optimized Linux networking solution with hardware packet acceleration

• OpenWRT build environment

• $10,000 for source code • Binary image

free of charge

High performance and fast time to market for broadband

networking applications such as gateways & routers

Application Solution Kit (NAS)

• Optimized Linux networking solution with hardware packet acceleration

• $10,000 for source code • Binary image

High performance and fast time to market for consumer network attached storage & other HDD

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ASK Pricing

Part number Resale Price

Description Tech support by

FAE/DFAE/ TIC

Support & Maintenance by Factory Software Team

LS1012A-SW-ASK $10,000 LS1012A OpenWRT Linux Application Solution Kit (ASK) Yes Not Included

*VoIP firmware and Packet forwarding Engine firmware are always supplied as binary libraries

ASK licensing

Part number Description Tech support by

FAE/DFAE/ TIC

Support & Maintenance by Factory Software Team

ASK-SERVICE LS1012A Software Feature Request NRE Yes Included in Premium Level Support

NRE features

Part number Resale Price

Description Ability to request

custom features

Support & Maintenance by Factory Software Team

LS1012A-SWSP-PRM $50,000 LS1012A Software Support Plan - Premium Level 250 Hours / 12 Months

Yes Yes

LS1012A-SWSP-PLS $25,000 LS1012A Software Support Plan - Plus Level 100 hours / 12 months

No Yes

Software Commercial Support Program

Support Level Premium Plus

Part Numbers LS1012A-SWSP-PRM LS1012A-SWSP-PLS

New ASK software releases* _{● ●}

Assigned a Voucher ID for

software support issues ● ●

Access to test codes to facilitate

early feature integration ● ●

Ability to request custom features _●

Software support hours included _{250 100}

Annual Fee _{$50,000 $25,000}

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LS1012A Timeline

Q1 Q2 Q3 Q4

Mar Apr May Jun Jul Aug

NXP TechForum

May 16-19, Austin

Press Announcement

Feb 22, Embedded World Nuremberg, Germany Jan Feb LS1012A Samples LS1012A RDB Samples Sep Channel Launch Oct Nov LS1012A RDB Production LS1012A Production Software EAR-1 Software EAR-2 Software Alpha Software Rev0.6

TARGET MARKETS &

DIFFERENTIATED

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LS1012A Differentiated Features & Target Applications

Performance starts with the core

• First 64-bit ARM Cortex-A53 core to be offered in a sub- 10x10 mm

package, delivering over 2,000 CoreMark®_{of performance at 1W (typical)}

for outstanding performance at exceptionally low power utilization

• Best in class 2.5 CoreMark / mW ratio

Broadest range of peripheral and I/O features in the sub-$10 ASP price range

• Only product in its class to offer Packet Acceleration for IP forwarding and NAS, delivering ourstanding packet throughput for this power/package envelope

• Trust and Security acceleration enables root of trust and high

performance encryption consistent with much higher cost microprocessors • First in its class to offer 64-bit support for battery powered mobile

applications and performance efficiency

• Only 1W 64-bit processor to combine USB 3.0 with integrated PHY, PCIe, 2.5 Gigabit Ethernet and SATA3 on a single SoC to enable lower system-level costs

• Enables low-cost, 4-layer board level designs together with high system level integration to support ultra-small form factor systems

LS1012A Target Applications

Consumer NAS

Value tier IOT gateway

Battery Powered Mobile NAS Entry BB Ethernet Gateway Trusted Gateway

Industrial Automation & Control Building Control systems

Ethernet Drives Networked Audio DDR3L Controller L2 Cache w/ECC USB3.0 w/PHY Cortex-A53 ARMv8 64b Core L1 Cache w/ECC Serial IO PCIe SATA 3 1x GbE Packet Engine Security Engine

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IOT Gateway Use Case

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Consumer NAS/DAS Use Case

Consumer NAS/DAS w/optional Wi-Fi

Ethernet Drive and USB to SATA DAS Use Cases

Ethernet Drive

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Battery Powered Portable NAS Use Case

Portable NAS/Router with battery power option

BB Ethernet Gateway Use Case

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Collateral

•

Available Now on Extranet:

−

Datasheet (preliminary)

−

Reference Manual (preliminary)

•

Going Live on 22

nd

_February:

−

Press release

−

Product Summary Page

−

Fact Sheet

•

Available by channel launch:

−

Tools Summary Page

−

LS1012A-RDB & documentation

−

Videos

−

White Papers

−

Application Notes

−

Kill sheets

−

Distributor communicator

−

Demos

−

Blogs

3

rd

Party Support

•

We are currently in discussion with the following 3

rd

_{parties to support LS1012A:}

−

WindRiver: WRLinux & VxWorks

−

Mentor Graphics

−

MontaVista

−

Multiple EBS partners

−

ODMs in Taiwan

−

Greenhills

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Part Numbers

•

Evaluation board:

LS1012ARDB

: $495 Resale

•

Extended temp part numbers to follow later.

LS1012 Family Part Numbers

Device Part Number TEMP Security CPU / DDR LS1012A

LS1012ASN7EKA S N 600/1000

LS1012ASN7HKA S N 800/1000

LS1012ASE7EKA S E 600/1000

SUMMARY & CALL

TO ACTION

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LS1012A Summary

•

LS1012A is the world’s smallest and lowest power 64-bit processor

•

LS1012A brings line-rate networking performance to

−

IOT Gateways

−

Networked Audio

−

Industrial control

−

Ethernet drives

−

Etc

•

Press announcement on 22

nd

_February

Call to action

•

Promote the LS1012A to your customers!

•

Look for key customers for early engagement

•

Part numbers are active – please register opportunities in CRM

•

Make sure your local distributor branch offices are aware

PRESENTER NAME PRESENTER TITLE NXPFTF-NET-N1865 DAY, MONTH, YEAR

NXPFTF-NET-N1865

LS1012A OVERVIEW

TECHNICAL SESSION

PUBLIC USE

33 PUBLIC USE #NXPFTF 33

AGENDA

•

Introduction to the LS1012A architecture details

−

Interfaces, Clocking, SerDes, POR, Boot sequence, pin

mux, etc

•

Enablement Tools and Board Bring up

LS1012A Block Diagram

• Single ARMv8 64-bit Cortex-A53 processor

• 1840 DMIPS / 2240 Coremark @ 800MHz

• NEON Co-processor and DP FPU

• 256 KB L2 cache with ECC

• Memory Controller

• DDR3L up to 1000 MHz

• 16-bit data bus, 1 chip select

• High Speed Interconnect

• 1x PCI Express Gen2

• 1x SATA Gen3

• 1x USB 3.0 w/PHY

• 1x USB 2.0 w/ULPI

• Ethernet Packet Accelerator

• 2x GbE (2.5G or 1G)

• 1 RGMII

• Datapath

• Packet Acceleration Engine (PPFE)

• Security acceleration engine (SEC)

CCI-400 Coherent Interconnect

Secure Boot Trust Zone Power Management 2x SD 3.0/SDIO/eMMC 2x I2C 2x I2S, 5x SAI QSPI, 1x SPI 2x UART 64-bit DDR2/3 Memory Controller 16-bit DDR3L Memory Controller 64KB SRAM GPIO, JTAG SEC 256KB L2 ARM Cortex-A53 32KB L1-D 32KB L1-I 1x USB3.0 + PHY 3-Lane 6GHz SERDES PCIe 2 .0 PPFE SAT A 3 .0 G b E G b E 1x USB2.0 Sec Monitor

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Summary of Key Differences from existing Products

Feature LS1012A LS1024A LS1021A

CPU/number of cores ARMv8 - A53; single core ARMv7: dual-core Cortex A9 ARMv7: Dual core; Cortex A7

Interconnect _{CCI-400 AMBA AXI/AHB @250MHz CCI-400}

Frequency(Core/Platform/DDR) (MHz) 800/250/500 1200/500/533 1000/300/1600

Clocking Single source Crystal Oscillator Single source Crystal Oscillator

DDR _{DDR3L (MMDC) DDR3 DDR4}

Network/Packet processing PFE PFE eTSEC 2.0

Crypto SEC Third-party IP block SEC

PCIe _{Gen 2 Gen 2 Gen 2} SATA _{Gen 3 Gen 3 Gen 3}

USB 3.0/USB 2.0 _{Y Y (incl PHYs) Y}

eSDHC _{Y N Y}

SPI/I2C/QSPI/FTM/SAI/GPIO SPIx1, QSPI, I2Cx2, FTMx2, SAIx5, GPIO

SPIx2, I2C, GPIO SPI, QSPI, I2C, FTM, FlexCAN, SAI, GPIO

Boot Sources _{QSPI (using PBL) NOR, I2C, SPI, UART, SATA QSPI/IFC/SD MMC (using PBL)}

Secure Boot _{Y Y Y}

IOMMU _{N (CSU for resource partition) N Yes (PAMU)}

ARM Trust Zone _{ARMv8 Trust Arch Y N}

Power/Size/Pin Count <3W/9.6mm * 9.6mm/ 211 4Wtyp/21x21mm/625 3.68/19mm x19mm/525

Package Type FC-LGA FCPBGAH FC-PBGA

Key differentiators ARMv8, 64 bit Low cost Low Power Truly single source

125M RGMII ref CLK

LS1012A Single Source Clocking Scheme

CGA PLL1

/2

EXTAL

A53 Core Cluster

32KB I-Cache 32KB D-Cache 256KB L2 cache PLATFORM PLL /4 Platform clock eSDHC IP Blocks /2 C lock S e le c tion Oscill a to r XTAL 100M Single Ended 125M (SYSCLK) 125M Differential RCW[CGA_P LL1_RAT ] RCW[CGA_P LL1_CFG ] RCW[CGA_P LL1_SPD ] RCW[SYS_PLL_CFG] RCW[SYS_PLL_RAT] RCW[SYS_PLL_SPD] RCW[C1_P LL_SEL ] 500M DDR Controller 1000M QSPI USB PHY 25M input from On board Crystal PFE

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POR Signals considerations

• HRESET_B signal doesn't exist

• RESET_REQ_B signal is multiplexed with QSPI_A_DATA3, GPIO1_14 and IIC2_SDA

− The primary function is QSPI_A_DATA3. If device fails to read RCW, RESET_REQ_B will not be asserted

− RESET_REQ_B may not be available if any of the alternate functions is used

• ASLEEP is multiplexed with USB1_PWRFAULT and GPIO2_01 − Multiplex options can be chosen using RCW

• Crystal Oscillators as the primary source of clock

• Minimum ramp rate for VDD is 0.06V/ms − VDD should ramp up within 16ms

POR Sequence

• PORESET should be asserted when power starts ramping up

• External crystal provides 25 MHz sinusoidal input

• cfg_eng_use and cfg_eng_use_2 are internal POR config pins sampled when VDD ramps up

• The external oscillator may take 2ms – 9ms to produce stable clock • The stable clock is fed to a PLL which outputs 125 MHz clock

− The 125 MHz output is referred as SYSCLK in LS1012 documents

• PORESET is required to asserted for 32 SYSCLKs after stable SYSCLK is available − Minimum assertion time for PORESET is specified as 100 ms in datasheet

• Rest of the POR config signals (cfg_rcw_src) are sampled at PORESET de-assertion

• RCW is read from QSPI

− QSPI is the only external memory for storing RCW

− QSPI block runs at SYSCLK (125 MHz)

• System and Core PLLs starts locking based on RCW fields

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RCW provisions

• LS1012A supports only one RCW source which is QSPI NOR

• The RCW and PBL fetch happens only in 2 bit QSPI mode

• In case of secure boot only 2 bit QSPI is available

• Additionally a provision of 1 Hard coded RCW is there to complete the reset cycle on a bare board.

− Hard-coded RCW option is not recommended as a feature to be used for functional use. It should only be used to restore/program the RCW on blank Flash.

Pin Mux overview and important considerations

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LS1012A SerDes

• Single SerDes module with 3 data lanes supported on the device.

• Two PLL’s used for clocking individual lanes.

• PLL1 Reference Clock pinned out on the package, provides clock to both PLL

• Option to provide PLL1 reference clock (controllable via RCW)

 With an external differential 100 MHz or 125 MHz clock.

 Can be driven internally with a 125MHz clock derived from the 25MHz on chip crystal

oscillator.

• LS1012A supports the following network protocols through SerDes

1. One PCIe (x1) (2.5/5.0 Gbps)  RC/EP support

2. One SATA (1.5/3.0/6.0 Gbps) 3. Upto two 1000 Base-KX

4. Upto two SGMII 2.5G 5. Upto two SGMII

LS1012A SerDes Lane Multiplexing

SRDS_PRTCL_S1

RCW[128:143]

Lane A Lane B Lane C Lane D RGMII Per lane

PLL mapping

Considerations of this SerDes protocol (validate with Mohit S)

0x0000 unused MAC #2 2222 Both PLLs should be powered down using RCW bits SRDS_PLL_PD_S1 (RCW[168:169]) 0x2208 sg.m1 (2.5G) sg.m2 (2.5G) UN USE D

SATA - 1122 2.5G SGMII requires 125MHz SerDes clock input on PLL1

0x0008 Unused Unused SATA MAC #2 1122 PLL1 cannot be powered down as common clock is used.

0x3508 sg.m1 PCIe(x1) SATA MAC #2 1122

0x3305 sg.m1 sg.m2 PCIe(x1) - 2222 PLL1 is unused, should be powered down using using RCW bits SRDS_PLL_PD_S1 (RCW[168:169]) 0x2205 sg.m1

(2.5G)

sg.m2 (2.5G)

PCIe(x1) - 1122 2.5G SGMII requires 125MHz SerDes clock input on PLL1

0x2305 sg.m1 (2.5G)

sg.m2 PCIe(x1) - 1222 2.5G SGMII requires 125MHz SerDes clock input on PLL1

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 TX_CLK is an output signal on one of the 3 Serdes lanes of LS1012A.

 It provides a 100 MHz differential reference clock that can be used by an Endpoint.

 This facilitates a low cost solution by eliminating the need for an onboard clock source for

the EP

SRDS_PRTCL_S1 RCW[128:143]

Lane A Lane B Lane C Lane D Considerations of this SerDes protocol

0x9508 TX_CLK PCIe(x1) SATA 100MHz clock output on Lane A for EP

0x3905 sg.m1 TX_CLK PCIe(x1) 100MHz clock output on Lane B for EP

0x9305 TX_CLK sg.m2 PCIe(x1) 100MHz clock output on Lane A for EP

 RGMII interface is driven by MAC2 of PPFE.

 SGMII on SerDes lane A is driven by MAC1

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MDIO

 MDIO registers have been changed from earlier SoCs  MDIO_CTL and MDIO_DATA are no more there  MDIO driver update is required for LS1012A  MDIO registers in LS1012A are:

 Load the MII Speed Control Register (MSCR)  for MDC configuration

 Load the MII Management Frame Register (MMFR)  For MDIO data transfers

 Interrupt Event Register (EIR)  For MII Event

 These registers have to be programmed by A53 core based on board configuration; they are not configured by PFE Firmware

LS1012A eSDHC

• LS1012A supports two eSDHC interfaces.

eSDHC1:

• Supported primarily for SD cards.

• On the EVDD/O2VDD interface.

• CD/WP/VSEL are at 1.8V.

• Card initialization happens at 3.3V, but can dynamically switch to 1.8V controlled

by the SDHC1_VSEL output pin.

• No provision to select EVDD=1.8V at boot time.

• 4 bit interface

eSDHC2:

• Supported for 1.8V embedded SDIO • 1.8V eMMC.

• On the 1.8V O1VDD voltage domain.

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LS1012A eSDHC interface - Supported SD card modes

Mode eSDHC1 eSDHC2 Comments

SD (SD cards/SDIO cards/embedded SDIO)

SD memory card in Default (25MHz) /

High speed (50MHz) Yes No Cards are supported on_{eSDHC1 interface due to availability of CD and WP pins.} Only embedded devices (SDIO, eMMC) are supported on eSDHC2 interface. Software needs to assume card is always present.

SDIO card in Default(25MHz)/High

speed (50MHz) Yes No SD memory card SDR50 Yes No

Card initialization happens in DS/HS mode at 3.3V and later switches to SDR50 mode at 1.8V

SDIO card

SDR50 Yes No SD memory card DDR50 Yes No

Card initialization happens in DS/HS mode at 3.3V and later switches to DDR50 mode at 1.8V

SDIO card DDR50 Yes No SD memory card SDR104 Yes No

Card initialization happens in DS/HS mode at 3.3V and later switches to SDR104 mode at 1.8V

SDIO card SDR104 Yes No eSDIO SDR50 No Yes

Only 1.8V eSDIO devices supported (on eSDHC2) eSDIO DDR50 No Yes

LS1012A eSDHC interface - Supported MMC/eMMC modes

Mode eSDHC1 eSDHC2 Comments

MMC/ eMMC MMC card in

Default(20MHz)/High speed (52MHz)

No No MMC is not supported.

eMMC DDR mode No Yes

1.8V only eMMC devices supported

eMMC HS200 No Yes

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Other Interfaces

Modes supported/Key aspects about the architecture

• JTAG: Not always available; selected via POR pin, TJTAG_SEL

• SAI

• FTM

• USB

• QSPI: Only 2 bit interface available in Non Secure Boot Use cases

• DSPI: Only Master Mode is supported

• UART

ENABLEMENT TOOLS

&

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CodeWarrior Flash programmer

LS1012A

connected CWTAP QSPI Flash device part number LS1012A QDS connected CWTAP

- Enables bare board QSPI Flash

programming via JTAG

- Provides both command line as well

as GUI versions

Type project name

Choose SoC

QCVS pinmux tool

•

Allows the user to select the

interfaces using a very

convenient GUI

•

Shows the selected as well

as eliminated interfaces.

•

Generates report of the pin

assignments.

PUBLIC USE 53 #NXPFTF SoC peripherals list _{Peripheral no} longer available[grey] Assignable peripheral [black] Assign/remove peripheral button Last assigned peripheral [yellow] Eliminated by last assigned peripheral [yellow]

Snips of the tool exercised on actual Si

Generate Pinmuxing report

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Bring-up tips and tricks

•

How to quickly bring up LS1012A on a new board? (Key points which should be

considered)

On initial boards keep below mentioned provisions to allow quick board bring up and iron out

board/Software issues:

−

Keep an option of Hard coded RCW. (cfg_rcw_src)

−

Keep an option to enable/disable JTAG using TJTAG_EN POR signal for debuggability.

−

The above can be removed on production boards if not required.

•

Take due care of pinmuxing and carefully select the RCW bits. Also be aware of the

constraints.

−

In some cases RESET_REQ_B is not always available to signal internal errors

−

JTAG is muxed so debug of interfaces which are muxed with JTAG cannot be debugged using

JTAG.

•

Keep the Bring-up tools like QCVS and CW Flash programmer handy.

Summary

•

Architecture has been designed to provide Low cost and Low power on 64 bit

ARMv8.

•

Design considerations for each Interface

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What is not supported?

•

DDR: NO ECC

•

No IEEE 1588

•

No HRESET

•

RESET_REQ_B only available in Secure boot

•

ASLEEP muxed with USB

•

JTAG muxed

•

Only 2 bit QSPI available with Secure boot

•

Runtime pinmux provision available for selected signals:

−

QSPI and GPIO

MDC (MSCR Register bit description)

MAC pclk = 250MHz

Ratio for ~2MHz MDC clock = 0x3E (d’62) MDC clock = 250/2(62+1) = 1.984MHz

write_reg (0x4200044

,0x27C)

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MDIO Register Programming Considerations

 If the MSCR register is written to a non-zero value in the case of writing to MMFR when MSCR equals 0, an MII

frame is generated with the data previously written to the MMFR. This allows MMFR and MSCR to be programmed in either order if MSCR is currently zero.

 If the MMFR register is written while frame generation is in progress, the frame contents are altered. So poll

EIR(MII) interrupt indication to avoid writing to the MMFR register while frame generation is in progress.