Evaluating
Embedded Non-Volatile Memory
for 65nm and Beyond
Wlodek Kurjanowicz
DesignCon 2008
© Sidense Corp 2008Agenda
Introduction: Why Embedded NVM?
Embedded Memory Landscape
Antifuse Memory evolution
1.5T cell
1T cell
1T/1.5T comparison
Scaling Challenges
Why Embedded NVM?
Three Basic Rules in Real Estate Investing:
Location (know your Budget)
Location (choose good location)
Location (have a plan in place)
Same rules apply to Silicon Real Estate:
Cost effective NVM for on-chip trimming and repair
Secure NVM for on-chip encryption keys
Reliable and portable NVM for on-chip firmware and
130nm Memory Bit-Cell Comparison
0.13um 5 u m POLY 2umeFUSE IBM System Z9 PGM: 10-15mA / bit
50µm nmos switch READ: <0.5mA / bit
SRAM
D
R
A
M
Floating Gate Logic NVM
Six HV (3.3V) Transistors /bit
6T SRAM 140F2 +2 Masks 1T1C DRAM 12-30F2 +3/5 Masks NOR Flash 10F2 +6/8 Masks 1T Anti-Fuse
>10F2
Mask ROM <10F2
Know Your Budget!
Size Does Matter!
F=1/2 DRAM Pitch
Embedded Memory Landscape
0.13um
5
u
m
POLY
2um
eFUSE
SRAM
D
R
A
M
Floating Gate Logic NVM 6T SRAM
1T1C DRAM
NOR Flash
1T Anti-Fuse
Mask ROM
Security
and
Secure Embedded NVM Landscape
Floating Gate Logic NVM
3.3V Transistors
ECC needed for retention
NOR Flash
+6 / 8 Masks
1T Anti-Fuse
Reliability
and
Portability
Across Fabs
and Process Nodes
What is an Antifuse
A “
structure alterable to a conductive state
”
An electronic device that changes state from not conducting to
conducting or from higher resistance to lower resistance in
response to electrical stress (programming voltage or current).
MOS capacitor is an excellent antifuse
Programmed by
gate oxide rupture
Exact mechanism still not well understood
Gate leakage is in order of pA or nA Oxide breaks down at 5-8V
MOS Antifuse Memory Evolution
1969, Semiconductor Antifuse
Inter-Metal Cap blown at the
row/column cross point
1979, MOS Antifuse
Cap shorted to GND when gate oxide
blown at the tip of the groove
1982, Dual Oxide 1.5T MOS
Antifuse
Gate-Drain shorted in the overlap area,
avalanche enhanced
1985, MOS Cap Antifuse
1986, ONO Antifuse
channel
1T1C (1.5T) Planar DRAM Antifuse
PL0 PL1 WL1 WL0
BL3
BL2
BL1
BL0
1T Thick Gate Oxide Access MOS
1C Thin Gate Oxide Storage MOS
Improved 2-Terminal 1.5T Antifuse
WL1 WL0
BL3
BL2
BL1
BL0
1T Thick Gate Oxide Access MOS
1C Thin Gate Oxide Storage MOS
Programming the Antifuse
• VPP Voltage Level• High enough to break Thin Gate Oxide
• Too low to break Thick Gate Oxide • Permanent Structural Change requires Energy (=V*I*t)
0V
Oxide Rupture Mechanism
Need V, I and time to avoid Soft
Breakdown of gate oxide
Inversion Channel High Electric Field 30MV/cm
n+ Poly
Gate
Communicating traps 2nm+6V
0V
P-Tunneling:
– Fowler-Nordheim – Direct– Trap Assisted
VPP More Tunneling Current Rupture Tmax? New Traps No Yes Soft Breakdown Oxide melts
Nano-scale Crystallization
Oxide melts in the breakdown area
100µA/100nm2 =1A/µm2 =1,000,000A/mm2
N-type Silicon filament is grown
A nano-scale diode-connected NMOS transistor is born
High Current Density
1A/µm2
n+ Poly Gate
P-n
-+6V
0V
+
-
n-p
5-10nm
n
Antifuse
programming
results in
permanent
STRUCTURAL
CHANGE
Where the Gate Oxide Breaks?
1.
Channel
2.
Transition Area (Halo or Pocket Implant)
3.
LDD
Channel
3
N+
2
1
Isol Poly
Gate
LDD
P-LeakageControl
N+
LDD
P-Poly Gate
3 Program Areas
3 cell characteristics!
Sidense Split-Channel 1T-Fuse™ Cell
Diffusion area removed
Portable between fabs
Programs always in
channel area
Permanent structural
change
Consistent cell
characteristic
Reliability = integrity of un-programmed gate oxide Yield = integrity of un-programmed gate oxide
1.5T / 1T Cell Current Comparison
Cell Current
µ
A
1.5T / 1T Cell Current Histogram Comparison 130nm Low Leakage Process 1 10 100 1000 10000
0.1 1 10 100
Micro Amps N u m b e r o f B it s 1.5T 1T
1.5T- High Vt Tail (Halo Region)
1.5T- High Current Tail (LDD Region)
1T- No Tail (Channel Region) # o f B it s
Sidense 1T OTP (0.5T effective) 2 terminals High Density Mask ROM (1T) Generic 2T OTP 3 terminals Legend:
Bit Line Contact Poly
Core Oxide Poly Gate IO Oxide Poly Gate Diffusion Cell Boundary 1.5T OTP 2 terminals WL WL PL WL SL BL BL FLOATING NODE BL WL BL BL
Antifuse Yield and Reliability
1.5T Antifuse
Yield and
reliability concern
Tail bits problem
Can’t differentiate between slow and softly programmed bits
Need higher read voltage and longer time, which
compromise retention
Poor portability
Split-Channel 1T
Antifuse
Good yield and
reliability
No tail
No softly
programmed bits
Fast access
Improved
retention
Antifuse Cell Sense Margin
>1,000x margin
between
programmed and
un-programmed
cells
Sense window
improves with
time
Retention T est, Lot #S5, 250C (64 M acros x 1kbit)
0 10 20 30 40 50 60 70 80 90 100
0.00001 0.0001 0.001 0.01 0.1 1 10
Cell Current (relative values)
%
C
e
ll
s
UnPGM_0h UnPGM-240h UnPGM_400h
PGM_0h PGM_240h PGM_400h
%
Cell Current
Programmed Cells Un-programmed Cells
Typical Antifuse HTOL Results
No fails, 80 devices (2.7Mbit each)
1000h read @ 1.25xVcc, 125C
Example of cell current distribution
Two chips, 160 macros each, 5.4Mbit total
Read Point
Total (hrs) T0
T1 180
T2 400
T3 600
T4 1000
Cell Current Cell Current
Challenges Beyond 65nm
Gate dielectric integrity (defect density)
Minimize gate perimeter and area, 1T cell advantage
Increased leakage
Use IO devices
IO / Core voltage ratio
Need headroom to pass programming voltage
Increased process variability
1.5T cell concern
Power density on-chip
Not a concern for antifuse
New gate materials
NVM for 65nm and Beyond
Split-channel 1T-Fuse:
No extra masks or process steps
Programmed state is permanent
Smallest embedded OTP cell
Improved yield and reliability
Tight cell current distribution
No breakdown to LDD, Pocket or Halo implantation
Portable and scalable with CMOS Logic
