Motor Control for Industrial Applications Altera

77 

Full text

(1)

Motor Control for Industrial

Applications

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© 2012 Altera Corporation

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.

Introduction

Matt Engeriser – Arrow FAE

(763) 370-9327

mengeriser@arrow.com

Michael Parker – Altera DSP Product Planning

(408) 544-8691

mparker@altera.com

Eric Cigan – MathWorks Product Marketing

(508) 647-7015

eric.cigan@mathworks.com

(3)

© 2012 Altera Corporation

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Agenda

Motor and Controller Basics

[45 minutes]

Motor types and operation

PID controllers

Park, Clark transforms and FOC

Motor Control using FPGAs

[15 minutes]

Introduction to Mathworks HDL Coder [30 minutes]

Break

[15 minutes]

Motor Control using HDL Coder

[30 minutes]

Introduction to DSP Builder Advanced Blockset [15minutes]

DSPBuilder Motor Control Demo

[30 minutes]

Park-Clarke and PI control

Implemented in both fixed point and floating point

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© 2012 Altera Corporation

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Magnetic Flux

S

N

= B

is flux density in Teslas

Φ

A

Φ

is flux, in Webers

1M 1M

A

is area in meters

2

Magnetic Fields exist as Lines of Force

Discovered in mid-1800s (Michael Farady)

Nikola Tesla described Flux Density

(inventor of the ACIM)

(6)

© 2012 Altera Corporation

Right-hand Rule

curr

ent

•Current running through a wire creates a magnetic field

•Interacts with other magnetic fields

•Force is proportional to current flowing through wire

•More Current = More Force

(7)

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Back-EMF

Back EMF Voltage

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© 2012 Altera Corporation

Torque Components

180º To rque (Nm) Composite Torque Reaction Torque Reluctance Torque 90º

Torque Curves for Induction Motor

-150 0 300

150

Rotor/Stator Magnetic Field Alignment (degrees) Fig. A 0 degree alignment Fig. B 90 degree alignment

N

S

N

S

N

S

N

S

•Reaction Torque created by reaction between magnets on the rotor and stator

•Reluctance Torque created by magnetic field reducing it‟s reluctance (or

resistance), “Switched Reluctance Motor”

•Both are a function of the alignment between stator and rotor

•Minimum Torque (0) at 180 degrees (see figure above)

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(10)

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Pulse Width Modulation (PWM)

Blue Waveform – Motor Voltage

Red Waveform – Filtered motor voltage

Controlling Voltage to the Motor is also known as Commutation

PWM allows sine wave current profiles

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Types of Motor Feedback

•Control Loops Require Feedback Information for the Motor

•Can Also Detect Fault Conditions

•Current Sensors

•Shunt Resistor

•Current-sensing Transformer

•Hall Effect Current Sensor

•Speed/Position Sensors

•Quadrature Encoder

•Hall Effect Tachometer

•Back EMF/Sensorless

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© 2012 Altera Corporation

Basic Control Loop

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PID Control Loop

Adjustment of gain

on each of the 3 legs

is critical for stable

performance

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© 2012 Altera Corporation

PID Controller

Output

P

D

Σ

Error signal

I

d

dt

Proportional – Correction based on the amount of error (primary feedback)

Integral – Correction based on accumulation of error (eliminate persistent error)

Derivative – Correction based on rate of change of error (faster transient response)

“underdamped”

“overdamped”

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Legacy DC Brush Motors

•Disadvantages

•Brushes Cause Sparking (noise)

•Brushes Wear Out

•Torque Ripple (reduces efficiency)

•Advantages

•Cheap and simple!

•Very Easy to Control

Mechanical Commutation (no electronic switching)

•Stator is a permanent magnet

•Rotor is an electromagnet; alternating direction of current

causes rotation of motor

Rotor

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DC Brush Motors (mechanical switching or

commutating)

(17)

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B

B

C

C

N

S

A

A

Curre

nt

A

B

C

N

S

Brushless DC Motors

Commutate Motor by switching

on one set of coils at a time (not

efficient)

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© 2012 Altera Corporation

T

orque

Curre

nt

A

B

C

A

B

C

B B C C

N

S

A A A A C C B B

Commutating a BLDC Motor

•Trapezoidal Commutation

•Need to know anglular position of rotor

•90 degrees offset for max torque

•Need Feedback

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Brushless Permanent Magnet Motors

PMSM or PMAC Motor

IPM Motor

Trapezoidal Waveforms

•Becomes an AC Motors (driven by AC waveform,

sinusoidal commutation)

•Permanent Magnet Synchronous Motor (PMSM)

•Also called PMAC

•Variation of a BLDC

•Rather than “on-off” current

switching, use PWM to create

sinusoidal current waveforms

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© 2012 Altera Corporation

Interior Permanent Magnet Motors

•Rare-Earth materiels used for rotor magnets

•Generates both Reactance and Reluctance Torque

•Larger Torque-per-Amp in a Smaller Package

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AC Induction Motors (slip → torque)

• Very Common for Industrial Applications

• No Permanent Magnets

• Very Efficient for High Power Applications (>500HP)

• Stator Magnetic Field Rotates Faster than Rotor Magnetic Field

•Asynchronous Motor

•Difference in Speed is called Slip

• More load = more slip. Slip factor affects

• Torque

• Efficiency on heavy loads

• Power Factor

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© 2012 Altera Corporation 0 . 0 s 0 . 3 s 0 . 6 s 0 . 9 s 1 . 2 s 1 . 5 s 1 . 8 s 2 . 1 s 2 . 4 s 2 . 7 s 3 . 0 s 3 . 3 s 3 . 6 s -2 0 0 V -1 5 0 V -1 0 0 V -5 0 V 0 V 5 0 V 1 0 0 V 1 5 0 V 2 0 0 V V (t r e a c t i o n ) T orque

Rotor flux angle – stator flux angle 0 º

-90º 90º

-180º 180º

Field Oriented Control

•Speed and Position Controlled by PI (or PID)

•Torque Controlled by FOC

•Under Load, Rotor Angle Lags Flux Angle

•90 Degree Lag = Maximum Torque @ Current

•More Current = More Torque

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© 2012 Altera Corporation

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Clark Transform

 

 

 

 

 

 

t

i

 

t

i

 

t

i

t

i

t

i

t

i

t

i

t

i

c

b

a

b

b

3

1

3

1

3

1

3

1

3

2

 

t

i

 

t

i

a

2

3

 

t

i

 

t

i

 

t

i

b

c

2

3

2

3

b

i

c

(t)

i

a

(t)

i

b

(t)

i

β

(t)

i

α

(t)

A B C

i

b

i

c

(implied)

i

a

A B C

b

forward

reverse

•Converts a three-phase system to a two-phase system

•Results in a vector with orthogonal α and β values

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© 2012 Altera Corporation

Park Transform

d

d

q

d

d

d

i

i

i

i

i

i

b

b

cos

sin

sin

cos

i

i

b

i

d

i

q

i

b

i

A

B

s

i

d

i

q

i

d

ref ref

d

q

d

d

d

q

d

d

i

i

i

i

i

i

b

cos

sin

sin

cos

forward

reverse

Converts sine waves

to DC waveforms

Process for 3 phase motor

•Sample three motor currents

•Perform Forward Clark to get a and b values

•Perform Forward Park to reflect them on d

and q axis

•Current regulation of i

d

and i

q

yields two

correction voltages

•Perform Reverse Park and Clark to get three

voltages which are applied to motor windings

(25)

© 2012 Altera Corporation

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Park Transform Animation

Forward Park Transformation

Notice that the X

and X

b

values change sinusoidally

over time. However, the X

d

and X

q

values are DC!

(26)

© 2012 Altera Corporation + - Commanded Rotor Speed

P

I

+ +

Actual Rotor Speed

V

b

V

c

V

a

Control Diagram of a Variable Speed Control System Utilizing Field Oriented Control.

Commanded

i

d

+ -

P

I

+ + + -

P

I

+ + Commanded

i

q

Reverse

Clark-Park

Transform

Forward

Clark-Park

Transform

i

d

i

q

Phase C Current Calculation

i

a

i

b

i

c

Commanded

i

d

Commanded

i

q

Slip

Calculator

Slip Frequency + -

θ

d

θ

d

θ

d

V

d

V

q

(flux)

(torque)

TI Dave’s Control Center

ACIM

ACIM FOC Control

Note: Set i

d

=

0 for PMSM

(27)

Benefits of FPGAs in Motor Control

applications

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© 2012 Altera Corporation

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What Drives The Drives Market?

WW Electricity consumption will rise by

76% from 2007-2030

Increased need for automation equipment

64% of electricity consumed in industry

Motors

90% of the Motor lifetime cost is in

energy bills

A Drive can save up to 40% in energy

consumption of a Motor

Energy Savings = Factory Profits

(29)

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Drive Operation:

Read → Calculate → Send

Fast Control Loops Improves Motor

Efficiency

Read „energy

needed“ from

motor

t

Implementation

t

Motor energy

consumption

µC or DSP

~65 µs

Medium

FPGA

5 µs

Very low

Apply „new

power value“

Algorithm

Control Loop

(30)

© 2012 Altera Corporation

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Challenges for Drive Manufacturers

Performance

Improvements

Tighter control loops

Support for Industrial

Ethernet protocols

HW/SW acceleration

Differentiation While

Lowering Costs

Integrate functions with

less components

Leverage model-based

design flow

Multiple motor types;

multi-axes control

Implementing

Functional Safety

Understanding &

simplifying Functional

Safety qualification

Cost overhead and time to

market impact

(31)

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Integrated Drive Control With The

Drive-On-A-Chip Framework

Drive On A Chip Features

Function

FPGA Differentiator

Embedded high performance processor

Task oriented & Real-time operation

asynchronously

Performance beyond

MCU/DSP

Motor Control Algorithm

<5 µs latency & Floating Point support

Lower power consumption

Connectivity

Multiple real-time Industrial Ethernet

protocols

Supports changing protocol

standards

Interface logic

Encoder, ADC, PWM control

Flexibility and fine-tuning

Functional Safety IP and tools

Safety-qualified diagnostic IP

Saves certification time

NIOS-II or

ARM

(32)

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Implementing Motor Control

Field Oriented Control (FOC) is common in controlling PMSM and

ACIM – used in a majority of drives

Math intensive algorithm with short latency requirements

Option of floating point implementation

Interface IP

DSP Builder

(33)

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Drive-On-A-Chip Framework Eases Integration

Save Time & Development

Costs

Leverage industry tools and

methodologies

Available reference designs and

hardware

Reduced HDL coding

Design Flexibility

Easily partition HW/SW domains

Modular, prebuilt IP

Single FPGA-based platform

Differentiate

Add in your „secret sauce‟

Keep up with changing standards

Scalable methodology for multiple

product variants

Management & Communication Fieldbus IEthernet MAC SW Stack Mgmt Application I/O • Digital • Analog Motor Control D ri ve -On -A -C h ip HW SW SW PWM

Current Control Loop Velocity Control Loop

Encoder ADC IF Motion planning HW FPGA or SoC FPGA Qsys System Integration Quartus II Simulink® / Matlab® Integrate in Hardware Compile Design System Placement Nios II or ARM Software Tools (IDE) Model System Optimize Algorithm in Hardware Algorithm Using DSP Builder Software Integrate with Application Software Algorithm in ‘C’ Algorithm in Software

Drive on a Chip Design Flow

MATLAB®

(34)

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Altera’s TÜV-Qualified Functional Safety

Data Package

Altera Functional Safety Value

Altera products are sufficiently free of

systematic errors

The Altera Functional Safety Data Package

saves 18-24 months in certifying

a safe application

(35)

Introduction to DSP Builder Advanced

Blockset

(36)

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(37)

© 2012 Altera Corporation

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DSP Builder Advanced Blockset

Constraint-driven design

User sets desired clock frequency, can also constrain latency

Models silicon speeds when translating to HDL

Different devices families and speed grades result in different HDL

Automated resource sharing

Tool analyzes clock rate in relation to sample rate, number of channels, interpolation

and decimation factor, and develops efficient HDL

Automated pipelining

Enables timing closure at high clock rates of 150-250+ MHz in Cyclone devices

Supports high performance floating-point design

Only FPGA tool synthesizing single and double precision optimized HDL

Increased Productivity by Fast Timing Closure, Ease

Handoff between Systems, and FPGA Design Teams

(38)

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Higher Level Synthesis

1. Covert the MDL schematic into an intermediate

DFG representation

2. Apply transforms and analysis:

Break apart carry chains

DSP Block & Memory Timing

Share multipliers

Pipeline for:

required FMax performance

Balanced/matched delays

….

3. Generate RTL

2

1

library IEEE; use IEEE.STD_LOGIC_1164.all; entity DSPA is port (

SEL: in STD_LOGIC_VECTOR(15 downto 0); C, D, B: in STD_LOGIC_VECTOR(15 downto 0); A : out STD_LOGIC);

end;

architecture BEHAVIOUR of DSPA is begin

A := B * C + D; ……

end;

(39)

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Parameterizable Fmax Performance through

pipelining

Simple 50-bit 4-input adder tree

No pipeline => 118 LUT4s, 121 MHz

1 stage pipeline => 175 LUT4s, 286MHz

5 stage pipeline => 350 LUT4s, 581 MHz

Simply enter desired System Clock Frequency,

No need to change model

+

+

=

Timing driven synthesis produces small or fast RTL from same model

(40)

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(41)

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Design Behaviorally

No need for knowledge of silicon features

(42)

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Zero Latency Blocks

Blocks are behavioural in nature

What to do, not When to do it

Focus on signal flow representation

Much easier debug and modify without pipeline

(43)

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Math.h

- SIN

- COS

- LDEXP

- TAN

- FLOOR

- ASIN

- CEIL

- ACOS

- SQRT

- ATAN

- 1/SQRT

- EXP

- DIVIDE

- LOG

- LOG10

Implemented in Floating-Point

(44)

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Simplifies Realization of Complex Equations

Complicated equation example:

(45)

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Simplifies Realization of Complex Equations

Drop down blocks for operators…

d = (

ln

(

S/L

)

+

v*v

*t

/2

+

rt

)/

sqrt(v*v*t)

Floating

Point !

(46)

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Fixed and Floating Point in Same Model

(single reduced precision coming in 12.1)

(47)

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DSP Builder Primitive Folding

Folding

Function Units are underutilized

when the sample rate is less

than the clock rate

Time-division multiplexing

technique

Automatic time-sharing of

hardware

Allows the user to create

simple, parameterizable

primitive designs without

wasting resources

DSP Builder allows for multiple

channels being processed per

clock cycle

Additional

muxes

Additional

registers

×

×

+

A

B

C

D

×

+

z

-1

z

-1

A

C

z

-1

B

D

“Unfolded Hardware”

“Folded Hardware”

(48)

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Obtain Accurate Device Resources

No need for Quartus Compile to see FPGA

resources

(49)

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Usability

Design Checker

Verification

Progress Bar

Model Wizard

Resource Usage

Memory Map

Debug

Pause

Useful for single-stepping through Simulink simulations

VCD sink

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(51)

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Design Flow

Model based design

Toolflow

MATLAB and Simulink

Simulate/Model, Add Processor/Avalon Interface, Generate VHDL

Qsys

Integrate (DSP Builder, Processor, Interfaces, Networking)

Quartus II

Compile FPGA

Software Integration

Nios II Software Build Tools (Eclipse)

Example „C‟ code

(52)

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DSP Builder – Model motor control loop

(53)

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Looking into control algorithm

- H/W & S/W partitioning

(54)

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(55)

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Folding Factor Advantage (Floating Point)

Specification

No Folding

Folding Factor 50x

Addsub Blocks

18

1

Multiplier Blocks

13

1

Maximum Throughput

100 Msps

2 Msps

0

5

10

15

20

25

No Folding 50x Folding

21kLE

10kLE

LE Usage

0

10

20

30

40

50

60

No Folding 50x Folding

56

5

Multiplier Usage

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

No Folding 50x Folding

1.0us

2.0us

Latency

(56)

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Floating & Fixed Point Comparison

Specification

Fixed 16-Bit

Fixed 32-Bit

Floating Point

LE Usage

2.4K

4.9K

9.7K

18-bit Multiplier

Usage

1

6

5

Latency

0.92 us

0.97 us

2.03us

0

1

2

3

4

5

6

7

8

9

10

Fixed

16-Bit

Fixed

32-Bit

Floating

Point

2.5k

5k

10k

LE Usage

0

1

2

3

4

5

6

Fixed

16-Bit

Fixed

32-Bit

Floating

Point

1

6

5

Multiplier Usage

0

0.5

1

1.5

2

2.5

Fixed

16-Bit

Fixed

32-Bit

Floating

Point

0.9us

1.0us

2.0us

Latency

(57)

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(58)

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(59)

© 2012 Altera Corporation

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Software Integration

Example „C‟ wrapper

Call to „C‟ wrapper

or software

implementation

(60)

© 2012 Altera Corporation

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.

Drive On A Chip Framework Availability

Stage1: Internal

Validation

Stage2: CIV Dev

System

Stage 3: CV

Drive on chip

Stage 4: CV SOC

Drive on Chip

Completed

Schedule

Q4 2011

Q2 2012

Q4 2012

Q2 2013

Base Platform

EBV Mercury Code

CIV

Terasic DE2-115

Altera CV

Development Kit

Board

Altera CV SOC

Development Kit

Board

Motor Control

Daughter Card

EBV Falconeye

System

Altera Motor Power

Board

Altera Motor Power

Board

Altera Motor Power

Board

Motor Support

PMSM

PMSM

PMSM + BLDC

PMSM, BLDC, ACIM

Connectivity

EtherCAT

Absolute Encoder

Eth/IP, EtherCAT

Eth IP, EtherCAT,

Profinet

Eth IP, EtherCAT,

Profinet, EPL,

(61)

Cyclone V DSP Variable Precision

DSP Architecture

(62)

© 2012 Altera Corporation

Cyclone V Improvements

Now includes MLAB

Small memory storage no longer requires block

memory

640 bit MLAB (10 bits by 64 deep, or 20 bits by 32

deep)

M10K DSP Block

Variable Precision DSP

Low cost FPGAs now incorporate full featured DSP

architecture

(63)

© 2012 Altera Corporation

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.

18x19 bit Mode

64 bits

X

+

_

X

+

-

Fee

db

ac

k

Re

gi

ste

r

Ou

tpu

t

Re

gi

ste

r

+/-

18x19

18x19

18 - bit 18 - bit

+/-

Bias

Re

gi

s

te

r

In

pu

t

Re

gi

ste

r

18 bits

18 bits

18 bits

18 bits

18 bits

18 bits

Second accumulator feedback

register for complex filters

(64)

© 2012 Altera Corporation

High Precision/Floating Point Mode

64 bits

27x27

X

+/-

In

pu

t

Re

gi

ste

r

25 - bit

+

-

Fee

db

ac

k

Re

gi

ste

r

Ou

tpu

t

Re

gi

ste

r

Bias

Re

gi

s

te

r

25 bits

25 bits

27 bits

Second accumulator feedback

register for complex filters

(65)

© 2012 Altera Corporation

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.

Simple Multiply Modes

X

9

9

18

X

9

9

18

X

9

9

18

X

27

27

54

19

X

X

18

19

18

37

37

Cyclone V Variable Precision DSP Block

74

(66)

© 2012 Altera Corporation

Pre-Adder and Internal Coefficient Banks

X

+

_

X

19

18

19

38

C0

C1

18

+/-

X

18

18

+/-

18

18

18x19 multiplier size allows use of

18 bit data while using preadder

Cyclone V Variable Precision DSP Block

74

108

X

+

_

X

19

18

19

38

18

+/-

X

18

18

+/-

18

18

+/-

25 25

26x22

X

22 48 27

27x27

X

27 54 C0

+/-

25 25

26x27

X

27 C0 53

(67)

© 2012 Altera Corporation

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.

Multiply Accumulate and Add Modes

Cyclone V Variable Precision DSP Block

X

+

_

18

18

36

37

A* B +/- C

64-bit

Acc

64

X

+

_

X

18

18

18

18

37

64-bit

Acc

64

X

27 27 54

(68)

© 2012 Altera Corporation

Two Block Complex Mode

Cyclone V Variable Precision DSP Block

Cyclone V Variable Precision DSP Block

X

37

18

18

37

REAL

REAL

IMAG

IMAG

18

18

REAL

IMAG

Complex

Mult

(69)

© 2012 Altera Corporation

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.

Internal Co-efficient Register Banks

Dual, independent 18-bit or single 27-bit wide banks

Both are eight registers deep

Dynamic, independent register addressing

Eases timing closure and eliminates external registers

Enough coefficients for most parallel systolic multi-channel FIR filters

0

1

2

3

4

5

6

7

18-bits

0

1

2

3

4

5

6

7

27-bits

OR

(70)

© 2012 Altera Corporation

Variable Precision DSP Block

Biased Rounding of Accumulator Results

• Dynamically enable

RND on 64 bit Accum

result

• Add ½ of LSB to

Accum, then truncate

• RND reg set to ½

desired LSB at

compile time

0

0

0

0

0

1

0

0

N-1

th

bit

63

62

N-2

61

1

N-1

N

0

RND Reg

Accum Reg

MSB

LSB

64-N Result

+

Discard

lower order

bits

=

DSP Block

(71)

© 2012 Altera Corporation

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.

18 bit Systolic Filter Mode

Cyclone V Variable Precision DSP Block

44 bits

X

44 bits

X

+

Systolic Register

+

Output Register

44 bits

18 18 18 18

(72)

© 2012 Altera Corporation

18 bit Systolic Filter with Pre-Adder, Coeff

Cyclone V Variable Precision DSP Block

44 bits

X

44 bits

X

+

Systolic Register

+

Output Register

44 bits

+/-

+/-

18 18 18 18

18

18

C0

C1

(73)

© 2012 Altera Corporation

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.

27 bit Systolic Filter Mode

Cyclone V Variable Precision DSP Block

64 bits

64 bits

X

+

Output Register

64 bits

27 27

(74)

© 2012 Altera Corporation

27 bit Systolic Filter with Pre-Adder, Coeff

Cyclone V Variable Precision DSP Block

64 bits

64 bits

X

+

Output Register

64 bits

+/-

25 25

27

C1

(75)

© 2012 Altera Corporation

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.

Cyclone V Direct Parallel Filter Block Diagram

MLAB

MLAB

Coeff

regs

MLAB

MLAB

MLAB

MLAB

External

Adder

Tree

18x19

18x19

18x19

DSP Block

DSP Block

Coeff

regs

Coeff

regs

* Use MLAB for cases where number of coefficient per multiplier > 8

(76)

© 2012 Altera Corporation

Cyclone V Polyphase Serial Filter

M10K

M10K

M10K

M10K

N/2

: 1

multistage

adder,

using

complex

inputs and

outputs

N :1

compIex

input

data

demux

18x19

DSP Block

18x19

18x19

18 bit Precision

(77)

Figure

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References

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