6595814 Wang Modeling With SystemC

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An investment in continuing success

!

Modeling with SystemC

TM

Workshop

Version 1.4

Author: Martin Wang of SLD

Workshop Prerequisites

Familiarity with UNIX workstations running

X-windows OR Windows NT

Familiarity with vi, emacs, or other UNIX/NT

text editors

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System Architects

HW Engineers responsible for board, ASIC and

FPGA design

Test/Verification Engineers

Programmers, software developers

Workshop Target Audience

System Architect RTL Designer Software Developer Lead Architect

SystemC

TM 4

Workshop Goal

Acquire the basic skills to write,

simulate and debug general

Hardware Models using

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By the end of this workshop, you should be able to:

Workshop Measurable Objectives

Demonstrate an applied, working knowledge of

SystemC

TM

_{C++ class libraries.}

Write general hardware models with SystemC

TM

_.

Simulate and debug hardware models using

SystemC

TM

_.

Write test-benches and verify SystemC

TM

_models.

This is not just a language class, this is an design class!

Agenda: Day One

DAY

1

11

1

Why C-based Design Flow

1

Topic Lab

Unit

SystemCTM _{- Introduction}

2

C++ for the C Programmer

3

Datatypes for Diff Abstraction Level

4

Communication with Signals

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Agenda: Day One

DAY

1

11

1

Ports and Signals

6

Topic Lab

Unit

Asynchronous Function Process

7

Asynchronous Thread Process

8

Agenda: Day Two

DAY

2

22

2

Special Case: Synchronous Process

9

Topic Lab

Unit

Process Execution Order

10

Top_Level and Testbench

11

Channels for Abstract Protocol

12

Hierarchy for Modular Design

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Agenda: Day Three

DAY

3

33

3

Global and Local Watching

14

Topic Lab

Unit

Modeling BUS with Resolved Vector

15 Refinement 16 Functional I/F 17 Hardware/Software Co-verification 18

Agenda: Day Three

DAY

3

33

3

System-on-a-Chip 19 Topic Lab Unit Workshop Summary 20

Appendix and Labs Solutions

21

Quick Reference Guide

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Agenda: Structured Labs & Exercises

DAY

Getting Started

1

Topic Lab

Lab

Simple Arithmetic Pipeline Design

2

Simple Memory Controller

3

4x4 Multicast Helix Packet Switching

4

Multiple-Cycle RAM

5

Simple RISC CPU

6 12

Agenda: Labs

DAY

Topic Lab Lab Image Smoother 7

Simple Arithmetic Pipeline Design II

8

Master-Slave Bus System

9

Labs & exercises will challenge your understanding of the concepts taught

Additional experimentation labs are provided for those who might finish the required labs early

Simple FIR Filter IP

10

RSA Public-Key Crypto-system

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Icons Used in this Workshop

What it Means Icon

Lab Exercise

Question

Hint, Tip, or Suggestion

What it Means Icon

Caution

Note

Remember

Lab Solutions at the end of the book

Implementation Specific Simulation Specific

Abbreviations and Acronyms

Acronym Meaning

FSM Finite State Machine

HDL Hardware Description Language

RTL Register Transfer Level

Synopsys On-Line GTECH Generic Technology

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Agenda: Day One

DAY

1

11

1

Topic Lab

Unit

2

3

4

5

16

Today’s Market

Years to 1 Million Sales

1 Million Units Sales Volume 5 10 15 PCS PC Color TV Cable TV Black & White TV 3G Cellul ar DVD Cellula r VCR

Development Times are getting shorter

1st Silicon tape-out need to be functional !

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Designers Challenges

Design Complexity is becoming greater

Design Complexity is still increasing

Design Complexity Design Productivity 1975 1980 1985 1990 1995 2000 Gates High level SPICE Pattern Generation IC CAD ASICs Place & Route Logic Simulation Logic Synthesis Behavioral Synthesis Cycle-Based Simulation Design Reuse Deep Submicron System on a Chip Transistors Polygons

The Design Process Today

C/C++ Environment System Level Design

Hardware and Software Algorithm Development Processor Selection Done mainly in C/C++ EDA Environment IC Development Hardware Implementation Decisions Done mainly in Verilog/VHDL C/C++ Environment Software Code development RTOS details Done mainly in C/C++ Refinement Refinement Manual Translation

$ $

Emulation / Prototyping

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IC Development Process

The current design flow

Same flow for RTL, schematic, polygons, etc

Design done then captured in an EDA environment Very little, if any, “what-if” exploration

Designers can end up focussing more on “data management” than “design” L ib ra ry -b a se d S y st e m D esig n M et h o d o log y 20

HDL Based Flow

Problems:Written specifications are incomplete and inconsistent Translation to HDL is time consuming and error prone

C/C++

1. Conceptualize 2. Simulate in C++ 3. Write specification

document

4. Hand over specification document HDL

5. Understand

6. (Re)Implement in HDL 7. (Re)Verify

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21 Ver 1.4 C/C++

C++ Based Flow

1. Conceptualize 2. Simulate in C++ 3. Write specification document 4. Hand over • Executable specification • Testbench • Written specification C/C++ 5. Understand 6. Refine in C++

7. Verify reusing testbenches 8. Synthesize from C++

Turning Algorithms into the Right Architectures for ASICs

quicker and better

Why C/C++ Based Design?

SoC

Design

System Architect C/C++ C/C++ HDL Marketing & Sales

Specification between architect and implementer is executable High simulation speed at the higher level of abstraction Refinement, no translation into HDL (no „semantic gap“)

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Existing Approaches are limited ...

Languages such as C/C++ and Java are not created to

model HW

Lack of uniform modeling style

Translation tools (C/C++ to HDL)

No clear design methodology

Sub-optimal QoR

Why another translation tool?

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Can C++ be used as is?

C++ does not support

Hardware style communication

Signals, protocols, etc.

Notion of time

Time sequenced operations.

Concurrency

Hardware and systems are inherently concurrent, i.e. they operate in parallel.

Reactivity

Hardware is inherently reactive, it responds to stimuli and is in constant interaction with its environment, which requires handling of exceptions.

Hardware data types

Bit type, bit-vector type, multi-valued logic type, signed and unsigned integer types and fixed-point types.

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Summary

Why C-based Design Flow

covered HDL based flow

covered C++ Based flow

covered benefits of a C++ based flow

covered “Can C++ be used as is?”

Agenda: Day One

DAY

1

11

1

Topic Lab

Unit

2

3

4

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C++ powered by SystemC

TM

What is SystemC ?

SystemC is a C++ Class library Include any C++ programs, libraries, encapsulation

... a methodology for modeling SoC designs consisting DSPs, ASICs, IP-Cores, Interfaces, ...

SystemC also enables

Modeling at high level of abstraction e.g. communication protocols Refinement to hardware

Software modeling - interrupts, exception handling System wide verification Hardware/Software co-verification

IP exchange

SystemC provides all the advantages of Verilog and VHDL Concurrent processes e.g. methods, threads, clocked threads

Concept of a clock Wide variety of bit-true data types

SystemC IS NOT Another C++ dialect -> it is C++

Just for hardware modeling only -> you can model hardware AND software in C++ with SystemC

Purely Algorithm /Software in C++

High Level Abstract Hardware Model in SystemC C++ Programs C++ Software Model Behavioral Level Hardware Model in SystemC Register Transfer Level Hardware Model in SystemC HW/SW partitioning C++ Software Model C++ Software Model 28

Short History of SystemC

TM

1997 1998 Scenery V0.9 Launches 9/27/1999 1997 DAC Paper HDL constructs fixed pt datatypes V1.0 Release 3/2000 1999 2000 •Source Code • User Guide • Reference Manual • Discussion Forum

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Getting Started with SystemC

Compiler

gcc

native compiler Visual C++, SUN cc

Debugger

gdb, ddd

lint, profiler, memory access checking

quantify, purify

www.gnu.org

First example

Compiler version

which gcc, gcc -v

which architecture is used

autoconf helps installation

./configure; gmake

Makefiles control what is included

compile directives

libraries

include files

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Books/Training

Nothing replaces hands-on experience!

Books

Kernigham/Ritchie; The C programming language

Stroustrup; The C++ Programming language

Lippman; C++ primer

man pages

web sources

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Compile SystemCand Run the executable!

class library and

simulation kernel source files for system

and testbenches your standard C/C++ development environment compiler linker debugger libraries header files „execu table specifi cation “

...

....

executable = simulator a.out „make“ ASIC IP-Core Interface DSP

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A SystemC

TM

_System

System consists of a set of concurrent processes

Process describes functionality

Processes communicate with each other through

signals and channels

Processes can be combined into modules to create

hierarchy

Process 1 Process 3 Process 2 Process 5 Process 4 Module 1 signals System channel

Simple Example - 1

main.cpp stimgen.cpp stimgen.h adder.cpp adder.h monitor.cpp monitor.h

+

in1 in2 out Adder in1 in2

out re Response_Monitor Stimulus Generator a1 a2 main.cc clk

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Simple Example - 2

// top level routine/level #include “systemc.h”

#include “adder.h” #include “stimgen.h” #include “monitor.h”

int sc_main(int ac, char *av[ ]){

// Create signals to tie modules sc_signal<int> s1; sc_signal<int> s2; sc_signal<int> s3; // Create clock sc_clock clock(“CLOCK”, 10, 0.5); // Instantiate modules adder Add(“MyAdd”); Add << clock << s1 << s2 << s3; stimgen ST(“STIM”); ST(clock, s1, s2); monitor M(“MON”); M.clockint(clock); M.s3int(s3); // Simulate sc_start(200);

return(0); // since sc_main have // type of int, return 0 // means no error. } main.cpp stimgen.cpp stimgen.h adder.cpp adder.h monitor.cpp monitor.h Adder in1 in2

out re Response_Monitor Stimulus Generator a1 a2 main.cc clk 36

Simple Example - 3

// header file adder.h struct adder : public sc_module {

// Input ports sc_in_clk CLK; sc_in<int> in1; sc_in<int> in2; // Output ports sc_out<int> out; // Constructor

adder (const char * NAME) : sc_module(NAME) {

sc_sync_tprocess(handle1,”ADDER”, adder, entry, CLK.pos()) end_module();

}

// Functionality of the process void entry(); }; main.cpp stimgen.cpp stimgen.h adder.cpp adder.h monitor.cpp monitor.h Adder in1 in2

out re Response_Monitor Stimulus Generator a1 a2 main.cc clk

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Simple Example - 4

// Implementation file adder.cc #include “systemc.h” #include “adder.h” void adder :: entry( ) { while (true) {

out = in1 + in2; wait( );

out = in1 + in2 + 2; wait( ); } } main.cpp stimgen.cpp stimgen.h adder.cpp adder.h monitor.cpp monitor.h Adder in1 in2 out Response Monitor re Stimulus Generator a1 a2 main.cc clk

Another Simple Multiply and Add Example

// header file mac.h #include “systemc.h”

struct mac : public sc_module { // Input ports sc_in_clk CLK; sc_in<int> in1; sc_in<int> in2; // Output ports sc_out<int> out; sc_out<bool>rdy; // Constructor mac (const char * NAME)

:sc_module (NAME) {

sc_sync_tprocess(handle1,”MAC”, mac, entry, CLK.pos())

{ /* watching for reset */ } // Functionality of the process void entry();

};

// Implementation file mac.cc #include “mac.h”

void mac :: entry( ){

int int_var; // internal variables while (true) {

rdy = false; int_var = in1 * in2; wait( );

// top level routine main.cc #include “mac.h”

#include “stimgen.h” #include “monitor.h”

int sc_main(int ac, char *av[ ]){ // Create signals sc_signal<int> s1; sc_signal<int> s2; sc_signal<int> s3; sc_signal<bool> s4; // Create clock sc_clock clock(“clock”, 10, 0.5); // Instantiate Processes mac MAC(“MAC_BLOCK”); MAC << clock << s1 << s2 << s3 << s4;

// other processes e.g. stimulus generator, monitor

// Simulate MAC in1 in2 out Response Monitor re Stimulus Generator a1 a2 Rdy OK s1 s2 _s4 s3 CLK

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So, How to create a SystemC Model

Determine the abstraction level

Determine signals & channels between processes

Determine protocol for signals between processes

Create the process functionality

SystemC - System Level

Behavioral Level Description

RTL Description Algorithm Level Description

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Summary

SystemC - Introduction

covered a short history of SystemC

TM

covered how to use SystemC

TM

covered a basic SystemC

TM

_example

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Lab 1: Getting Started - 1

Counter.h contains the process declaration Counter.cpp contains the process

functionality

Test_Counter.h contains the stimulus and

control process declaration

Test_Counter.cpp contains the stimulus and

control functionality

main.cpp contains the main entry point and

instantiates the two processes

Primary Objective:

Understanding A SystemC System

This lab introduces the process of simulating with SystemCTM_.

You will simulate a simple counter that counts up to seven, then wraps around to zero. The counter can be reset at any point.

Lab 1: Getting Started - 2

1. Compile and link the files with the following command:

gmake ultraclean; gmake

2. Run lab1.x You should see the counter counting and being reset OR. Compile each file with the following command:

gcc -c -g -I. -I../include Counter.cpp gcc -c -g -I. -I../include test_Counter.cpp gcc -c -g -I. -I../include main.cpp

Where:

-c Compile only - do not attempt to link

-g Include debugging information

-I. Look for include files in the current dir

-I../include Look for include file in the ../include dir Note: no space between the option (I)and the argument. Link the object files together to create the executable:

gcc -o lab1.x *.o -lsystemc-g -L../lib -lstdc++

Where:

-o lab1.x The resulting executable file will be called lab1.x

*.o Link together all the object files

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Lab 1: Sample Output

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Lab 1: Debugging with SystemC

TM

_{- 1}

Debugging. You determine what is wrong in your simulation. Debugging consists of:

Controlling the execution of your simulation

Examining values of key data during the course of simulation

Use a debugger tool for source-level debugging:

Unix: gdb, xgdb, dbx

NT: Visual C++ development environment

Use "print" I/O statements in your code

SystemCTM_{provides useful data}

Trace waveforms for post-simulation viewing

Tip:

To enable source-level debugging, compile with the -g option in gcc

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Lab 1: Debugging with SystemC

TM

_{- 2}

Controlling the execution of the simulation:

SystemCTM_{is different than normal, sequential programming} Single-stepping from the beginning is not productive

You don't know the actual order in which your processes will execute proc1::entry() { // Declarations, initialization while (true) { val = some_func(in_sig); out_sig.write(val); wait(); } } Set breakpoint here Tips:

Set breakpoints in processes (first executable statement inside the while loop)

For asynchronous blocks, at first executable statement

Single-step within processes

Step over calls to SystemCTM_{built-in functions}

Step OVER

Lab 1: Debugging with SystemC

TM

_{- 3}

Examining data values:

While single-stepping, use the print command in the debugger

gdb is C++ savvy

Use C++ I/O to print out data values

SystemCTM_{data types know how to display themselves using C++ I/O} If you must use C-style I/O, SystemCTM_{data types have a}_{to_string()}

method proc1::entry() { while (true) { val = some_func(in_sig); printf("proc1(%s): in_sig = %s\n", sc_time_stamp(), in_sig.to_string()); cout << "proc1 (" << sc_clock::time_stamp() <<

"): val =" << val << endl; out_sig.write(val);

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Lab 1: Overview of ddd -

Free Graphical C++ Debugger

http://www.gnu.org/software/ddd/

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Lab 1: Debugging with ddd - 1

Invoking the debugger:

ddd

File -> Open Program

Open lab1.x

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lab 1: Debugging with ddd - 2

Click here to Run!

NOTE: If you see this sc_xxx.cpp then your library is compiled correctly for debug mode.

Lab 1: Debugging with ddd - 3

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Lab 1: Debugging with ddd - 4

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Lab 1: Debugging with ddd - 5

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Lab 1: Debugging with ddd - 6

Lab 1: Debugging with ddd - 7

Set your breakpoint here!

Step your simulation Put your mouse here

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Case Study: Digital Video Camera Design Project

Challenge

Need to prove the concept -> ask for design funding FAST from management. Complete design as fast as possible. IP Reuse, minimum changes to IP.

Need to quickly explore different architectures before actual implementation.

Easy and quick validation/debug. Need a golden C++ model.

Need a system model for software development before hardware design complete.

Quick to Prototyping.

Need RAPID product development to enter explosive, competitive consumer markets

Subsequent labs will be based on the following design specification. By modeling different modules using different abstraction levels we will learn the capabilities of SystemCTM

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Case Study: DSP Systems Development Process

• Algorithm Design:

³ Stable, accurate algorithms that perform as required

• Performance Optimization:

³ Optimized fixed-point algorithms that meet performance specifications under system operating conditions

• HW or SW Implementation:

³ Optimized VLSI architecture that executes algorithms efficiently and rapidly • Integration/Verification:

³ Functional correctness of the implementation of the

SYSTEM

Hardware

Implement-ation

System Integration and Verification (System Test) Performance Optimization Algorithm Design Software Implement-ation Verification (Unit Test) y Models Models

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Case Study: Digital Video Camera System View

System Bus DSP ASIC FFT CPU Core Memory Assembly code/ Machine Code Application Software, Device Driver… in C++ While (…) { ... } cout << … Compiler C++ models SystemCTM_models Add R1, R2, R3 mul R2, R4. R5 bnz loop1 … DMA BUS Controller 0000 0110110010110101 1000 0111100001010101 0100 0011111010101011 1100 0010101011111001 0010 1101010111010101 1010 0000000011010101 0110 0111111110010111 Reg BUS FPU SIMD Decode ALU Fe tc h DSP Core from Company X Network Interface

Case Study: SystemC

TM

_View

//Example: cpu_core.cpp (Cluster Level) while (true) { …. } //Example: cpu_core.h (Cluster Level) while (true) { ….

//Example: fft.h (Unit Level) #include “debug.h” //Example: dsp_asic.cpp (Cluster Level) while (true) { System Bus DSP ASIC FFT CPU Core Network Interface BUS controller DSP Core from Company X DMA //Example: dsp_asic.h (Module Level) #include “ip_interface.h” #include “fft.h” #include “bus_controller.h” … IP vendor Provide .obj(compiled from same compiler)

& interface.h file

//Example: sc_main.cpp (System Level)

#include “systemc.h” // REQUIRED

#include “cpu_core.h” #include “dsp_asic.h” #include “testbench.h” …

int sc_main(int ac, char* av[]){ // MAIN // internal signals ... sc_clock clk(“SYSCLK”, 20.0, 0.5,0.0); testbench T(“TESTBENCH”, ... cpu_core CPU(“CPU_CORE”, ... dsp_asic CPU(“DSP_ASIC”, ... … sc_start(1000); }

//Example: fft.cpp (Unit Level) #include “fft.h” …… //Example: bus_controller.h (Unit Level) Hierarchical Design Memory

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Agenda: Day One

DAY

1

11

1

Topic Lab

Unit

2

3

4

5

60

Identifiers & Comments

Identifiers are the names assigned by the user to C++

or SystemC

TM

_{objects such as variables.}

Identifiers must begin with a letter or an underscore (a-z A-Z _ ).

Identifiers may be composed of letters, digits and the underscore (a-z A-Z 0-9 _ ).

C++ is case sensitive

No limit on length and all are significant.

Comments

Single line comments:

• Begin with "//" and end with a carriage return • May begin anywhere on the line.

Multiple line comments:

• Begin with "/*" and end with a "*/" • May begin and end anywhere on the line • Everything in between is commented out

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Strings

• Strings are enclosed in double quotes and are

specified on one line.

• SystemC

TM

_{recognizes normal C/C++ escape}

Characters (\t, \n, \\, \",%%).

”Synopsys's tools are the key to your success!"

"This format is spaced with a tab \t followed with this"

"\n This puts a newline before this string"

"Address = %h at time %d"

If and if-else

syntax:

if (expression) statement;

If the expression evaluates to true then execute the statement (or statement group)

if (expression) statement1; else statement2;

If the expression evaluates to true then execute statement1,

If false, then execute statement2 (or corresponding statement groups).

Data_D Data_C Data_B Sel_C Data_Out 0 1 0 1 0 1 if (Sel_A == 1){ Data_Out = Data_A; } else if (Sel_B == 1) { Data_Out = Data_B; } else if (Sel_C == 1) { Data_Out = Data_C; }

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63 Ver 1.4 00 01 10 11 D_Out A B C D Sel(1 downto 0)

Case statement

syntax:

switch (expression){

case_item_1: statement or statement_group break;

case_item_2: break;

case_item_3: statement or statement_group break;

case_item_n: statement or statement_group break;

default: statement or statement_group break;

}

•Does an identity comparison

•Compares expression with each case_item_(n) in turn. •If none match, the default code is executed.

•Default clause is ideal to catch unknown/unspecified values

REMEMBER TO PUT BREAK!

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When to use : case or if-then-else

Some general rules to remember:

• Use if-else where you MUST have priority encoded

logic

• Use case for non-priority encoded logic

• case items are mutually exclusive

• Always specify a default clause in case statements

• There is an impact on simulation speed

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SystemC

TM

_{Modeling Constructs}

For Loop SystemC Modeling I/O Variables Inputs Outputs Clocks Loop Exits/ Continues Operations While Loop wait statements If-else Case Modules

Quick(!) Introduction to C++ Class

structs

Are used in C to group data elements together as an integral whole.

C++ extends this notion to include functions as data members as well as data types.

Encapsulates behavior as well as characteristics

Example:

struct RandNum {

unsigned long seed; unsigned short getRand(); }

Function can be a data member

Bad idea to allow users of an object to directly use and manipulate internal data

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C++ Classes and Data Abstraction

C++ provides modifiers to control access to data:

public (default)

private

protected

In C++, a class default is private. Struct default is public

IP Example: class Time{ private: int hour; int minute; int second; public: Time();

void setTime(int, int, int); void printMilitary(); void printStandard(); }

Member access specifier

Alert: do not initialize a data member explicitly in class definition

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Information Hiding Example

Example:

Time rv;

rv.hour = 12;

rv.setTime(11, 12, 13);

rv.printStandard();

Error!! Can’t access private member

This is the right way

Member functions are accessed just like data members

Tips:Making data members of a class private and member functions of class public facilitate debugging because data manipulation is localized to either class’s member function or friends of the class.

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Data Initialization

C++: A special member function (constructor) is automatically called by the compiler.

Constructor has same name as the class or struct, with no return type

Example:

class Time{ private:

int hour, minute, second; public:

Time();

void setTime(int, int, int); void printMilitary(); void printStandard(); }

// constructor initialize each data members Time::Time() { hour = minute = second = 0;} void Time::setTime (int h, int m, int s) {

hour = .. }

void Time::printMilitary() { cout << (hour < 10 ? … }

You can have more than one constructor, so you can initialize your data in different ways

C: Explicitly call initialization routines, but not in C++.

Don’t forget class name and :: !

C++ Constructor Overview

A class member function is invoked automatically each time it is instantiated

Constructor can be overloaded for a variety of reasons like initializing objects of the class

Data members must:

initialized in a constructor of the class their values are set after the object is created

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Operator & Function Overloading

C: Multiple functions with unique names

C++: Functions with the same name, different arguments

C++: Define how operators interpret data, as if built into the language.

C++ is strongly typed

Need more flexible, generic object e.g. Instances differ only in type

// Example: overloading for complex number

class Complex { public:

Complex(double = 0.0, double = 0.0); Complex operator+(const Complex &) const; const Complex &operator=( const Complex &); void print() const;

private:

double real, imaginary; };

Complex::Complex(double r, double I) :real(R), imaginary(I){}

Complex Complex::operator+(const Complex &operand2) const{ return Complex(real+operand2.real, imaginary+operand2.imaginary); }

Constructor !

Overloading + operator

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Inheritance

Reuse existing classes by defining a new sub-class that inherits from a super (or parent) class

You change only what is unique about the new class

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References vs. Pointers

C: Arguments to functions passed by reference or by value

C++ references simplify passing data by reference

Eliminate pointer de-referencing

Use const for passing large objects to simulate call-by-value.

Benefit of reducing large data copying overhead

Called function will not corrupt caller’s data.

Benefits: Better code clarity, readability, eliminates common errors

Example:

incr( int &arg1, int *arg2 ) {

arg++; *arg2++; }

int i1, i2;

i1 = 0; i2 = 0;

incr(i1, &i2);

Passes address of i2 to incr

Tips: Call-by-reference improves performance because it eliminates the overhead of copying large amounts of data.

Scope Resolution Operator

// purely C++ software code #include <iostream.h>

#include <iomanip.h>

const double PI = 3.14159265358979;

int main() {

const float PI = static_cast<float>(::PI);

cout<<setprecision(20) <<“Local value of PI= “<<PI

<<“Global value of PI= “<<::PI<<endl; return 0;

}

C++ provide the unary scope resolution operator ::

to access global variable when a local variable of the same name in

the scope.

Use const for passing large objects

Local value = 3.14159

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I/O in C++

C++ simplifies I/O considerably Standard variables: cout, cin, cerr

Operators: << for writing, >> for reading Formatting manipulators

endl Output end-of-line (\n) setw(int) Set the width of the output

hex Output numbers in hexadecimal format setprecision(int) Sets floating-point output precision Streams file, network memory buffer Example: #include <iostream.h> #include <iomanip.h> main() { int i = 12; float r = 12.34; cout << “1234567890” << endl; cout << i << endl;

cout << hex << setw(4) << i << endl; cout << r << endl;

cout << setprecision(1) << r << endl; } Output: 1234567890 12 c 12.34 12.3

Tips: C printf work well too!.

76

Why Objects for hardware?

Object contains data and functions

Objects can get created and destroyed

Data members are visible local to the object

Splitting functionality is easy

Report internal states

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77

Ver 1.4

Why Objects for hardware?

struct cmult : sc_module {

sc_in_clk clk; sc_in<bool> new_data; sc_in<sc_int<8> > data_in; sc_out<sc_int<8> > data_out; sc_int<8> a; void entry() { sc_int<8> b, c, d; while(true) { wait_until(new_data.delayed() == true); a = data_in.read(); #if DEBUG dump(); #endif wait(); … data_out.write(a*c-a*d); } }; void dump() {

cout << “Information : cmult new data item “ << a << endl; }; SC_CTOR(cmult) { SC_METHOD(entry, clk.pos()); } }

Summary

C++ for the C Programmer

covered basic standard C++ programming

languages

introduced Classes

covered Constructor - Way to initialize things

covered Operator and Function Overloading

covered References and Pointers

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79

Ver 1.4

Agenda: Day One

DAY

1

11

1

Topic Lab

Unit

2

3

4

5

80

Data Types

C++ built in data types may be used but are not

adequate to model Hardware.

long, int, short, char, unsigned long, unsigned int, unsigned short, unsigned char, float, double, long double, and bool.

SystemCTM_{provides other types that are needed for}

System modeling.

Boolean types: sc_bit

Scalar types: sc_logic

Integer types:sc_int<length>, sc_uint<length>, sc_bigint<length>, sc_biguint<length>

Logic/Boolean vector types:sc_bv<length>(Ver 0.9: sc_bool_vector) , sc_lv<length> (Ver 0.9: sc_logic_vector),

sc_array

Scalar and integer types introduced now, vector types covered later.

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81

Ver 1.4

Table of SystemC Datatypes

sc_int<length> all all all allall all all all yes yes

sc_uint<length> all all all allall all all all yes yes

sc_bigint<length> all all all allall all all all yes yes

sc_biguint<length> all all all all all all all yes yes

sc_bv<length> ~ & ^ | all =. &=,

|=, ^=

yes

sc_lv<length> ~ & ^ | all =. &=,

|=, ^= yes sc_array all = sc_2d all = yes yes yes yes List of all operations SystemCTM_{allows on types}

Types Bitwise

Arith-metic Logical Equal-ity Rela-tional Assign-ment Auto- incre-ment or dec-rement Arith-metic if Concat -nation

sc_bit & ^ | all all all =. &=,

|=, ^=

yes yes

sc_logic ~ & ^ | all =. &=,

|=, ^=

yes Index

When to use which Data Types?

There is a tradeoff between simulation speed and code objective:

To summarize, follow these rules in order:

1) use native data types as much as possible

2) use sc_int<length>/sc_uint<length>

3) use sc_bv<length> for bitwise operations

4) use sc_logic/sc_lv<length> to model 'X' and 'Z’

5) use sc_bigint<length>/sc_biguint<length> for arbitrary

length arithmetic operations

Hint: One very interesting option for simulation speed is using profiling tools Fastest

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83

Ver 1.4

sc_int<>, sc_uint<>

sc_int<length>

,

sc_uint<length>

Used for performing arithmetic on signed and unsigned integers of

less than or equal to 64 bits (on a 32-bit machine)

Not optimal for bit vector manipulation.

A two's-complement representation is used for signed integers.

An array of bits

Can address an individual bit

Interpreted as an integer for arithmetic operations

Simulate faster than the arbitrary precision data types

NOTE: C++ language defines the int type to be 32 bits wide. SystemC provides both fixed precision and arbitrary precision types when you need integers of a different bit width than 32.

Unsigned integer

84

sc_bigint<>, sc_biguint<>

sc_bigint<length>

,

sc_biguint<length>

Used when more than 64 bits of precision are required

Not optimal for bit vector manipulation

A two's-complement representation is used for signed integers

An array of bits

Can address an individual bit

Interpreted as an integer for arithmetic operations

Hint: Use for arithmetic operations wider than 64 bits

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85

Ver 1.4

sc_int, sc_uint, sc_bigint, sc_biguint Syntax

Syntax: sc_int<length> variable_name ; sc_uint<length> variable_name ; sc_bigint<length> variable_name ; sc_biguint<length> variable_name ; length:

Specifies the number of elements in the array

Must be greater than 0

Must be compile time constant

Use []to bit select and range()to part select. Rightmost is LSB(0), Leftmost is MSB (n-1)

sc_int<5> a; // a is a 5-bit signed integer sc_uint<44> b; // b is a 44-bit unsigned integer sc_int<3> c;

sc_bigint<5> a;

a = 13; // a gets 01101, a[4] = 0, a[3] = 1, …, a[0] = 1 bool b;

b = a[4]; // b gets 0 b = a[3]; // b gets 1 sc_bigint<3> c;

c = a.range(3, 1); // c gets 110 - interpreted as -2

sc_logic

Interpreted as a single-bit variable representing multiple-valued logic

Values:

0 logical zero or false (equivalent to boolfalse) 1 logical one or true (equivalent to booltrue) Z high impedance

X unknown

Use only when necessary to model tri-state buses and their drivers.

Remember: Simulation & Synthesis interpret “X” differently; Simulation - unknown, Synthesis - don’t care

Try to limit assignments of X to internal variables, not the output nodes of your module.

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87

Ver 1.4

sc_bit

Interpreted as a single-bit variable representing two-valued logic

Values:

0 logical zero or false (equivalent to boolfalse) 1 logical one or true (equivalent to booltrue)

Hint: Use two-valued logic whenever possible.

WARNING: C++ bool is implemented as integer! Remember to initialize your bool variables to 0 or 1 if you use C++‘s bool.

Syntax:

sc_bit variable_name, variable_name, … ; Example:

sc_bit a, b; // declares variables ‘a’ and ‘b’ as type sc_bit

88

sc_logic Syntax

Syntax:

sc_logic variable_name, variable_name, … ; Example:

sc_logic a, b; // declares variables ‘a’ and ‘b’ as type sc_logic

This is a model of a Tri-state driver.

{

bool control, data; sc_logic ts_out;

if (control == false) {

ts_out = ’Z’; // Set the drive to Z }

else {

ts_out = data; // Set the drive to data }

}

INFO:Most simulators simplify 9-value logic to 4-value logic for faster simulation speed, therefore 9-value logic is not provided

data control

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89

Ver 1.4

Summary

Datatypes for Different Abstraction Level

covered sc_int<>, sc_uint<>

covered sc_bigint<>, sc_biguint<> and sc_logic,

sc_bit

mentioned simulation speed impact

Agenda: Day One

DAY

1

11

1

Topic Lab

Unit

2

3

4

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91

Ver 1.4

Introduction to Signals

Processes communicate with each other through signals or channels

Signals are analogous to wires in hardware

Signals are typed and always carry a value

Signals are resolved or non-resolved

SystemC allows signals of all built-in C++ data types or SystemC data types

Declaring or instantiating a signal of a particular type require the use of C++ template mechanism

ie. in C++ terminology, a signal is a template class

Tips: Use sc_signal<type> for processes communication!

process1sc_signal<T>process2

92

Reading Signals

When a process reads a signal it reads the

current value.

The reading of a signal does not remove the value

stored in the signal.

Multiple processes can read the same signal.

ALERT: Reading a sc_channel DOES REMOVE the value. We will cover channels later.

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93

Ver 1.4

Reading Signal Using read()

All signals support the

read()

method.

Returns the value currently carried by the signal immediately. Any number of processes can read value of a signal with

read()method. Example:

i = count.read(); //Read signal ’count’ and store // value in variable ’i’

Examples:

i = count; // Equivalent to i = count.read()

if (count < 7) {…} // Equivalent to if (count.read() < 7) {…}

Hint:read()method is recommended.

Clearly differentiates reads & writes Not required. Either or mix is OK

Writing Signal - 1

A write to a signal overwrites the value.

Value is overwritten regardless if the last value has been read or not.

Non-resolved signals may have only one writer

Resolved signals may have multiplewriters (drivers)

Computed by applying resolution function to the drivers

X 0 1 Z X X X X X 0 X 0 X X 1 1 Resolve X 0 1 Z X 0 1 Z

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95

Ver 1.4

Writing Signal - 2

All signals have a

write()

method for writing.

Value is assigned to the signal but

Signal value does not change as soon as the assignment

statement is executed.

Assignment statement schedules the signal for a value

update.

When the update occurs depends upon what type of

process (more later).

Implication: Successive writes to the same signal can overwrite the value of the signal before the update occurs. Only the last value written will be visible to other processes.

Example:

count.write(’a’); //Write char ’a’ on signal ’count’ count.write(’b’); //now ’b’ will be written to count

//in the next clock cycle.

count2 = ’c’; // Equivalent to count2.write(’c’)

96

Signals of Scalar types - sc_signal

A signal is a C++ template class -sc_signal

Used to communicate scalar values between processes. Non-resolved signal.

Signals are as wide as their corresponding data type.

Individual bits of a scalar signal cannot be read or

written. All bits must be read together.

Syntax:

sc_signal<type> signal_name ; type:

Built in C++ types

sc_logic

sc_signal<char> a; // a is a signal of type char

sc_signal<sc_uint<10> > b; // b is a signal of type sc_uint 10 bits wide sc_signal<int> c; // c is a signal of type int

sc_signal<bool> d; // d is a signal of type bool sc_signal<sc_logic> e; // e is a signal of type sc_logic

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97

Ver 1.4

Other Signal types

Other signal types are defined - covered later:

Special signal arrays

sc_signal_bv<length> (Ver 0.9: sc_signal_bool_vector)

sc_signal_lv<length> (ver 0.9: sc_signal_logic_vector)

Resolved signal of vector type

sc_signal_rv<length> (Ver 0.9: sc_signal_resolved_vector )

Refer to Appendix or Reference Manual for more information.

Summary

Communication with Signals

introduced signals - means of communicating

between processes

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99

Ver 1.4

Lab 2: Simple Arithmetic Pipeline Design - 1

Stage1.h, Stage2.h, Stage3.h contains the process declaration Stage1.cc, Stage2.cc, Stage3.cc contains the process functionality

Numgen.h and display.h contains the stimulus and control process declaration Numgen.cc and display.cc contains the stimulus and control functionality main.cpp contains the main entry point and instantiates all processes

Primary Objective:

Understanding how to write interface file

This lab introduces the process communication using SystemCTM _{signals. You will simulate a simple 3 stage}

pipelined arithmetic operation. You need to provide the correct signal type (by modifying Stage1-3.h file) for inter-pipestage /process communication.

main.cc Stage1.cc Stage1.h Stage2.cc Stage2.h Stage3.cc Stage3.h 100

Lab 2: Simple Arithmetic Pipeline Design - 2

Stage1 Stage 2 Stage3

In1 In2 Sum Diff Prod Quot Powr a b a+b a-b a*b a/b a b a b a^b

Tips : Make sure you have sc_signalfor your signals in your interface file. <double> <double> <double> <double> <double> <double> <double>

!

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101

Ver 1.4

Lab 2: Sample Output

Sample output:

Agenda: Day One

DAY

1

11

1

6

Topic Lab

Unit

7

(52)

103

Ver 1.4

Ports

Ports of a module are external interface that pass information to and from a module, and trigger actions within the modules

Signals create connections between module ports allowing modules to communicate.

A port can have three different modes of operation

Input sc_in<port type>

an input port transfers data into a module e.g. sc_in<bool> reset; Output sc_out<port type>

an output port transfers data out from a module e.g. sc_out<int> dest; InOut sc_inout<port type>

an inout port transfers data both into and out of a module depending on module operation e.g. sc_inout<sc_bit> dnt;

Ports are always bound to a signal except when a port is bound directly to another port.

Signal binding occurs during the execution of the module constructor

104

Signals

A signal sc_signal<type> connects the port of a module to the port of another module

The signal transfer data from one port to another as if the ports were connected directly

When a port is read , the value of the signal connected to the port is returned

When a port is written, the new value will be written to the signal when the process performing the write operation has finished execution or has been suspended.

Preventing some processes seeing the old value while other processes sees the new value during execution.

All processes executing during a timestamp will see the old value of the signal

These signal semantics are the same as VHDL signal operation and Verilog deferred assignment behavior.

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105

Ver 1.4

Ports and Signals

FIFO

data din

No signal required: port data of the module NWK is directly connected to a port din of module FIFO, so in this case no local signal is required.

NWK

clkin clkint

Signal required: if an input port of a module connects directly to an output port, then a local signal is needed. In this case, port clkin connects directly to port clkout, so a signal is needed to connect the two ports.

CTREE

clkout

Example of ports and signals

Example:

sc_in<sc_logic> a[32]; // ports a[0] to a[31] of type sc_logic

sc_signal<sc_logic> i[16]; // signals i[0] to i[15] of type sc_logic

sc_in_clk CLK; // CLOCK port

sc_in_bv<10> kan; // a bit vector input port 10 bits wide sc_out_bv<20> bao; // a bit vector output port 20 bits wide sc_inout_bv<33> wang; // a bit vector inout port of 33 bits wide sc_in_lv<10> creat; // a logic vector input port 10 bits wide sc_out_lv<20> this; // a logic vector output port 20 bits wide sc_inout_lv<33> train; // a logic vector inout port of 33 bits wide sc_in_rv<10> ing; // a resolved logic vector input port 10 bits wide sc_out_rv<20> mater; // a resolved logic vector output port 20 bits wide sc_inout_rv<8> labz; // a resolved logic vector inout port of 8 bits wide

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107

Ver 1.4

Clocks - A special port and signal

Time is determined by transitions of special signals called clocks

No smaller granularity of time than a clock cycle

Clocks provide a mechanism for synchronization and ordering of communication between processes A system can have more than one clock

Clocks do not have to be related (e.g. CPU core clock, bus clock…) Time of first edge used to establish phase relationship.

Positive edge _{Negative edge}

Master Clock T = 0

Time of first edge establishes the phase relationship between clocks

period Duty Cycle = D/Period

Out-of-Phase Clock

108

Clock Syntax

A clock is a C++ class - sc_clock Example:

sc_clock variable_name (name, period, duty_cycle, start_time, positive_first ) ;

name: clock name type: char * default value: none period: clock periodtype: double default value: 1

duty_cycle: clock duty cycle type: double default value: 0.5 start_time: time of first edge type: doubledefault value: 0 positive_first: first edge positive type: bool default value: true

sc_in_clk clk2; //creating Clock port

sc_clock clk2(“clk2”, 20.0, 0.5, 10, 1); //generating clock

0 10 20 30 40 50 60 First ed ge at tim e 10 First edg e positive edge clk2 period

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109

Ver 1.4

Clocks in general

A clock is a general ordering mechanism. It does not have to be associated with the real system clock.

At a high level of abstraction, a clock cycle can be thought of as a step of computation and a way of ordering communication

0 10 20 30 40 50

At the implementation level of abstraction, a clock should be thought of as the actual system clock

read Header Processing Sentout data

Hint: Good practice is to have the variable_name and the clock

name the same . Only one clock per process.

Clocks and Edges

Each clock has two edges - each edge of a clock is also a C++ class

sc_clock_edge

Clock edges are used to trigger synchronous processes

Clock edges are used only by synchronous processes

Clock edges are not explicitly defined, but are derived from a clock using the pos() and neg() methods

Example:

given: sc_clock clk(“clk”, 10, 0.5);

clk.pos(); // Gives a reference to the positive edge of clk

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111

Ver 1.4

Clocks - Other Information

If you know the variable name for the signal:

name() method returns the clock name

period() method returns the clock period

duty_cycle() method returns the clock duty cycle

Example:

given signal clk2 was defined as follows:

sc_clock clk2(“clk2”, 20.0, 0.5, 10, 1); clk2.name(); // returns “clk2” clk2.period(); // returns 20.0 clk2.duty_cycle(); // returns 0.5

112

More on Clock: Gated Clocks and DFT

Though gated clocks are an important power

management strategy, they reduce the controllability

required by a design for test (DFT) methodology.

Architects can use SystemC to do clock gating analysis

and DFT evaluation.

Controllability can be restored by introducing another pin

and assigning a fixed value to it during testing

This fixed value will override and nullify the gated clock

subsystem Count ResetClock Enable + 1 TMS Combin. circuit

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113

Ver 1.4

Power : Growing ASIC/IC Driver

Green PC Packaging Costs Packaging Cost Battery life Reliability Cooling Costs Power-Driven Area-Driven (cost) Performance-Driven Consumer Peripheral Hi-Volume Portables Cellular Pagers Medical Workstations PCs Military Telecom

More than just your cellular phone

Clock Gating Overview

Clock gating

Reduces power consumption in sequential parts

Eliminates high activity (power) feedback muxes

Reduces capacitance on clock tree network

Benefits greatest when

High ratio of sequential elements

Large bus width designs

Non-throughput of one designs

Variable lifetimes are long (and static!)

Costs

Impact on clock tree synthesis and balancing

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115

Ver 1.4

Clock Gating

Clock the data registers only when there is new data

Power saving is design dependent (a range of 0 to 60%)

Typical network and control designs that “hold” a lot of

data is a “good fit” for clock gating.

Wider the bus widths, better the savings

AFTER Clock F S M Enable Latch F S M Clock Enable BEFORE 116

Manually generated Real Clocks

Tips: For your convenience, you can simply use

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117

Ver 1.4

Summary

Ports and Signals

covered the syntax of clock and it’s usage

Agenda: Day One

DAY

1

11

1

6

Topic Lab

Unit

7

(60)

119

Ver 1.4

Functionality Description - 1

Functionality is described in processes.

Processes are like functions that are executed whenever their inputs change.

Some processes execute when called and return control to the calling function (behave like a function).

Some processes are called once, and then can suspend themselves and resume execution later (behave like threads).

Processes are not hierarchical

Cannot have a process inside another process (use module for hierarchical design)

120

Functionality Description - 2

Processes use signals to communicate with each other.

Don't use global variables - may cause order dependencies in code (very bad).

Processes use timing control statements to implement synchronization and writing of signals in processes. Process and signal updates follow the evaluate-update