Design and Simulation of Start Frame Delimiter & Buffer of Ethernet MAC Receiver

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Volume 2, Issue 11, November 2013

Page 452

Abstract

The paper aims to provide suitable RTL design for MAC Receiver. Here the receiver supplies receive data to the host system from the receive data stream. It detects the preamble and SFD, checks the length field, and executes CRC check. Status information on each received packet, such as the number of received bytes and occurrence of errors, is written to a register after reception has been completed.

What is Ethernet?

Ethernet is the most widely used local area network (LAN) technology. The original and most popular version of Ethernet supports a data transmission rate of 10 Mb/s. Newer versions of Ethernet called "Fast Ethernet" and "Gigabit Ethernet" support data rates of 100 Mb/s and 1 Gb/s (1000 Mb/s). Ethernet devices compete for access to the network using a protocol called Carrier Sense Multiple Access with Collision Detection (CSMA/CD)

System Diagram

Here we are using data sheets of 82595 TX-Ethernet Controller provided by Intel and µPD98431 10/100 Mbps Ethernet Controller by NEC corporation for specification.

Receiver Processing Algorithm

Figure 1: Receiver Algorithm

IEEE 802.3 Frame Format

The frame format of IEEE802.2 is shown below

Figure 2: MAC Frame IEEE 802.2

Design and Simulation of Start Frame Delimiter

& Buffer of Ethernet MAC Receiver

Sandeep Kalundrekar 1 , Amit Singh Rajput2

1,2

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Volume 2, Issue 11, November 2013

Page 453

Block Diagram

Figure 3: Internal Block Diagram of Ethernet MAC Receiver

The Receiver Subsystem

1. SFD Detector: This component helps in the detection of the start of the packet.

2. Buffer: This is the buffer that forms the entry point of data into the receiver. This may or may not pass on the data to the memory based on the state of the receiver.

3. Address Matching Logic: This component verifies whether the data coming in is actually of concern or not. It compares the destination address of frame with host destination address.

4. FCS Checker: This component does the error checking by computing the CRC and then checking it with the trailer of the frame.

5. Controller: This is component that forms the glue between all the other component

Work

In this paper we are giving simulation Buffer & SFD.

Buffer

Signal Type Description

rx_data[3:0] In Data (nibble)transferred from MII

data [3:0] Out Data (nibble)transferred from buffer to FIFO

data_sa 3:0] Out Data (nibble)transferred from buffer to SFD detector and AML

data_enable In Enable signal from rx state machine to open the buffer and lets data[3:0] delivered to FIFO

Clock In Clock signals from MII

reset_n In Active low signals that initializes the receive MAC function

Table 1: Signal Descriptions of Buffer

Description

The function of this module to do data de capsulation. This module continues gives data to SFD detector and AML. And pass rx_data to the FIFO when darta_enable is high. It means it hold packet data .i.e. when data_enable is high then only it can pass data to FIFO.

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Volume 2, Issue 11, November 2013

Page 454

rseet_n=0 data_sa=0000 data_temp=0000 data_sa=rx_data data_temp=data_sa data_enable=1 data=data_temp data=zzzz stop start yes no no yes

Figure 3: Flow Chart of Buffer

Start Frame Delimiter

Signal Type Description

sfd_start_detect In A single clock signals gives instruction to SFD detector to begin to detect the SFD

data_sa[3:0] In Data (nibble) transferred from MII

sfd_detected out This signal indicates that SFD has detected.

Clock In Clock signals from MII

reset_n In Active low signals that initializes the receive MAC function

Table 2: Signal Descriptions of SFD

Description

SFD_Detector has the data flowing in through the data_sa. When the module receives a sfd_start_detect signal, it starts detecting SFD bits in the preamble, when it detects the SFD, it enables the sfd_detected signal.the sfd_start_check signal come from controller State Machine that launched after rx_dv asserted This module is control by controller ,when ever MII sense carrier on cable it give rx_data_valid signal to controller, now controller know that some frame is coming ,and now it has to receive it. We can say that when rx_data is coming SFD_start_detect signal will high and will be high until SFD_detected equal to one, after that it will become zero.

Flow Chart rseet_n=0 sfd_detected=0 sfd_start_detect=0 stop start yes no no yes data_sa=1011 sfd_detected=1 yes no

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