Experiment Manual

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University of Santo Tomas

Faculty of Engineering

Information and Computer Science Department

(Logic Circuit with Digital Circuit Design)

aboratory Manual

Raul B Ponay

Eugenia P Ramirez

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IT102L

IT102L Logic Circuit DesignLogic Circuit Design IT

IT Department Department Version Version 2011-2012011-2012-2nd2-2nd Page 1 of 50 Page 1 of 50

EXPERIMENT 1:

EXPERIMENT 1: ...

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D

IGITAL TRAINER ANDIGITAL TRAINER AND

SSI

SSI G

G

ATESATES

F

AMILIARIZATIONAMILIARIZATION... 2... 2

EXPERIMENT 2:

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L

OGICOGIC

G

ATESATES

T

RUTHRUTH

T

ABLEABLE

D

ERIVATIONERIVATION ... 11... 11

EXPERIMENT 3:

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C

OMBINATIONALOMBINATIONAL

C

IRCUITIRCUIT

:: L

L

OGICOGIC

G

ATE INTERCONNECTIONATE INTERCONNECTION... ... 1515

EXPERIMENT 4:

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S

IMPLIFICATION OFIMPLIFICATION OF

B

OOLEANOOLEAN

E

XPRESSION XPRESSION ... ... .... 1919

EXPERIMENT 5:

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A

DDER ANDDDER AND

S

UBTRACTERUBTRACTER

C

IRCUITIRCUIT ... ... ... 2222

EXPERIMENT 6:

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NAND-NAND

AND AND

NOR-NOR

NOR-NOR II

MPLEMENTATIONSMPLEMENTATIONS ... 27 ... 27

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D

ECODERECODER

C

IRCUITIRCUIT ... ... .... 3333

EXPERIMENT 8:

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M

ULTIPLEXERULTIPLEXER

II

MPLEMENTATIONMPLEMENTATION ... ... ... 3838

EXPERIMENT 9:

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B

ASICASIC

F

LIPLIP

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FLOPSFLOPS ... ... ... 4242

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S

EQUENTIAL LOGICEQUENTIAL LOGIC

C

IRCUITIRCUIT ... ... 4747

The breadboard or protoboard serves as the temporary circuit board for The breadboard or protoboard serves as the temporary circuit board for experimental circuit. The components are placed in the board and connected experimental circuit. The components are placed in the board and connected using solid wires (jumpers). Additional breadboard can be used if the circuit is using solid wires (jumpers). Additional breadboard can be used if the circuit is large and cannot be accommodated in the board provided in the trainer.

large and cannot be accommodated in the board provided in the trainer.

2.

2. Power SupplyPower Supply

The power supply provides a constant or regulated DC output voltage of 5V. this The power supply provides a constant or regulated DC output voltage of 5V. this power supply is the same power used all throughout the trainer.

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3.

3. LEDsLEDs

There are eight LEDs available. These are activated by supplying a TTL high to There are eight LEDs available. These are activated by supplying a TTL high to each of the corresponding terminal block pins.

each of the corresponding terminal block pins.

4.

4. SwitchesSwitches

There are eight available switches in the kit, six (Sw0 to Sw0) of which are There are eight available switches in the kit, six (Sw0 to Sw0) of which are ordinary toggle switched while the two others are debounced switches (Sw6 & ordinary toggle switched while the two others are debounced switches (Sw6 & Sw7). The common node of the single pole double throw switches is connected Sw7). The common node of the single pole double throw switches is connected to the wire holder while the other two nodes to ground and Vcc.

to the wire holder while the other two nodes to ground and Vcc.

5.

5. 7-segment Display7-segment Display

The two seven segment displays are driven by 7447 BCD-to-seven-segment The two seven segment displays are driven by 7447 BCD-to-seven-segment display decoders/drivers. The said driver has 4 inputs corresponding to the display decoders/drivers. The said driver has 4 inputs corresponding to the binary code of the desired decimal output on the seven segment display. Inputs binary code of the desired decimal output on the seven segment display. Inputs

not connected to any value are considered as ‘floating’ HIGH, thus causing the

display to turn off when not in use.

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6.

6. Digital ClocksDigital Clocks

Two clocks are provided by the kit, one having a fix frequency of 1KHz and the Two clocks are provided by the kit, one having a fix frequency of 1KHz and the other having a variable frequency of

3-other having a variable frequency of 3-

50Hz. “

OUTOUT

” is for the fix clock, and

“

OUT*OUT*

” is for

” is for variable clock.

variable clock.

7.

7. The Logic ProbeThe Logic Probe

Two logic probes are provided with logic LOW, HIGH, UNDEFINED/OPEN (not Two logic probes are provided with logic LOW, HIGH, UNDEFINED/OPEN (not high or low) CIRCUIT indicator. It is

high or low) CIRCUIT indicator. It is

labeled “

LP1LP1

” and “

LP2LP2

”

SSI Gates SSI Gates

Some TTL circuits as shown in Figure 1-1. Each IC is enclosed within a 14 or 16 Some TTL circuits as shown in Figure 1-1. Each IC is enclosed within a 14 or 16 pin package. A notch placed on the left side of the package is used as reference for the pin package. A notch placed on the left side of the package is used as reference for the pin numbers. The pins are numbered along the two sides starting from the notch and pin numbers. The pins are numbered along the two sides starting from the notch and continuing counterclockwise. The inputs and outputs of the gates are connected to the continuing counterclockwise. The inputs and outputs of the gates are connected to the package pins.

package pins.

The TTL IC’s are distinguished by their numerical designation, e.g. the 5400 and

7400 series. The former has a wide temperature range is suitable for military use, while 7400 series. The former has a wide temperature range is suitable for military use, while

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the latter has a narrower temperature range and is suitable for commercial use. The the latter has a narrower temperature range and is suitable for commercial use. The numerical designation of the 7400 series means that the IC packages are numbered as numerical designation of the 7400 series means that the IC packages are numbered as 7400, 7401, 7402, etc.

7400, 7401, 7402, etc.

The differences between the various TTL series are in their electrical The differences between the various TTL series are in their electrical characteristics, e.g., power dissipation, propagation delay, and switching speed. They do characteristics, e.g., power dissipation, propagation delay, and switching speed. They do not differ in pin assignment NOR on the logic operation performed by the internal not differ in pin assignment NOR on the logic operation performed by the internal circuits. For example, all the ICS listed in Table 1-1 with an 86 number, no matter what circuits. For example, all the ICS listed in Table 1-1 with an 86 number, no matter what the prefix, contain four exclusive OR gates with the same pin assignment in each the prefix, contain four exclusive OR gates with the same pin assignment in each package.

package.

MATERIALS MATERIALS

1

1 Logic ProbeLogic Probe 1

1 Fixed Fixed Power Power SupplySupply 1

1 ProtoboardProtoboard

1

1 Long Nose PliersLong Nose Pliers 1

1 Wire Stripper PliersWire Stripper Pliers Connecting Wires Connecting Wires 1

1 Digital Digital TrainerTrainer Integrated Circuits (ICs) Integrated Circuits (ICs) 1 1 74LS0074LS00 1 1 74LS0274LS02 1 1 74LS0474LS04 1 1 74LS0874LS08 1 1 74LS3274LS32 1 1 74LS8674LS86 PROCEDURES PROCEDURES 1.

1. Examine the ICs supplied to you. The IC number is printed on the surface of eachExamine the ICs supplied to you. The IC number is printed on the surface of each IC.

IC. 2.

2. Connect the 74LS00 as shown in Figure 1-2. Supply the IC with 5V and Ground.Connect the 74LS00 as shown in Figure 1-2. Supply the IC with 5V and Ground. 3.

3. Using the logic probe, test the status condition or logic level at the input and outputUsing the logic probe, test the status condition or logic level at the input and output terminals.

terminals. 4.

4. Of each gate in the IC. Record the logic values in the corresponding tables.Of each gate in the IC. Record the logic values in the corresponding tables. 5.

5. Remove the IC mounted on the protoboard and replace it with another IC.Remove the IC mounted on the protoboard and replace it with another IC. 6.

6. Repeat step 3 for each of the other ICs.Repeat step 3 for each of the other ICs. 7.

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Figure 1-1 Basic Gates Pin Configuration Figure 1-1 Basic Gates Pin Configuration 74LS08 - Quad 2-Input AND Gate

74LS08 - Quad 2-Input AND Gate

11 11 1 14 4 113 3 112 2 110 0 9 9 88 4 4 1 1 22 33 55 66 77 Vcc Vcc GND GND

74LS00 - Quad 2-Input NAND Gate 74LS00 - Quad 2-Input NAND Gate

11 11 1 14 4 113 3 112 2 110 0 9 9 88 4 4 1 1 22 33 55 66 77 Vcc Vcc GND GND 74LS04 - Hex Inverter 74LS04 - Hex Inverter 11 11 1 14 4 113 3 112 2 110 0 9 9 88 4 4 1 1 22 33 55 66 77 Vcc Vcc GND GND

74LS02 - Quad 2-Input NOR Gate 74LS02 - Quad 2-Input NOR Gate

11 11 1 14 4 113 3 112 2 110 0 9 9 88 4 4 1 1 22 33 55 66 77 Vcc Vcc GND GND

74LS86 - Quad 2-Input XOR Gate 74LS86 - Quad 2-Input XOR Gate

11 11 1 14 4 113 3 112 2 110 0 9 9 88 4 4 1 1 22 33 55 66 77 Vcc Vcc GND GND

74LS32 - Quad 2-Input OR Gate 74LS32 - Quad 2-Input OR Gate

11 11 1 14 4 113 3 112 2 110 0 9 9 88 4 4 1 1 22 33 55 66 77 Vcc Vcc GND GND

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1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 14 4 113 3 112 2 11 11 110 0 9 9 88 5V 5V V V_CC_CC GND GND Power Power Supply Supply conne

connection fction f or or logi

logic c pp roberobe

Figure 1-2 Experimental Circuit Set-up Figure 1-2 Experimental Circuit Set-up

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DATA AND RESULTS DATA AND RESULTS

Table 1-1 Test Results for 74LS00 IC Table 1-1 Test Results for 74LS00 IC

Input

Input Terminals Terminals Output Output TerminalsTerminals Pin Pin No. No. Logic Logic Level Level Pin Pin No. No. Logic Logic Level Level 1 1 33 2 2 66 4 4 88 5 11 5 11 9 9 10 10 12 12 13 13

Input

Input Terminals Terminals Output Output TerminalsTerminals Pin Pin No. No. Logic Logic Level Level Pin Pin No. No. Logic Logic Level Level 2 2 11 3 3 44 5 10 5 10 6 13 6 13 8 8 9 9 11 11 12 12

Input

Input Terminals Terminals Output Output TerminalsTerminals Pin Pin No. No. Logic Logic Level Level Pin Pin No. No. Logic Logic Level Level 1 1 22 3 3 44 5 5 66 9 9 88 11 10 11 10 13 12 13 12

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QUESTIONS QUESTIONS 1.

1. What is the logicWhat is the logic

al equivalent of the “hang” input?

________ ____________ 2.

2. Identify the following ICs with the same pin configuration.Identify the following ICs with the same pin configuration.

3.

3. Describe the pin configurations of 74LS02 and 74LS04 ICs.Describe the pin configurations of 74LS02 and 74LS04 ICs.

4.

4. Describe the functionalities of the Digital trainer.Describe the functionalities of the Digital trainer.

5.

5. What are the possible benefits in using digital trainer in the construction of digitalWhat are the possible benefits in using digital trainer in the construction of digital circuits?

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IT102L

IT Department Department Version Version 2011-

2011-2012-2nd 2012-2nd Page 11 of 50 Page 11 of 50 Experiment 2: Experiment 2:

Logic Gates Truth Table Derivation

OBJECTIVES OBJECTIVES

1.To study the operation of logic gates 1.To study the operation of logic gates

2.To demonstrate the derivation of the truth table for SSI gates. 2.To demonstrate the derivation of the truth table for SSI gates. 3.To determine whether the gates are working properly or not. 3.To determine whether the gates are working properly or not.

BASIC INFORMATION BASIC INFORMATION

Logic gates are building blocks of logic circuits that run computer hardware. Logic gates are building blocks of logic circuits that run computer hardware. Logic gates are the basic representation of the logical operations performed on Logic gates are the basic representation of the logical operations performed on Boolean expression. Functional operation of any binary expression can be translated Boolean expression. Functional operation of any binary expression can be translated to hardware via logic gates. They are fundamental in understanding more complex to hardware via logic gates. They are fundamental in understanding more complex digital circuitry.

digital circuitry. A

A truth truth table table defines defines a a logic logic operation by operation by a a list list of of the the output output of of the the operationoperation against all the possible input combinations.

against all the possible input combinations.

74LS00 74LS00

Input Output Input Output A

A BB

X=(AB)’

0 0 0 0 11 0 0 1 1 11 1 1 0 0 11 1 1 1 1 00 74LS08 74LS08 Input Output Input Output A A B B X= ABX= AB 0 0 0 0 00 0 0 1 1 00 1 1 0 0 00 1 1 1 1 11 74LS86 74LS86 Input Output Input Output A

A BB

X= (AB’+A’B)

0 0 0 0 00 0 0 1 1 11 1 1 0 0 11 1 1 1 1 00 74LS02 74LS02 Input Output Input Output A

A BB

X= (A+B)’

0 0 0 0 11 0 0 1 1 00 1 1 0 0 00 1 1 1 1 00 74LS32 74LS32 Input Output Input Output A

A B B X= A+BX= A+B 0 0 0 0 00 0 0 1 1 11 1 1 0 0 11 1 1 1 1 11 74LS04 74LS04 Input Output Input Output A

A

X= A’

0

0 11

1

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MATERIALS MATERIALS

1

1 Digital Digital Trainer Trainer 1 1 Cutter Cutter plierspliers 1

1 Long Long nose nose pliers pliers Connecting Connecting wireswires Integrated Circuit (IC)

Integrated Circuit (IC) 1 1 74LS00 74LS00 1 1 74LS0274LS02 1 1 74LS04 74LS04 1 1 74LS0874LS08 1 1 74LS32 74LS32 1 1 74LS8674LS86 PROCEDURE PROCEDURE 1. Wire the 74LS00 as

1. Wire the 74LS00 as shown in Figure 2-1. shown in Figure 2-1. Set the power supply to Set the power supply to 5V.5V. 2.

2. Test each IC (7400, 7402, 7404, 7408, Test each IC (7400, 7402, 7404, 7408, 7432, ad 7486) if all the 7432, ad 7486) if all the gates inside are workinggates inside are working properly.

properly. 3.

3. Testing is done by cTesting is done by comparing the output of the omparing the output of the IC with the IC with the output of the truth output of the truth tabletable using the flowchart below.

using the flowchart below.

Start Start

Connect the inputs (A, B) to Connect the inputs (A, B) to switches; connect the output (X) switches; connect the output (X)

to LED to LED

Set the switches based on the Set the switches based on the truth table values(A, B); compare truth table values(A, B); compare the output (X) with output in the the output (X) with output in the

DATA STATUS LED DATA STATUS LED

Is X= LED? Is X= LED?

Set the next input combination (A, Set the next input combination (A,

B) based on the truth table B) based on the truth table

Last input combination? Last input combination?

Logic gate is working Logic gate is working

properly properly

Logic gate is faulty Logic gate is faulty

YES YES YES YES NO NO NO NO End End

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4. Remove the IC mounted on the breadboard and replace it with another IC. 4. Remove the IC mounted on the breadboard and replace it with another IC. 5. Repeat step

5. Repeat step

for each of the other IC’s.

CIRCUIT DIAGRAMS / SCHEMETICS CIRCUIT DIAGRAMS / SCHEMETICS

Figure 2-1 Experimental Circuit Set-up Figure 2-1 Experimental Circuit Set-up

DATA GATHERING: DATA GATHERING:

Fill-up the table below

based on the testing procedure. Check (√) if the

based on the testing procedure. Check (√) if the gate is working

gate is working

properly. Write (X) if a particular gate is faulty. Take note:

properly. Write (X) if a particular gate is faulty. Take note: a faulty gate does nota faulty gate does not necessary make the other gates in one IC faulty as well.

necessary make the other gates in one IC faulty as well.

IC IC U1 U1 U2 U2 U3 U3 U4 U4 U5 U5 U6U6 7400 7400 NA NA NANA 7402 7402 NA NA NANA 7404 7404 7408 7408 NA NA NANA 7432 7432 NA NA NANA 7486 7486 NA NA NANA +5V +5V Terminal Terminal Ground Ground Terminal Terminal

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QUESTIONS: QUESTIONS:

Referring to the truth tables, write logical statements that suitably describes the function Referring to the truth tables, write logical statements that suitably describes the function table of each of the following basic gates:

table of each of the following basic gates: 1.

1. AND Gate AND Gate

2.

2. OR GateOR Gate

3.

3. INVERTERINVERTER

4.

4. NAND GateNAND Gate

5.

5. NOR GateNOR Gate

6.

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Combinational Circuit: Logic Gate interconnection

OBJECTIVES

1. To interconnect a basic logic gate IC with other basic logic gates. 1. To interconnect a basic logic gate IC with other basic logic gates. 2. To experimentally verify the output signal of the resulting circuit. 2. To experimentally verify the output signal of the resulting circuit. 3. To compare the certain gate combinations with existing basic gates. 3. To compare the certain gate combinations with existing basic gates. 4. To determine the equivalent truth table of the logic circuit

4. To determine the equivalent truth table of the logic circuit 5. To translate Boolean expression to logic circuit.

5. To translate Boolean expression to logic circuit.

Basic Information Basic Information

Combinational logic circuit (CLC) is a type of logic circuit composed of logic gates Combinational logic circuit (CLC) is a type of logic circuit composed of logic gates whose output is dependent entirely on the present or current input values. The circuit whose output is dependent entirely on the present or current input values. The circuit construction has well-formed (WF) structure meaning no feedback path; no 2 or more construction has well-formed (WF) structure meaning no feedback path; no 2 or more outputs of gates are tied together and only cascaded arrangements of logic gates. Simple outputs of gates are tied together and only cascaded arrangements of logic gates. Simple CLC is the direct translation of Boolean expression in different formats such as simplified CLC is the direct translation of Boolean expression in different formats such as simplified standard sum of product (SOP) format, standard format or canonical sum of product (SOP) standard sum of product (SOP) format, standard format or canonical sum of product (SOP) or product of sum (POS).

or product of sum (POS).

Combining or interconnecting logic gates forms a logic circuit. A logic circuit is an Combining or interconnecting logic gates forms a logic circuit. A logic circuit is an electronic circuit that processes information by performing logical operations on it. In logic electronic circuit that processes information by performing logical operations on it. In logic circuits, there are only two possible levels for the input and output signals: HIGH and LOW, circuits, there are only two possible levels for the input and output signals: HIGH and LOW, numerically represented by the binary digits 1 and 0, respectively.

numerically represented by the binary digits 1 and 0, respectively.

The output signal, using binary notation, is controlled by the logic circuit in The output signal, using binary notation, is controlled by the logic circuit in accordance with the input system. The basic logic gates are the AND, the OR, and the accordance with the input system. The basic logic gates are the AND, the OR, and the INVERTER (NOT). Often, certain combinations of logic gates are commonly used, e.g., a INVERTER (NOT). Often, certain combinations of logic gates are commonly used, e.g., a NAND circuit consists of NOT + AND logic gates, and a NOR for NOT + OR.

NAND circuit consists of NOT + AND logic gates, and a NOR for NOT + OR.

MATERIALS MATERIALS

1

1 Digital Digital Trainer Trainer 1 1 Cutter Cutter plierspliers 1

Integrated Circuit (IC) 1 1 74LS00 74LS00 1 1 74LS0274LS02 1 1 74LS04 74LS04 1 1 74LS0874LS08 1 1 74LS32 74LS32 1 1 74LS8674LS86 PROCEDURE: PROCEDURE: 1. Connect the

1. Connect the circuit shown circuit shown in Figure in Figure 3-13-1 2. Supply the circuit with +5V and ground. 2. Supply the circuit with +5V and ground.

3. Derive the truth table of the circuit and record the results. 3. Derive the truth table of the circuit and record the results.

4. Repeat Step 2 for the Figures 3-1(b), 3-2, 3-3, 3-4, and 3-5 respectively. 4. Repeat Step 2 for the Figures 3-1(b), 3-2, 3-3, 3-4, and 3-5 respectively.

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CIRCUIT DIAGRAMS / SCHEMETICS CIRCUIT DIAGRAMS / SCHEMETICS

X X A A B B Figure 3-5 Figure 3-5 A A B B X X Figure 3-4 Figure 3-4 A A B B X X Figure 3-2 Figure 3-2 A A B B X X Figure 3-3 Figure 3-3 A A XX Figure 3-1(b) Figure 3-1(b) A A XX Figure 3-1(a) Figure 3-1(a)

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DATA AND RESULTS: DATA AND RESULTS:

1.

1. Construct the theoretical truth tables for Figure 3-1 to Figure 3-5. Compare these withConstruct the theoretical truth tables for Figure 3-1 to Figure 3-5. Compare these with

the “actual” truth tables. Explain the discrepancies if any.

Figure 3-1(a)

A NAND ga

A NAND gate withte with input terminals input terminals

short-circuited. circuited. A A XX 0 0 1 1 Figure 3-1(b) Figure 3-1(b)

A NOR gate

A NOR gate with inputwith input terminals terminals short-circuited. circuited. A A XX 0 0 1 1 Figure 3-2 Figure 3-2

An AND gat

An AND gate withe with input terminals input terminals inverted (Bubbled inverted (Bubbled AND). AND). A A B B XX 0 0 00 0 0 11 1 1 00 1 1 11 Figure 3-3 Figure 3-3 Ad OR gate wi

Ad OR gate with inputth input terminals inverted terminals inverted (Bubbled OR). (Bubbled OR). A A B B XX 0 0 00 0 0 11 1 1 00 1 1 11 Figure 3-4 Figure 3-4 A combinat A combination ofion of INVERTER, AND, and INVERTER, AND, and

OR gates. OR gates. A A B B XX 0 0 00 0 0 11 1 1 00 1 1 11 Figure 3-5 Figure 3-5 A combinat A combination ofion of INVERTER, AND, and INVERTER, AND, and

OR gates. OR gates. A A B B XX 0 0 00 0 0 11 1 1 00 1 1 11

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2.

2. Referring to your DATA AND RESULTS, identify the corresponding basic logic gateReferring to your DATA AND RESULTS, identify the corresponding basic logic gate equivalent of each of the experimental circuit.

equivalent of each of the experimental circuit.

Figure

Figure EquivalentEquivalent_Gate_Gate Figure 3-1(a) Figure 3-1(a) Figure 3-1(b) Figure 3-1(b) Figure 3-2 Figure 3-2 Figure 3-3 Figure 3-3 Figure 3-4 Figure 3-4 Figure 3-5 Figure 3-5 3.

3. Is it possible for different Boolean expressions to have the same output? Why or whyIs it possible for different Boolean expressions to have the same output? Why or why not?

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Simplification of Boolean Expression

OBJECTIVES

OBJECTIVES 1.

1. To derive the experimental truth table from the given COMPLEX Boolean expression.To derive the experimental truth table from the given COMPLEX Boolean expression. 2.

2. To simplify the given Boolean expression using the algebraic simplification techniques.To simplify the given Boolean expression using the algebraic simplification techniques. 3.

3. To design and connect a logic circuit from the simplified circuit.To design and connect a logic circuit from the simplified circuit. 4.

4. To derive the actual truth table from the designed logic circuit.To derive the actual truth table from the designed logic circuit.

MATERIALS: MATERIALS:

1

1 Logic Logic Probe Probe 1 1 BreadboardBreadboard 1

1 Power Power supply supply 1 1 Cutter pliersCutter pliers 1

Integrated Circuit (IC) 1 1 74LS00 74LS00 1 1 74LS0274LS02 1 1 74LS04 74LS04 1 1 74LS0874LS08 1 1 74LS32 74LS32 1 1 74LS8674LS86 PROCEDURE: PROCEDURE: 1.

1. Examine the Examine the ICs supplied ICs supplied to to you. you. The number The number is is printed on printed on the surface the surface of each of each IC.IC. 2.

2. Given the COMPLEX Boolean expression in Table 1, draw and construct theGiven the COMPLEX Boolean expression in Table 1, draw and construct the

corresponding combinational circuit to derive its truth table. Record the result in Table corresponding combinational circuit to derive its truth table. Record the result in Table 1: Truth Table A.

1: Truth Table A. 3.

3. Simplify the COMPLEX Boolean equation, please write your simplification solution andSimplify the COMPLEX Boolean equation, please write your simplification solution and record the simplified equation in Table 1: Simplified Equation.

record the simplified equation in Table 1: Simplified Equation. 4.

4. Draw the Logic circuit and construct the logic circuit to derive its truth table. Record theDraw the Logic circuit and construct the logic circuit to derive its truth table. Record the result in Table 1: Truth Table B.

result in Table 1: Truth Table B. 5.

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Table 1: Table 1: COMPLEX EQUATION: COMPLEX EQUATION: F F

= ZX + ZX’Y

SIMPLIFICATION SOLUTION: SIMPLIFICATION SOLUTION: SIMPLIFIED EQUATION: SIMPLIFIED EQUATION: F = F = Truth

Truth Table Table A A Truth Truth Table Table BB X X Y Y Z Z F F X X Y Y Z Z FF 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 1 1 0 0 0 0 11 0 0 1 1 0 0 0 0 1 1 00 0 0 1 1 1 1 0 0 1 1 11 1 1 0 0 0 0 1 1 0 0 00 1 1 0 0 1 1 1 1 0 0 11 1 1 1 1 0 0 1 1 1 1 00 1 1 1 1 1 1 1 1 1 1 11 COMPLEX

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IT Department Department Version Version 2011-202011-2012-2nd12-2nd Page 21 of 50 Page 21 of 50 Table 2: Table 2: COMPLEX EQUATION: COMPLEX EQUATION: C =

C =

A’B’ + AB + A’B

SIMPLIFICATION SOLUTION SIMPLIFICATION SOLUTION SIMPLIFIED EQUATION: SIMPLIFIED EQUATION: C = C = Truth

Truth Table Table A A Truth Truth Table Table BB

A A B B C C A A B B CC 0 0 0 0 0 0 00 0 0 1 1 0 0 11 1 1 0 0 1 1 00 1 1 1 1 1 1 11 COMPLEX

COMPLEX EQUATION EQUATION LOGIC LOGIC CIRCUIT CIRCUIT SIMPLIFIED SIMPLIFIED EQUATION EQUATION LOGIC LOGIC CIRCUITCIRCUIT

1.

1. Compare Truth Table A and Truth Table B are the result the same? Explain anyCompare Truth Table A and Truth Table B are the result the same? Explain any discrepancies?

discrepancies?

2.

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Adder and Subtracter Circui

Adder and Subtracter Circuitt

1.

1. To study the operation of basic adders and subtractersTo study the operation of basic adders and subtracters 2.

2. To construct simple adders and subtractersTo construct simple adders and subtracters 3.

3. To design adders or subracters for digital application.To design adders or subracters for digital application.

Arithmeti

Arithmetic operations are c operations are very important in very important in digital and computer processes. The digital and computer processes. The designdesign of them can be

of them can be built from the basic adders and built from the basic adders and subtractersubtracters, in particular the half-adder ands, in particular the half-adder and full-adder.

full-adder.

Half-adder Half-adder

Half-adder is a combinational circuit that performs addition of two bits. The design is Half-adder is a combinational circuit that performs addition of two bits. The design is shown below:

shown below:

A

A B B SUM SUM CARRYCARRY 0 0 0 0 0 0 00 0 0 1 1 1 1 00 1 1 0 0 1 1 00 1 1 1 1 0 0 11

The simplified Boolean functions for the two outputs can be obtained directly from the The simplified Boolean functions for the two outputs can be obtained directly from the truth table. The simplified sum of products expressions are:

truth table. The simplified sum of products expressions are:

SUM= A’B + AB’ = A XOR B

CARRY = AB CARRY = AB

Full-adder Full-adder

Full-adder is a combinational circuit that forms the arithmetic sum of three input bits. Full-adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. It can be obtained using two half-adders as It consists of three inputs and two outputs. It can be obtained using two half-adders as shown below: shown below: XOR2 XOR2 AND2 AND2 SUM SUM CARRY CARRY

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IT Department Department Version Version 2011-202011-2012-2nd12-2nd Page 23 of 50 Page 23 of 50 A A B B SUM SUM CARRY CARRY SUM SUM CARRY CARRY C C A A B B X1 X1 X2 X2 halfadder halfadder halfadder halfadder OR2 OR2 SUM SUM CARRY CARRY

The sum of half-adder X1 is added to C via the next half-adder X2. The two carries are The sum of half-adder X1 is added to C via the next half-adder X2. The two carries are ORed to get the correct value.

ORed to get the correct value.

Half- Subtracters Half- Subtracters

A half-subt

A half-subtracter is racter is a combinaa combinational cirtional circuit that cuit that performs performs subtractsubtraction on tion on two bits awo bits andnd produces their difference.

produces their difference.

A

A B B DIFF DIFF BORROWBORROW 0 0 0 0 0 0 00 0 0 1 1 1 1 11 1 1 0 0 1 1 00 1 1 1 1 0 0 00

The simplified Boolean functions for the two outputs can be obtained directly from the truth The simplified Boolean functions for the two outputs can be obtained directly from the truth table. The simplified sum of products expressions are:

table. The simplified sum of products expressions are:

DIFF = A’B

BORROW = AB’ + A’B = A XOR

BORROW = AB’ + A’B = A XOR B

B

Full - Subtracter Full - Subtracter

A full-subt

A full-subtracter is racter is a combinaa combinational cirtional circuit that cuit that performs performs a subtraca subtraction of ttion of three bitshree bits. It. It consists of three inputs and two outputs. It can be obtained using two half-subtracter as consists of three inputs and two outputs. It can be obtained using two half-subtracter as shown below: shown below: XOR2 XOR2 AND2 AND2 BORROW BORROW A A B B DIFF DIFF

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A A B B DIFF DIFF BORROW BORROW C C A A B B X1 X1 X2 X2 halfsubtracter halfsubtracter halfsubtracter halfsubtracter OR2 OR2 DIFF DIFF BORROW BORROW DIFF DIFF BORROW BORROW MATERIALS: MATERIALS: Digital

Digital Trainer Trainer 1 1 Long Long nose nose plierspliers Connecting wires

Connecting wires

Integrated Circuit (IC) Integrated Circuit (IC) 1 1 74LS04 74LS04 1 1 74LS0874LS08 1 1 74LS32 74LS32 1 1 74LS8674LS86 PROCEDURE: PROCEDURE:

1. Examine the ICs supplied to

1. Examine the ICs supplied to you. you. The number is printed on the The number is printed on the surface of each IC.surface of each IC. 74LS04 74LS08

74LS04 74LS08 74LS32 74LS86 74LS32 74LS86

2. Connect the circuit given above for half-adder and half-subtracter. Verify the truth table. 2. Connect the circuit given above for half-adder and half-subtracter. Verify the truth table. 3. Fill the truth table for full-adder and full-subtracter.

3. Fill the truth table for full-adder and full-subtracter.

4. Draw the equivalent logic circuit for full-adder and full-subtracter. Show complete 4. Draw the equivalent logic circuit for full-adder and full-subtracter. Show complete

solution. solution.

5. Construct the circuit in the digital trainer and verify if the output if there are 5. Construct the circuit in the digital trainer and verify if the output if there are

discrepancies. discrepancies.

FULL-

FULL- ADDER ADDER FULL-SUBTRACTERFULL-SUBTRACTER INPUT

INPUT OUTPUT OUTPUT INPUT INPUT OUTPUTOUTPUT A

A B B C C SUM SUM CARRY CARRY A A B B C C DIFF DIFF BORROWBORROW 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 1 1 0 0 0 0 11 0 0 1 1 0 0 0 1 0 1 00 0 0 1 1 1 1 0 1 0 1 11 1 1 0 0 0 0 1 0 1 0 00 1 1 0 0 1 1 1 0 1 0 11 1 1 1 1 0 0 1 1 1 1 00

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IT Department Department Version Version 2011-202011-2012-2nd12-2nd Page 25 of 50 Page 25 of 50 K-map: K-map: Full-Adder Full-Subtracter Full-Adder Full-Subtracter

6. Design an adder/ subtracter combo (A+B/ A-B) using full-adder by adding another signal 6. Design an adder/ subtracter combo (A+B/ A-B) using full-adder by adding another signal S. when S=0, the circuit performs addition but when S=1, the circuit performs subtraction. S. when S=0, the circuit performs addition but when S=1, the circuit performs subtraction. Hint: Draw, construct, test and fill-up the truth table below.

Hint: Draw, construct, test and fill-up the truth table below.

ADDER/ SUB

ADDER/ SUBTRACTERTRACTER

INPUT OUTPUT

S

S B B C C SUM/DIFFSUM/DIFF CARRY/CARRY/ BORROW BORROW 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1

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ADDER/SUBTRACTER CIRCUIT: ADDER/SUBTRACTER CIRCUIT:

1.

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NAND-NAND and NOR-NOR

NAND-NAND and NOR-NOR Implementations

Implementations

OBJECTIVES

1.

1. To study To study universal gates: NAND universal gates: NAND and NORand NOR 2.

2.

To simplify the given functions using SOP (considering 1’s) and POS (considering 0’s)

solutions.

solutions. 3.

3. To construct NAND-NAND and NOR-NOR Networks.To construct NAND-NAND and NOR-NOR Networks. 4.

4. 0To translate standard format to NAND or NOR format.0To translate standard format to NAND or NOR format. 5.

5. To experimentally derive the truth tables of NAND-NAND and NOR-NOR networks andTo experimentally derive the truth tables of NAND-NAND and NOR-NOR networks and compared these with their theoretical truth tables.

compared these with their theoretical truth tables.

Digital circuits are more frequently constructed with NAND or NOR gates. NAND or Digital circuits are more frequently constructed with NAND or NOR gates. NAND or NOR are easier to fabricate with electronic components and are the basic gates used in all NOR are easier to fabricate with electronic components and are the basic gates used in all IC digital logic families. Because of the prominence of NAND and NOR gates in the design of IC digital logic families. Because of the prominence of NAND and NOR gates in the design of digital circuits, rule and procedure have been developed for conversion from Boolean digital circuits, rule and procedure have been developed for conversion from Boolean functions implemented with AND, OR and NOT into equivalent NAND and NOR logic functions implemented with AND, OR and NOT into equivalent NAND and NOR logic diagrams.

diagrams.

NAND Implementations NAND Implementations

The implementations of a Boolean function with NAND gates require that the function be The implementations of a Boolean function with NAND gates require that the function be simplified in the Sum of Products (SOP) form. The following rule and procedures are simplified in the Sum of Products (SOP) form. The following rule and procedures are observed for obtaining the NAND logic diagram from a Boolean function.

observed for obtaining the NAND logic diagram from a Boolean function. 1.

1. Simplify the function and express it in SOP form.Simplify the function and express it in SOP form. 2.

2. Draw a NAND gate for each product term of the function that has at least two literals.Draw a NAND gate for each product term of the function that has at least two literals. The inputs to each NAND gate are the literals of the term. This constitutes a group of The inputs to each NAND gate are the literals of the term. This constitutes a group of first-level gates.

first-level gates. 3.

3. Draw a single NAND gate in the second level with inputs coming from the outputs of theDraw a single NAND gate in the second level with inputs coming from the outputs of the first-level gates.

first-level gates. 4.

4. A A term term with with a a single single literal literal requires requires an an inverter inverter in in the the first first level level or or may may bebe complemented and applied as an input to the second-level NAND gate.

complemented and applied as an input to the second-level NAND gate.

NOR Implementations NOR Implementations

The NOR function is the dual of the NAND function. For this reason all procedures The NOR function is the dual of the NAND function. For this reason all procedures and rules for the NOR logic are the duals for the corresponding procedures and rules and rules for the NOR logic are the duals for the corresponding procedures and rules developed for NAND logic.

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The implementation of a Boolean function with NOR gates requires that the function The implementation of a Boolean function with NOR gates requires that the function be simplified in Product of Sums (POS) form. The rules and procedures for obtaining the be simplified in Product of Sums (POS) form. The rules and procedures for obtaining the NOR logic diagram from a Boolean function is similar to the three-step NAND rule, except NOR logic diagram from a Boolean function is similar to the three-step NAND rule, except that the simplified expression must be in the Product of Sums and the terms for the that the simplified expression must be in the Product of Sums and the terms for the first-level NOR gates are the sum terms. A term with single literal requires a one-input NOR or level NOR gates are the sum terms. A term with single literal requires a one-input NOR or Inverter gate, or may be complemented and applied directly to the second-level NOR gate. Inverter gate, or may be complemented and applied directly to the second-level NOR gate.

Y = A’ =

Y = A’ = (AA)’ = (A+A)’

(AA)’ = (A+A)’

A A NA NA ND ND or a or a NOR can be used to replace by an inverter by tying the inputs together.

NOR can be used to replace by an inverter by tying the inputs together.

Y= AB = ((AB)’)’ = (A’+B’)’

NOR NOR NOR NOR NAND2 NAND2 NAND2 NAND2 A A B B Y Y A A B B Y Y AND2 AND2 A A B B Y Y

Y= A + B = ((A + B)’)’ = (A’B’)’

N NOORR2 2 NNOORR22 NAND2 NAND2 OR2 OR2 Y Y Y Y A A B B A A B B A A B B Y Y NOR NOR NAND2

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IT102L

Y = A XOR B = ((AB’)’(A’B)’)’ = (((A’+B)’ + (A+B’)’)’

NAND2 NAND2 NAND2 NAND2 NAND2 NAND2 NAND2 NAND2 NAND2 NAND2 Y Y A A B B NOR NOR NOR NOR NOR NOR NOR NOR NOR NOR NOR NOR B B A A Y Y A A B B Y Y MATERIALS: MATERIALS: 2

2 Long Nose PliersLong Nose Pliers 2

2 Wire Stripper PliersWire Stripper Pliers

Connecting Wires Connecting Wires 1

1 Digital Digital TrainerTrainer

Integrated Circuits (ICs) Integrated Circuits (ICs) 2 2 74LS0074LS00 2 2 74LS0274LS02 PROCEDURES: PROCEDURES: 1.

1. Plot the function in the map to simplify it. Consider tPlot the function in the map to simplify it. Consider t

he 1’s to obtain the SOP expression for

the NAND-NAND network. Do the same with map of the NOR-NOR network but this time the NAND-NAND network. Do the same with map of the NOR-NOR network but this time

using the 0’s for POS.

2.

2. After obtain After obtaining the sing the simplified fuimplified function frnction from the K-om the K-map, constmap, construct the ruct the theoretitheoretical truth cal truth tabletable of each network.

of each network. 3.

3. Test the logic level of each IC supplied and report any damage to the Laboratory TechnicianTest the logic level of each IC supplied and report any damage to the Laboratory Technician for immediate

for immediate replacemenreplacement.t. 4.

4. Connect the circuit as shown in Figure 7-2. Adjust the power to 5V.Connect the circuit as shown in Figure 7-2. Adjust the power to 5V. 5.

5. Derive the truth table of the circuit by applying logic combinations of 0 and 1 to the inputDerive the truth table of the circuit by applying logic combinations of 0 and 1 to the input variables according to the specified logic level in the truth table. Record the logic signal variables according to the specified logic level in the truth table. Record the logic signal values in the corresponding table.

values in the corresponding table. 6.

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Q(A,

Q(A, B, B, C, C, D) D) = = (0,1,2,3,7,(0,1,2,3,7,8,10) 8,10) + + d(5,6,11,15d(5,6,11,15))

1.

1. AND-OR N AND-OR Networketwork A.

A. K-K-

Map: SOP (encircle 1’s)

00 00 01 01 11 11 10 10 00 01 00 01 11 11 1010 B. Simplified Function: _________________________________ B. Simplified Function: _________________________________

C. Theoretical Truth Table C. Theoretical Truth Table

A

A B B D D Q Q A A

’ ’

BB

’ ’

DD

’ ’

BB

’ ’

DD

’ ’

A A

’ ’

DD 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1

D. Experimental Truth Table D. Experimental Truth Table

A A B B D D QQ 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1

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IT Department Department Version Version 2011-2012-2011-2012-2nd2nd Page 31 of 50 Page 31 of 50

2. OR-AND Network 2. OR-AND Network

A.

A. K-K-

Map: SOP (encircle 0’s)

00 00 01 01 11 11 10 10 00 01 00 01 11 11 1010 B. Simplified Function: _________________________________ B. Simplified Function: _________________________________

Figure 7-2 NAND-NAND Network Figure 7-2 NAND-NAND Network

Figure 7-3 NOR-NOR Network Figure 7-3 NOR-NOR Network

C. Theoretical Truth Table C. Theoretical Truth Table

A

A B B D D Q Q A A

’ ’

BB

’ ’

DD

’ ’

A A

’+

D D A A

’+

DD

’ ’

0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1

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D. Experimental Truth Table D. Experimental Truth Table

A A B B D D QQ 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 QUESTIONS: QUESTIONS: 1.

1. Explain in your own words, the procedure for implementing Boolean function with:Explain in your own words, the procedure for implementing Boolean function with: A.

A. NAND-NAND NetworkNAND-NAND Network

B.

B. NOR-NOR NetworkNOR-NOR Network

2.

2. What are the advantages and disadvantages of implementing logic circuit as NAND and NORWhat are the advantages and disadvantages of implementing logic circuit as NAND and NOR universal gates against standard formats such as POS and SOP?

universal gates against standard formats such as POS and SOP?

3.

3. Which implementation is better: NAND or NOR implementation? Why?Which implementation is better: NAND or NOR implementation? Why?

4.

4. Determine the NAND implementationDetermine the NAND implementation a.

a.

F(ABC) = Σ( 0, 3, 5,7)

5.

5. Determine the NOR implementation.Determine the NOR implementation. a.

a.

F(ABC) = Π ( 1,2,5,7)

***For 4 and 5: Draw the logic circuit at the back of this paper ***For 4 and 5: Draw the logic circuit at the back of this paper

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IT Department Department Version Version 2011-2012-2011-2012-2nd2nd Page 33 of 50 Page 33 of 50 Experiment 7: Experiment 7:

Decoder Circuit

OBJECTIVES: OBJECTIVES: 1.

1. To demonstrate the unique output lines of a decoder.To demonstrate the unique output lines of a decoder. 2.

2. To implement a full-adder circuit suing a decoder and two four-input NAND gates.To implement a full-adder circuit suing a decoder and two four-input NAND gates.

MATERIALS: MATERIALS: Digital Trainer Digital Trainer 1 1 74LS4774LS47 4

4 10Kohms 10Kohms resistorresistor 1

1 100 100 ohmsohms 1

1 LED LED displaydisplay

Decoders Decoders

A

A digital digital decoder decoder has has 22NN_{outputs and accepts N inputs. Only the output that}_{outputs and accepts N inputs. Only the output that}

corresponds to the binary number on the input lines is activated. Decoders are used in corresponds to the binary number on the input lines is activated. Decoders are used in many digital circuits. They can be used to select memory addresses, and to decode many digital circuits. They can be used to select memory addresses, and to decode instructions in a computer. They are used whenever only one line from several possible instructions in a computer. They are used whenever only one line from several possible lines must be selected.

lines must be selected.

TRUTH TABLE 3-TO-8 DECODER TRUTH TABLE 3-TO-8 DECODER

INPUT OUTPUT INPUT OUTPUT X Y Z D0 D1 D2 D3 D4 D5 D6 D7 X Y Z D0 D1 D2 D3 D4 D5 D6 D7 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 00 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 00 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 00 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 00 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 00 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 00 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11

The 3-to-8 decoder provides 8 unique output elements and 8 unique output The 3-to-8 decoder provides 8 unique output elements and 8 unique output combinations. The logic gate that can produce one unique output based on all input combinations. The logic gate that can produce one unique output based on all input combination is AND gate. So, in the design the 3-to-8 decoder has 8 AND gates.

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TRUTH TABLE: BCD TO DECIMAL DECODER TRUTH TABLE: BCD TO DECIMAL DECODER

INPUT OUTPUT INPUT OUTPUT D D C C B B A A 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 99 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 2 2 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 11 3 3 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 11 4 4 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 11 5 5 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 11 6 6 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 11 7 7 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 11 8 8 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 11 9 9 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 A A 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 B B 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 C C 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 D D 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 E E 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 F F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11

The BCD-to-Decimal decoder converts Binary Coded Digit to Decimal. There are The BCD-to-Decimal decoder converts Binary Coded Digit to Decimal. There are 10 unique output elements for 4-bit input combination. Only 10 out of 16 possible input 10 unique output elements for 4-bit input combination. Only 10 out of 16 possible input combinations result to the correct decoded output. The rest are incorrect since there combinations result to the correct decoded output. The rest are incorrect since there must be only 10 combinations for a decimal code. Notice the output is inverted meaning must be only 10 combinations for a decimal code. Notice the output is inverted meaning NAND gates are used instead of AND gate. TTL 74145 is a BCD-to-Decimal decoder that NAND gates are used instead of AND gate. TTL 74145 is a BCD-to-Decimal decoder that follows the above truth table.

follows the above truth table.

Seven-Segment Decoders Seven-Segment Decoders

A

A seven seven segment segment display display consists consists of of seven seven elements elements that that are are made made of of eithereither

LCD’s (liquid crystal

s) or LEDs (s) or LEDs (light-emlight-emitting diode). The elements are labeled from a-g.itting diode). The elements are labeled from a-g.

Seven segment indicators may be of the common

–

cathode type in which allcathode type in which all anodes are connected together. With the common-anode type, you have to connect a anodes are connected together. With the common-anode type, you have to connect a

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IT102L

IT Department Department Version Version 2011-202011-2012-2nd12-2nd Page 35 of 50 Page 35 of 50 +V +VCCCC a a bb cc dd ee f f gg _Gnd_Gnd g g f f d d c c b b ee a a

(a) common anode

(a) common anode (b) common cathode(b) common cathode

A seven-segment decoder-driver is an IC decoder t

A seven-segment decoder-driver is an IC decoder that can be used to

hat can be used to

drive a seven-segment indicator. There are two types of decoder drivers, one for

common anode indicators and the other for common-cathode indicators. Each

decoder-driver has 4-input pins (the BCD input) and 7 output pins (a through g

segments). A T

segments). A TTL 7447 requires a

TL 7447 requires a CA seven segment

CA seven segment display while

display while TTL 7448

TTL 7448

needs a CK seven segment display.

DATA GATHERING:

1. 1. Construct the circuit below.

Construct the circuit below.

s s w w i i t t c c h h e e s s DD C C B B A A V V CC CC GN GNDD a a b b c c d d e e f f g g 16 16 13 13 12 12 11 11 10 10 9 9 15 15 14 14 8 8 6 6 2 2 1 1 7 7 100 100 5V 5V a a b b c c d d e e f f g g C CAA

74

74 LS

LS

47

Seven-segment Seven-segment display display a a b b c c d d e e f f g g 10k 10k

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2.

2. Fill the truth table.Fill the truth table.

D D C C B B AA LED LED DISPLAY DISPLAY 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 3.

3. Design a decoder for a seven segment display. The decoder will convert binary toDesign a decoder for a seven segment display. The decoder will convert binary to

octal. Show the solution and circuit design below. Write down the part’s name of

the TTL IC to be used. Write down also the pin assignment of each gate in the the TTL IC to be used. Write down also the pin assignment of each gate in the circuit.

circuit.

Truth Table: Truth Table:

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1.

1. What is the difference between decoder and encoder?What is the difference between decoder and encoder?

2.

2. Cite examples where encoder and decoders are used together.Cite examples where encoder and decoders are used together.

3.

3. What is the effect/display when pin#3 of 74LS47 is connected to the ground?What is the effect/display when pin#3 of 74LS47 is connected to the ground?

4.

4. What is the effect/display when pin#4 of 74LS47 is connected to the ground?What is the effect/display when pin#4 of 74LS47 is connected to the ground?

5.

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Multiplexer Implementation

1. To prove experimentally that MUX is a DATA SELECTOR. 1. To prove experimentally that MUX is a DATA SELECTOR. 2. To implement a given Boolean function using 4 x 1 MUX. 2. To implement a given Boolean function using 4 x 1 MUX. 3. To construct multiplexer as universal logic circuit.

3. To construct multiplexer as universal logic circuit.

Multiplexing is the transmission of large number of information units over a Multiplexing is the transmission of large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. line. The selection of a particular input line is controlled by a set of selection lines.

Normally, there are

Normally, there are 2 2 n n _{input lines and n}_{input lines and} _{n selection lines whose combinations}_{selection lines whose combinations}

determine which input is selected. A multiplexer is also called data selector since it determine which input is selected. A multiplexer is also called data selector since it selects one of many inputs and steers the binary information to the output line. It is selects one of many inputs and steers the binary information to the output line. It is often abbreviated as MUX. In general, a

often abbreviated as MUX. In general, a 2 2 n n _-to-1_-to-1_{line multiplexer is constructed from an}_{line multiplexer is constructed from an}

n-to-2

n-to-2 n n _line_{line decoder}_{decoder by adding to its 2}_{by adding to its 2}nn_{input lines, one to each AND gates. As in}_{input lines, one to each AND gates. As in}

decoders, multiplexer ICs also have an enable input to control the operation of the unit. decoders, multiplexer ICs also have an enable input to control the operation of the unit.

1C0 1C0 1C1 1C1 1C2 1C2 1C3 1C3 2C0 2C0 2C1 2C1 2C2 2C2 2C3 2C3 A A B B ~1G ~1G ~2G ~2G 1Y 1Y 2Y 2Y VCC VCC GND GND 74LS153 74LS153 14 14 2 2 6 6 5 5 4 4 3 3 10 10 11 11 12 12 13 13 1 1 15 15 16 16 8 8 7 7 9 9

This data selector/ multiplexer contains inverters and drivers to supply fully This data selector/ multiplexer contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR gates. Separate complementary, on-chip, binary decoding data selection to the AND-OR gates. Separate strobe inputs are provided for each of the two four-line sections. The TTL 74153 can be strobe inputs are provided for each of the two four-line sections. The TTL 74153 can be used to implement two 3-variable Boolean expressions as shown:

used to implement two 3-variable Boolean expressions as shown: Given:

Given:

MULTIPLEXER TRUTH TABLE MULTIPLEXER TRUTH TABLE select DATA

select DATA INPUTS INPUTS STROBE STROBE OUTPUTOUTPUT B B A A C0 C0 C1 C1 C2 C2 C3 C3 ~G ~G YY X X X X X X X X X X X X 1 1 00 0 0 0 0 0 0 X X X X X X 0 0 00 0 0 0 0 1 1 X X X X X X 0 0 11 0 0 1 1 X X 0 0 X X X X 0 0 00 0 0 1 1 X X 1 1 X X X X 0 0 11 1 1 0 0 X X X X 0 0 X X 0 0 00 1 1 0 0 X X X X 1 1 X X 0 0 11 1 1 1 1 X X X X X X 0 0 0 0 00 1 1 1 1 X X X X X X 1 1 0 0 11

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IMPLEMENTATION TABLE IMPLEMENTATION TABLE MUX

MUX 1 1 MUX MUX 22

IC0 IC1 IC2 IC3 2C0 2C1 2C2 2C3 IC0 IC1 IC2 IC3 2C0 2C1 2C2 2C3 ~C ~C 0 0 0 0 0 0 1 1 0 0 1 1 1 1 00 C C 1 1 1 1 1 1 0 0 0 0 1 1 0 0 00 C C C C C C ~C ~C 0 0 1 1 ~C ~C 00 1C0 1C0 1C1 1C1 1C2 1C2 1C3 1C3 2C0 2C0 2C1 2C1 2C3 2C3 2C4 2C4 A A B B ~1G ~1G ~2G ~2G 1Y 1Y 2Y 2Y VCC VCC GND GND 74LS153 74LS153 14 14 2 2 6 6 5 5 4 4 3 3 10 10 11 11 12 12 13 13 1 1 15 15 16 16 8 8 7 7 9 9 VCC VCC 5V 5V A A B B C C NOT NOT F1F1 F2 F2 GND GND MATERIALS: MATERIALS: 1

1 Digital Digital Trainer Trainer Connecting Connecting wireswires Integrated Circuit (IC)

Integrated Circuit (IC) 1

1 74LS04 74LS04 1 1 74LS15374LS153

1.

1. Write a procedure to test the function of the TTL74153. Verify the output withWrite a procedure to test the function of the TTL74153. Verify the output with the truth table. Draw the circuit.

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2.

2. Implement the function F1 (A, B, C) =Implement the function F1 (A, B, C) =

7) using multiplexer. Show complete solution. 7) using multiplexer. Show complete solution.

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1.

1. What part of the multiplexer circuit that determines input data selection?What part of the multiplexer circuit that determines input data selection?

2.

2. Which is more convenient implementing Boolean function using combinationalWhich is more convenient implementing Boolean function using combinational circuit or multiplexer circuit? Elaborate your answer.

circuit or multiplexer circuit? Elaborate your answer.

3.

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Basic Flip-flops

1. To study the operation of flip-flops. 1. To study the operation of flip-flops. 2. To construct different types of flip-flops 2. To construct different types of flip-flops

Flip-flop can be called bistable multivibrator is a basic memory element. It can be Flip-flop can be called bistable multivibrator is a basic memory element. It can be referred to as latch or memory cell as well. They can store one bit of information either referred to as latch or memory cell as well. They can store one bit of information either 0 or 1. The term bistable refers to its memory being stable at

0 or 1. The term bistable refers to its memory being stable at 0 when the input is 0 0 when the input is 0 andand stable at 1 when the input is 1. There are 4 basic flops namely: RS flop, D stable at 1 when the input is 1. There are 4 basic flops namely: RS flop, D flip-flop, T flip-flip-flop, and JK flip-flop. The circuit construction and operation are shown below: flop, T flip-flop, and JK flip-flop. The circuit construction and operation are shown below:

S S R R Q Q Q Q 0 0 11 11 11 ₁₁₁₁ 10 10 01 01

The state diagram clearly shows the operation of the RS flip-flop. Notice that when R The state diagram clearly shows the operation of the RS flip-flop. Notice that when R becomes 1 the state will go to 0, while when S becomes 1 the state will go to 1. Input becomes 1 the state will go to 0, while when S becomes 1 the state will go to 1. Input 11 will result to same state while input 00 will yield an illegal output ( Q = 1, ~Q=1). 11 will result to same state while input 00 will yield an illegal output ( Q = 1, ~Q=1).

R R S S ~Q~Q Q Q 0 0 11 11 11 ₁₁₁₁ 10 10 01 01

The NOR implementation shows that input 11 will yield illegal output while input 00 will The NOR implementation shows that input 11 will yield illegal output while input 00 will

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IT102L

IT Department Department Version Version 2011-202011-2012-2nd12-2nd Page 43 of 50 Page 43 of 50 D D Q Q ~Q ~Q 0 0 11 0 0 ₁₁ 0 0 1 1

The D-flip-flop shown above is a modified latch. The added NAND gate acts as inverter The D-flip-flop shown above is a modified latch. The added NAND gate acts as inverter and assures the input of the latch with only 01 and 10 combination. The input 0

and assures the input of the latch with only 01 and 10 combination. The input 0 represents reset and input 1 represents set. As shown in the state diagram. represents reset and input 1 represents set. As shown in the state diagram.

0

1

00

00 ₀₀

₀₀

01

10

11

0

01

1

10

0

The JK flip-flop shown above is a clocked flip-flop. By adding AND gates, the illegal The JK flip-flop shown above is a clocked flip-flop. By adding AND gates, the illegal inputs will never occur, instead a toggle condition will results to 11.