Soft-Switching in DC-DC Converters: Principles, Practical Topologies, Design Techniques, Latest Developments

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Soft-Switching in DC-DC Converters:

Principles, Practical Topologies,

Design Techniques, Latest Developments

Raja Ayyanar

Arizona State University

Ned Mohan

University of Minnesota

Eric Persson

International Rectifier

©2002, N. Mohan, R. Ayyanar, E. Persson APEC 2002

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Objectives

•

What is soft-switching?

•

Basic principles

•

Concentration on a few

popular topologies

•

Design techniques

•

Computer simulations

•

New developments

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What is Soft-Switching

•

Switching transitions occur under favorable

conditions – device voltage or current is zero

•

Reduced switching losses, switch stress,

possibly low EMI, easier thermal management

•

A must for very high frequency operation,

(also medium frequency at high power levels)

•

Usually involves compromises in conduction loss,

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Relationship Between Efficiency

and Power Density

0.8 0.82 0.84 0.86 0.88 0.9 0.92 0.94 0.96 0 50 100 150 200 250 300 350 400 450 500 Power Rating 20 loss P = W 10 loss P = W Efficiency 0 8. 0 84. 0 88. 0 92. 0 96. 100 200 300 400 500 0 1 out out loss out loss P P P P P η η η = + ∴ = −

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Hard-Switching

7 n+ p n− ds C gd C drain-body depletion layer gs C p n + gate source drain n+

Cross-sectional view of an n-channel MOSFET

MOSFET Characteristics

Output characteristics

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MOSFET Characteristics

( )

MOSFET model valid in

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Time

0s 0.5us 1.0us 1.5us 2.0us 2.5us 3.0us 3.5us 4.0us V(M1:d)/4 ID(M1)*2 V(R2:2) V(V3:+) -10 0 10 20 0 V1 50V 80 D2 I3 1A R2 25.0 M1 IRF150 R3 1m L2 40nH

Simulation of Hard Switching Converters

DS v gate input D i GS v Ideal diode IRF150

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Simulation of Hard Switching Converters

• Diode reverse recovery

Time

30.9500us 31.0000us 31.0500us 31.1000us

30.9154us 31.1299us -I(R3) V(M1:1)/3 V(M1:2) I(I1) 0 20.0 38.5 Time

32.95us 33.00us 33.05us 33.10us 33.15us 33.20us 33.25us 33.30us 33.34us -I(R3) V(M1:1)/3 V(M1:2) I(I1) 0 20.0 38.5 V1 100 R2 10 M1 MT B20N 20E V4 TD = 1u TF = 1n PW = 2u PER = {1/fs} V1 = 0 TR = 1n V2 = 15 PARAMETERS: fs = 100k R_LOAD = 1 I1 5A MU R 2020R D5 MTB20N20E MUR2020R Time

30.0us 30.4us 30.8us 31.2us 31.6us 32.0us 32.4us 32.8us 33.2us 33.6us 34.0us -I(R3) V(M1:1)/2 V(M1:2) I(I1) 0 20 40 -10 55 ds v gs v ds i o I ds v o I gs v ds i ds v ds i I_o gs v

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Problems of Hard-Switching

Possible Solutions (combination)

• Snubbers to reduce di/dt and dv/dt

• Circuit layout to reduce stray inductances

• Gate drive

• Soft switching to achieve ZVS and/or ZCS

Þ usually no change in losses (unless loss recovery)

Þ circuit layout

Þ turn on / off speeds

• Switching losses

• Device stress, thermal management

• EMI due to high di/dt and dv/dt

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Snubbers

•

Passive components (R, L, C) and a diode to shape

switching trajectories

Turn-on snubber (seldom used)

i t V L t T d s ( )= • low di/dt

• lower turn-on losses in the device • low reverse recovery current

Þ At turn-on

Þ Price to be paid at turn-off

• 1/2 LI2 _{energy dissipated during off interval}

• off interval > 2 to 3 times L_S /R_S time constant • switch voltage rating increases by R_S I_O

i_T L_s R_s I_o + - vT t V_d v_T i_T t 0 0 i_T L_s R_s I_o + - vT t V_d v_T i_T t 0 0

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Turn-off Snubbers

† At turn-off

• while builds up

• switch turn-off loss decreases

• lower dv/dt i_T I_o i_C S i_C D_S S = − ( flows through ) † Issues at turn-on • 1/2 CV2 _{energy dissipated in R} S and switch

• switch current rating increases by

• ON interval > 2 to 3 times R_S C_S time constant

v_T V_d / R_S i_T I_o + -v_T C_S R_S V_d D_S iCS i_T I_o + -v_T C_S R_S V_d D_S iCS v_T i_T I_o V_d 0 C_S 1 C_S 2 C_S 3 0 C_S C_S C_S 3 > 2 > 1 C_S=0 v_T i_T I_o V_d 0 C_S 1 C_S 2 C_S 3 0 C_S C_S C_S 3 > 2 > 1 C_S=0

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Soft-Switching

•

ZVS (Zero Voltage Switching)

•

ZCS (Zero Current Switching)

Advantages

- Lower losses (may be !)

- Low EMI (may be !)

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ZVS (Zero Voltage Switching)

Turn OFF Turn ON

• Switch voltage brought to zero before gate voltage is applied

• Ideal, zero-loss transition

• Low-loss transition

• Parallel capacitor as a loss-less snubber

• Preferred scheme for very high frequency applications using MOSFETs

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ZCS (Zero Current Switching)

Best suited for converters with IGBTs due to tail current at turn-off

• Switch current brought to zero before gate voltage is removed

• Ideal, zero-loss transition Turn OFF

Turn ON

• Low-loss transition

• Series inductor as a loss-less snubber

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ZVS and Hard-Switched Waveforms

Zero-voltage switched _{Hard-switched}

gate source v ₋ drain source v ₋ 12V − 12V gate source v ₋ drain source v ₋ 0V 0V 12V −

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An Example: Zero Voltage Transition (ZVT)

At t = 0, T+ is turned off ( ) ( ) 0 0 0 -C d C v v V + = = - d C C v ₊ +v =V d V + + − − Vo T+ T− D+ D− L L i C+ -C C i ₊ -C i A

Synchronous Buck Converter

L

i

19 - d C C Since v ₊ +v =V 0 -C C s s dv dv C C dt dt + + = 0 -C C i ₊ i ∴ + = 0 -C d C v v V + ∴ = = 0 d V - L C C Also, i ₊ - i =i 2 -L C C i i ₊ -i ∴ = =

• At the end of this charge/discharge interval, positive i_L is carried by

• Subsequently, is turned on; i_L must reverse direction D− T− d V + + − − Vo T+ T− D+ D− L L i s C+ -s C C i + -C i A

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Zero Voltage Transition

d V + + − − Vo T+ T− D+ D− L L i s C+ -s C C i + -C i A Conducting Devices 0 t 0 ’ t t₀" t1 t₁’ t2 t3 d V o V L i T+ D− T− None None D+ T+ None t t

( )

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Time

9us 10us 11us 12us 13us 14us 15us 16us 17us V(M2:d)/2 ID(M2)*2 V(M2:g) I(L1)*2 V(V8:+) -20 -10 0 10 20 0 L1 20uH IC = 2A V1 21V C2 1000uF IC = 10V M1 IRF150 M2 IRF150 V8 TD = {TDLY2} V7 TD = {TDLY1} R7 25 R8 25 PARAMETERS: PulseWidth = 4.5us Period = 10us TDLY1 = 5.5us TDLY2 = 0.5us R6 10.0

Simulation of a ZVT Buck Converter

DS v _inputgate D i GS v L i ZVT_buck.opj

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Classification of

Soft-Switching Schemes

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Load Resonant Converters

•

Converters with Resonant Switches (Quasi-

resonant, Multi-resonant)

•

Resonant Transition Converters

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† Makes use of switch capacitances and transformer leakage inductance and magnetizing current

Phase Shift Controlled

Full-Bridge Converter (ZVT)

• Poles A & B switched at nearly 50% duty-cycle

• Output voltage regulation is achieved by phase modulating the two pole outputs

48 T_A+ T_A− T_B− T_B+ D_b+ Db − D_a− D_a+ + − 2 d V o I A B a b + − 2 d V D_A+ D_A− D_B− D_B+ lT L 0 ficticious i_L + − in V i_AB + −vAB

Switching waveforms

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Transitions - Pole B

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Transitions - Pole A

• All four diodes conduct

• Leakage inductance resonates with switch capacitance

• Determination of T_del critical for ZVS design

• Load dependent ZVS D_b− D_a+ L i T_B+ + − o I A B a b d V T_A− T_A+ AB v AB i + -A A T to T t

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Methods to increase ZVS range

• Use of external series inductor

Disadvantages † Loss of volt-sec

higher turns-ratio higher

conduction loss _{VA ratings}increased

† Load dependent ZVS + − V_in + − V_o A B i_AB L_o L_series + − v_rect i_AB v_AB 0 left-leg v_rect

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Use of magnetizing current

Disadvantages

† higher conduction loss due to

• peak circulating current

• current through right-leg

MOSFETs

• peak magnetizing current independent of V_in

i_load + i_mag imag

A B + − V_in i_mag v_AB left leg

2

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ƒ Design of other parameters like L_o, C_o, transformer etc identical to hard switched PWM

Factors Affecting ZVS

™ Capacitance across MOSFETs – internal and external ™ Leakage inductance

™ Delay time

™ Magnetizing current ™ ZVS Load Range

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Designing for ZVS

(

)

( )

(

)

mag _ pk refl in,max

ds L . I I V C + ≥ 2 2 2 delay eq ds . T = π L . C Conditions for ZVS

MOSFET voltage during critical turn-on transition ds v t 2 2 LLk Cds π

55 A Possible Design Approach Using MathCAD

• Sweep for all practical values of

• •

• Calculate total losses. Iterate for different ZVS ranges

ds

C - based on limiting voltage rise during turn-off

delay

T - as a percentage of switching period

mag,pk lk

Calculate required I and L for each set

Calculate switch peak current and RMS current

Turn-off loss Conduction loss

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Designing for ZVS