Ethernet_Interface_Documentation_Package_Jun80.pdf

;-ANFORD CS()

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Ethernet Interface Documentation Pacl{age

John Seamons and Andreas Bechtolsheim Computer Science Department

Stanford University

June 30, 1980

This ~ t of documents describes a 3 Megabit Ethernet Interface developed by the Computer Science Department at Stanford University. The interface is designed to interconnect host computers to the Ethernet via a 16-bit parallel port.

The package contains:

* Function and Interface Description * Logic Schematics

* Prototype Layout

* Timing Diagrams

* State Machine Graphs

* State Machine Code

PrOject Heferance File Designer Rev

SUNet Ethernet Interface Clocks ei.acover.sil ,Iohn Seamons 3

..

Date Page

3 Jul 1980 18: 11 E.DOC[SUN,AVB] COMMENT e VALID 90897 PAGES

C REC PAGE DESCRIPTION

C00991 00001 C09002 99992

coaoos

00003 C00908 09094 COOOIB 99995 C00012 80006 COB91S 99097 C99018 ENDMK

Ce; .

Ethernet Interface Documentation Ethernet Receiver

Ethernet Transmitter Ethernet Controller DMA Controller: Controller Function:

3 Jul 1989 18:11 E.DOC[SUN,AVB] PAGE 2-1

Ethernet Interface Documentation

The Ethernet interface described in the following connects an Ethernet transceiver to one of three system interfaces:

1) A 8/16 bits parallel port.

2) The GPIB General Purpose Interface Bus.

3) A RS-422 high-speed serial line.

The interface is designed for full-duplex operation.

Thus loopback (sending to oneself) is possible for diagnostic purposes.

The Ethernet interface itself consists of three parts: a Receiver, a Transmitter, and a Controller.

The receiver converts serial data from the Ethernet into IS-bit parallel words.

A

Bit-vector address filter, which is loaded from the controller.

accepts only a selected set of destination addresses.

The receiver also straps the Ethernet leader bit and checks the CRee

The transmitter translates IS-bit parallel data into a serial data stream.

It prefixes the data stream with a leader bit and appends the CRC ,code

which it computes on the fly.

In addition, the transmitter jams the Ethernet if a collision is detected either by the transceiver or the receiver.

The controller performs the other functions necessary for a system level Ethernet interface: packet buffering, retransmission, and initialization.

The controller interfaces the Ethernet to either a 8/16 bit parallel port,

a GPIB port, or a high-speed serial line port.

These ports can be easily interfaced to almost any host computer.

The controller is implemented as a fast a-bit microcomputer system with

four DMA channels, Timer, and 4 kBytes of buffer memory.

If desired, the controller's·functionality can be replaced by a

"host" mini- or microcomputer system. However. the timing characteristics

of the Ethernet (one IS-bit word every 5.44 usee, retransmission within 37 usee)

3 Jul 1980 18: II

Ethernet Receiver

Receiver Interface:

R.Data <0:15) R.ReadO\ R.Readl\ R.Rcad\ R.Ready\ R.End\ R.Abort\ R.Ack\ R.Enable

R.FA <9:7)

R.FDin R.FWE\

Output Input Input Input Output Output Output Input Input

In/Out

Input" Input

Receiver Functions:

E.OOC[SUN,AVB] PAGE 3-1

Parallel Data.

Read Byte 0 (Bits <9:7». } Tie together for

Read Byte 1 (Bits <8:15». } 16 bit operatio~.

Clear flags. Tie to R.Read9/1. New data ready.

End of Message. Cleared by R.Ack.

Abort message in progress. Cleared by R.Ack. Clear R.End and R.Abort.

Initializes receiver state machine. Assert after initialization is complete. Fil ter Address.

Shift Register Output if R.Enable is asserted.

Fi lter Data In Filter Write Enable

If R.Enable non asserted, then receiver state machine is initialized. Address filter can be loaded via R.FA, R.FDin, and R.FWE\.

Address filter should be loaded before interface is enabled.

After R.Enable is asserted. receiver state machine wilJ enter flush state until carrier 1dle.

Receiver then listens continously to Ethernet. Phase Decoder acquires synchronization on Start Bit. Receiver state machine places data into shift register.

At the end of the first word it checks the address in the address vector. If Ethernet carrier drops, receive state machine checks

eRC and Bit-count. If both are correct. R.End flag is set. Otherwise and in the case of collision after the first R.Ready R.Abort is set.

Microcomputer system should throwaway aborted messages. (Number of aborted messages is expected to be very small.)

Response time requirements:

R.Ready to R.Read:

3 Jul 1989 18: 11

Ethernet Transmitter

Transmitter Interface:

T.Data (0:15)

T. Wr iteO\

T.Writel\ T.Write\ T.Ready\ T.Sent\ T.Abort\ T.Ack\ T.Enable

Input Input Input Input Output Output Output Input Input

Transmitter Functions:

LDOC[SUN,AVB] PAGE 4-1

Parallel Data.

Write Byte 9 (Bits <9:7». } Tie together for

Write Byte 1 (Bits (8:15». } 16 bit operation.

Clear flags. Tie to WriteS/l.

Ready to accept data. Cleared by T.Write. Message transmitted. Cleared by T.Ack. Message collided. Cleared by T.Ack. Clear T.Sent and T.Abort.

Enable transmit data driver to transceiver.

Can be used to terminate transmissions immediately. Should be held inactive after power-up to allow transmitter state machine to autoinitialize.

Transmitter is activated by writing first data word. Transmitter then attempts to aquire Ethernet.

Timeout function for aQuisition must be provided externally.

Transmission is terminated with CRe code if no more data is available.

Transmission is aborted upon collision reported by Transceiver or Phase Decoder. Retransmission function and algorithm must be provided externally.

Response time requirements:

T.Write to T.Ready: 5440 nsec (16 bit times).

3 Jul 1980 18:11 E.DOC[SUN,AVB] PAGE 5-1 Ethernet Controller

Controller Interface:

The controller supports one of three bidirectional data ports:

a parallel port, a

GPrs

port, and a

sro

port.

For a particular system, only one of these ports can be used. The particular port in use will be called ·local port·.

The interface is implemented via messages consisting of one 16-blt

command word that is optionally followed by a fixed number of data words. The length of the data field is limited to 512 words (1924 bytes).

Message Summar~:

Host to EthernetjController: Initialize

Load Address Filter with <n> address What is your fixed address?

Send following packet with <n> words, <words>*n

Ethernet Controller to Host:

My fixed address is <n>

Timeout on network aQuisition

I failed to send a packet despite 8 retries

3 Jul 1989 18:11 E.OOC[SUN,AVB] PAGE 6-1 OMA Controller:

All data transfers are handled by the 9517 OMA Controller. This DMA chip has four channels allocated as follows: Channel 9 Receiver

Channel 1 Receiver EOP Pointer -Channel 2 Transmitter

Channel 3 local Port

Chan 9: Autoinitialization implements cyclical buffer.

Save all receiver data in buffer (including bad messages) Chan 1: Autoinitjalization implements cyclical buffer.

Save current address and R.Abort on R.End.

Chan 2: Transfer fixed number of data words from buffer to transmitter. Chan 3: Transfer fixed number of data words between local port and buffer. The first two channels allow to receive back-to-back packets while

the buffer memory can be simultaneously unloaded to the local port. Both the channel for Receiver Data and EOP Address perform their task without intervention of the microprocessor and deposit their data items

into cyclical Queues in buffer memory.

In contrast, the local port Read/Write and Transmitter Data channel

are explicitel~ started under microcomputer control with a

definite wordcount, which is the length of the packet to be transferred. The Microcomputer is interrupted on EOP of a local port transfer

and on SENT from the transmitter. Note that SENT is set whenever the transmitter terminated its transmission, which might be on

3 Jul 1989 18: 11 E.OOC[SUN,AVB] PAGE 7-1

Controller Function:

Upon initialization (either hardware or command), the 8685 controller:

1) reads the fixed address and loads it into the address filter.

2) initializes the Ports

3) initializes the OMA device

4) cnables the receiver and the transmitter

5) enables interrupts

6) halts.

All further functions are interrupt driven (described below).

Interrupt routines:

Trap (edge and level. non-maskable)

not used because of difficulty to synchronize DHA device manipulation.

RST 7.5 (edge level)

TO (Timer: Count=O)

Timer is started on network aQuisition for timeout and on collision for retransmission.

At other times timer is running continously for random number generation. RST 7.5 Interrupt is disabled then.

RST 6.5 (1 eve 1)

.RX: Message arrived (Pointer and Status was queued by Channell) Reset Interrupt request

Check DMA Channel 1 current address to see how many pointers are pending.

Note that if last interrupt was asynchronous. no new message arrived. , Future Interrupts wi 11 aga in be handl ed synchronous 1y.

If Abort then throw packet away else put on received Queue. Send message to host that packet arrived •

. RST 5.5 (l eve 1 )

INTR:

TX: Message sent.

Check Collision Status.

Check whether DMA controller terminated transmission. Clear request.

If Collision then if collision count

<

8 then retry

else send host message about failure.

If port idle then write message header to port else put on queue.

(level)

I f port idle, then Intr .. Write Interrupt request else

Intr .. EOP channel 3.

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KI114A I FREQ123.538 AA12

9491 2 AA32, AJ12

93425A 1 AA42

745374 5 AC81, AEal, AEU; AE21, AJ21

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30-jun-80

Page

ANFOROi' Project

CSD SUNet Ethernet Interface Clocks

Designer Rev

ei .clocks.sil John Seamons 3

Date

1

42.5 nsec Clock

85 nsec Clock

t

Level 0

Rising

Edge

Falling

Edge

Level 1

0 0 - 0 0

0 0 - 01

0 0 - 1 0

0 0 - 11

0 1 - 00

0 1 - 01

0 1 - 10

0 1 - 11

1 0 - 00

1 0 - 01

1 0 - 1 0

1 0 - 11

1 1 - 00

1 1 - 01

1"\- 10

11 - 11

The Shift Register samples RX.Data every 42.5 nsec.

No Transition (0)

Gooel Transition (0-1), Start at 1

Bad Transition

Good Transition (0-1), Start at 2

Bad Transition

Bad Transition

Good Transition (1-0), Start at 1

No Transition (1)

No Transition (0)

Good Transition (0-1), Start at 1

Bad Transition

Bad Transition

Good Transition (1-0), Start at 2

Bad Transition

Good Transition ("I-a), Start at 1.

No Transition (1)

Since the Phase Decoder State Machine is clocl\ed at 85 nsec, each 85 nsec window has 4 possilJle cases (Level 0, Rising Edge, Failino Edge, Level 1). Thus there are 16 possible transitions between consecutive state machine states, which are shown above.

Data Transitions

~

[!)meout

I

Transitions

Windows _{Setup Data Window Too Few}

Duration

[DJ1]2

13 T

4]~ ~

1

7

:ril

~ E9.FE2113114Ii~

State Case 1

[:<

1:3 ..

[5

_J

7

9 (11 ..

:1

13:J~

State Case 2

I

_{2 4 [ 6 8],10}

I

₁₂

r

₁₄

State 0 meuns no carrier.

State measures time between data transitions in 42.5 nsec units.

State starts at 1 if data tmnsition falls in between 85 nS8C clocll, starts on 2 if dala transition on 85 nsec boundary. Duration of pulse is computed from current state, adjusted by + 1 if transition falls into middle of 85 nsec cycle.

ANFORO!

?,ojo," - [ "'/0'""'0 . - Filo Dosiglk"

ei.pdsr.sil John Seamons

GSD SUi'let Phase Decoder SR

_ - rq"o;_ ".. CICii....-,: .,,,.,

Rev 3

Date

30-jun-80

Page

I Transition No Transitions

State

>=

13?

Y;Y

No

DataO

/~

CARRIER

=

1

STATE

=

15

COLLlSlON

Jam

CARRIER=O

STATE

=

0

NOTHING

Em:J-Of-Packet

(0-0)

CARRIER = 0

STATE

=

0

NOH-liNG

Idle

CARRIER

=

1

STATE

=

+2

NOTHING

Active

(0-1 ) all others

CARRIER

=

1 CARRIER

=

0

STATE

=

1,2 STATE

=

0

DATA ONE COLLISION

Start Bit Lost .~ync

Duration = If 85-Transition then State else State -I-1

Bad Transitions

~ARRIER

=

1

3TATE

=

+ 2

';OLLISION

roo Many Transitions

ANFOHO Project Heference

2 .. 5 / .. 10

7000ci

Transitions

CARRIER

=

1 CARRIER

=

1

STATE

=

+ 2

NOTHING

Setup

STATE = 1,2

I

DataO

7~

DATA ONE DATA ZERO

Data Transition

File

CARRIER

=

1

STATE

=

1,2

COLLISION

Too Few Transitions

CSD SUNet Phase Decoder FSM ei.pclfsm.sil

Designer

I

Rev

John Seamons 3

~~CiU~~ T~~

C85.0·42 Pd.Carrier Pd.Oata Pd. Shift Rx.Ctear Counter

State idte

C85.0-42 Pd.Data

Pd.Shift

-,

SR Data 14

Rx.Fce\ Rx.Fdoul RX.Adrs Rx.WordO RX.Write Counter State

14 first word

15

Start Bit

L

_ _ _ _ _ _

- - - I

15

x=:x

x=:X

15

SR Full

o first word

o

o

other words

---.---.---

....

--

....

---~

C85.0-42 Pd. Carrier

Pd.Data

-,

Pd.Sllift

-,

SR Data 14 15

Hx.WordO

______________________ Jr

Rx.End

---~

Rx.Abort\

Rx.Clear Rx.Write Rx.CrcClr

---~---~

Counter

State first word

Reference

Gsa SUNet Receiver Timing

"~ '-,ANFORD

I

Project

.---~---15

flush

End of Packet

File Designer Rev

ei.rxtiming_sil John Seamons 3

o

Dale Page

1E~;bl;?-1 y~~

=-c

woo

{Enable}

-I

Fce\

I

no

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... I yes '-~ _yes

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no no

y

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_{End Idle}

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'10

I

no yes '-~ yes

I

I-71

Carrier?

~

>:

Event? ]

>j

Fce\ _I

>1

Word? _I /d Ad rs?

1----71

Write

no no

Invisible

First Word

- *

-

-

lI_1IIoI

L

Ino

'71

ca~>l

Event? : do'" "0

~:

Word? : '"

~rW;i1e

]

collision

I

End

l

W

no _Visible

I

Word?:

>;

Abort\ _I

I

yes

Other Words

1 P

[l]rCClr

I~

no. _{,Carner? .1-....} . 1....-

I

yes

Flush

ANFOHD Project Reference File

0."9""

~"

Pdge

GSD SUNet Receiver FSM ei.rxfsm.sil John Seamons 3 . 30-jun-80 1

""---...--C340.170·0 C170.85·0 Tx.Ready Pd.Carrier Tx.Go Tx.Load Tx.ldle Tx.SrDala TX.Crcin Tx.Data Setup Tr's Counter State

C340.170·0 Tx.Ready Tx.Word Tx.Load Tx.ldle Tx.SrData TX.Crcin TX.Data Setup Tr's Counter Slate

C340.170·0 TX.Word Tx.Go Tx.ldle TX.SrData TX.Crcin TX.Data Setup Tr's Counter State

CJ\NFORD

csa

..J

idle

Project

SUNet

-+

start bit (1)

J..

o o

15 o 2 3 4 5

send

Idle

I send·sendCRC only

send·send only

Send / Send CRC

'--_ ... 1

I

I forced zero by Ix.end! (no glitches)

14 15 o

send CRC idle

Shut Down

Reference File Designer Rev Dale Page

.... 1 ayes ... i . I no

r---...;/~'~i Ready? I 71 Car,ner?

J I - - - ,

Id!e i /

~L-_ _

-.Jf'-I

no,

Idle

yes

[

~--!~_,~"r-.

- - " ' " ' I I

J'

no yes yes

,~

I-Jam? I--;?'~ G~ 1I---3>~~d? i~i Ready? 1'--7>; Load

I

yes

I - - - l no

Send

no

[--rO

r

.'--7 '~ Go

-~-Send CRC

Oille

~..

I

OeS;!;lIer r

-_c_'s_'o ____

~_S_u_N_e_t

__

~

____

T_r_a_ns_i_n_it_te_r_r-_-S_M ____

~~_~_,m

__ .s_il __

~I~J_~_h_n_S_:_a_m

__

o_ns_.~~3

__ _L_3_0_-j_u_n_-8_0 __

~

___ 1 __

~

3 Jul 1989 18:Z4 PO.SAI[SUN,AVB]

begin "prmgen"

require "prom.sal" source!file; S256;

define

data9 datal dataZ data3 stateS statel stateZ state3

=[ a9],

=[al],.

=[aZ],

=[ a3],

=[ a4],

=[a5], =[a6],

=[ a 7],

$carrier=[d9],

Sdata =[dl],

Sshift =[d2], Scoll_i =[d3], Sstate8 =[d4], Sstatel =[d5], Sstate2 =[d6], $state3 =[d7],

3 Jul 1989

state active

onetransition zerotransition idl etransit ion goodtransition notransition

badtransition

85 transition

duration idle startbit lostsync -toomany setup datatrans toofew timeout jam eop

data zero data::::one collision start reset nextstate prombegin bit($carrier, bit($data, bit($shift, bit($coll_i, b1t($stateO, bi t( $statel, bit($state2, bit($state3,

18:24 PD.SAI[SUN,AVB] PAGE Z-1

=[«stateO + statel + stateZ + state3) div d4)], =[ (statetl!O)],

=[(~data2 A data9»), comment X9 ~ Xl;

=[(data2 A ~dataO)]. comment Xl ~ XO;

=[(~data3 A ~data2 A ~datal A ~dataO)], comment 99 ~ 00:

=[(onetransition v zerotransition»).

=[«~data2 A ~datal A ~dataO) comment XO ~ 00;

v (data2 A datal A dataO»]. comment Xl ~ 11;

=[(~goodtrans;tion A ~notransition»), comment all others;

=[(dataO A datal v ~dataO A ~datal)]. comment in sync with 85:

=[(if _85_transition then state else (state+1»),

=[(~active A idletransition)].

_ =[ (~act ive A onetransition

»).

=[(~active A ~(idletransition v onetransition»),

=[(attive A badtransition)],

=[(active A goodtransition A (2~duration~5»),

=[(active A goodtransition A (6~duration~19»],

=[(active A (goodtransition v badtransition) A (11~duration~15»],

=[(active A notransition A (13~state~15»),

=[(timeout A data9)].

=[(timeout A ~data9»),

=[(zerotransition A datatrans»).

=[«onetransition A datatrans) v startbit)],

=[(lostsync v jam v toomany v toofew)].

=[(startbit v lostsync v jam v datatrans v toofew)],

=[( idle V eop»),

=[(if reset then 9

else if (start A ~_85_transition) then 1

else if (start A _85_transition) then Z

else (state+2»];

(nextstate~O» ;

(collision v data_one»; (data_zero v data_one»;

( ~co 11 is i on» ;

(nextstate land dO»; (nextstate land dl»: (nextstate land d2»: (nextstate land d3»;

if (idle A (collision v data_zero v data_one»

then error ("illegal idle state!"):

if (collision A (idle v data_zero v data_one»

then error ("illegal collision state!");

if (data_zero A (idle v collision v data_one»

then error (";11ega1 data zero state!"):

if (data_one A (idle v collision

v

data_zero»

then error (" i 11 ega 1 data_one state!");

promend:

3 Jul 1980 18:05 RX.SAI[SUN,AVB]

begin "prmgen"

require "prom.sai" source!file; $256;

define

carrier data shift word adrs enablo state9 statel

$write Send

$abort i

$clear-i $crcclr $fce i $state9 $statel

=[aO], =[al], =[ a2],

=[ a3],

=[ 04

J,

=[05], =[a6],

=[ a7],

=[ dO

J,

=[dl].

=[ d2

J,

=[ d3

J,

=[ d4

J,

=[d5J,

=[ d6

J,

=[ d7],

3 Jul 1989

init state idle first word other-words flush -event nil collision d_zero done datatr visible invisible

end idle lostsync nextstate prombegin b1t($write, bit($end, bit($abort_i, bit($clear_i, bit(Scrcclr, . b1t($fce i, bit($state9, bit(Sstatel,

18:05 RX.SAI[SUN,AVB]

=[(.,enable)],

=[«statel + stateO) d1v d6»),

=[(state=O)], =[(state=l) ], =[(state=Z)], =[(state=3)],

=[«shift + data) div dl»),

=[(event=O)], =[ (event=l)], =[(event=Z)], =[( event=3)],

PAGE 2-1

=[(carrier A (d_zero v d_one v nil»],

=[(other_words A «.,carrier A .,word) v (carrier A collision»)],

=[(first_word A «<arrier) v (carrier A collision) v

(datatr A word A .,adrs»)],

=[(idle A carrier A .,word)],

=[(i~le A carrier A collision)],

=[(

if ( ! idle:

(idle A .,carrier) v

(idle A carrier A .,(collision vend_idle» v

(flush A .,carrier)

) then 9 else

if ( ! first_word:

(first_word A datatr A .,word) v

(end_idle)

) then 1 else

if ( ! other_words;

(first_word A datatr A word A adrs) v

(other_words A datatr)

) then Z else

i f ( ! flush:

(flush A carrier) v

(lostsync) v

(visible) v

(invisible) v

(other_words A .,carrier A word)

) then 3 else

error(cvs($$adrs)&": didn't assign any statel")

») :

(.,init A «first_word A datatr A word A adrs) v

(other_words A datatr A word»»;

(.,init A «visible) v (other_words A .,carrier A word»»;

.,(init v (visible»);

.,(init v (idle A .,carrier»);

(init v (flush A .,carrier»):

.,(init v (first_word A carrier A (d_zero v d_one»»;

(init v (nextstate land dO»): (init v (nextstate land dill);

promend:

3 Ju 1 1989

spare state idle send sendere start r.eload nextstate

18:25 TX.SAI[SUN,AVB]

=[(sparcO A sparel)],

=[«statel + stateS) div d6)],

=[ (state=9)], =[(state=l)], =[ (state=2)],

=[(idle A ready A ~carrier)],

=[(send A ~jam A word A ready)],

=[(if (~spare v (state=3)) then 8

else if ( ! idle;

(idle A (~ready v carrier)} v

«send v sendere) A jam} v

(sendere A ~jam A word)

) then 8 else

if ( ! send;

(start) v (reload) v

(send A .,jam A .,word) ) then 1 else

if ( I senderc;

(send A ~jam A word A .. ready) v

(sendere A .,jam A .,word)

PAGE 2-1

} th.en 2 else

error(cvs($$adrs)&w: didn't assign any state!W)

prombegin

bit($go, bit($go_i, bit($load, bit($load_i, bit($idle, bit($idle_i, bit($stateO, bit($statel,

)]:

(spareA «send v sendere) A ~jam})};

(spareA ~«send v sendcrc) A ~jam»);

(spareA reload»:

(spareA ~reload»;

(sp~reA (idle A ~start»):

(spqreA ~(idle A ~start.»):

(SpareA (nextstate land dO»); (spareA (nextstate land dl»):

promend;

3 Jul 1989 18:25

TX.SAI[SUN,AVB]

begin "prmgen"

require "prom.sai" source!file;

$256;

define

carrier jam word ready spare9 sparel state9 statel

$go $go:,..1

$load $load i

$idle-Sidle i $state9 $statel

=[ a9],

=[ a 1],

=[ a2], =[ a3], =[a4], =[a5], =[a6], =[a7],

=[d9], =[d11, =[d2],

=[ d3],

=[ d4],

=[d5], =[d6], =[d7],