• No results found

Electrical Properties of Grain Boundaries and Dislocations in Crystalline Silicon: Influence of Impurity Incorporation and Hydrogenation

N/A
N/A
Protected

Academic year: 2020

Share "Electrical Properties of Grain Boundaries and Dislocations in Crystalline Silicon: Influence of Impurity Incorporation and Hydrogenation"

Copied!
127
0
0

Loading.... (view fulltext now)

Full text

(1)

ABSTRACT

PARK, YONGKOOK. Electrical Properties of Grain Boundaries and Dislocations in Crystalline Silicon: Influence of Impurity Incorporation and Hydrogenation. (Under the direction of Professor George A. Rozgonyi.)

This thesis examines the electrical properties of grain boundaries (GBs) and dislocations in crystalline silicon. The influence of impurity incorporation and hydrogenation on the electrical properties of grain boundaries, as well as the electrical activity of impurity decorated dislocations and the retention of impurities at dislocations at high temperatures have been investigated.

(2)

The density of GB states before and after hydrogenation was evaluated by J-V, C-V and capacitance transient methods using gold/direct-silicon-bonded (DSB) (110) thin silicon top layer/(100) silicon substrate junctions. The GB potential energy barrier in thermal equilibrium was reduced by 70 meV. Whereas the clean sample had a density of GB states of ~6×1012 cm-2eV-1 in the range of Ev+0.54~0.64 eV, hydrogenation reduced the density of GB

states to ~9×1011 cm-2eV-1 in the range of Ev+0.56~0.61 eV, which is about a seven-fold

reduction from that of the clean sample.

Segregation and thermal dissociation kinetics of hydrogen at a large-angle general GB in crystalline silicon have been investigated using deuterium as a readily identifiable isotope which duplicates hydrogen chemistry. Segregation or trapping of deuterium (hydrogen) introduced was found to take place at (110)/(001) Si GB. The segregation coefficient (k) of deuterium (hydrogen) at GB was determined as k≈24±3 at 100°C. Thermal dissociation of deuterium (hydrogen) from GB obeyed first-order kinetics with an activation energy of ~1.62 eV.

(3)
(4)

Electrical Properties of Grain Boundaries and Dislocations in Crystalline Silicon: Influence of Impurity Incorporation and Hydrogenation

by Yongkook Park

A dissertation submitted to the Graduate Faculty of North Carolina State University

in partial fulfillment of the requirements for the degree of

Doctor of Philosophy

Materials Science and Engineering

Raleigh, North Carolina 2009

APPROVED BY:

_______________________________ ______________________________ Prof. George A. Rozgonyi Prof. Jerome J. Cuomo Chair of Advisory Committee

(5)

ii

DEDICATION

(6)

iii BIOGRAPHY

(7)

iv

ACKNOWLEDGEMENTS

First I would like to thank Prof. Rozgonyi for giving me the opportunity to study at NCSU and for his advice and encouragement. I am also indebted to my advisory committee, Prof. Cuomo, Prof. Aspnes, and Prof. Bedair. I thank them for being on my committee.

I would also like to acknowledge my collaborators on this research effort, both inside the USA and abroad. I am grateful to M. Seacrist of MEMC for providing many valuable samples for this study.

I am grateful to my colleagues at NCSU. Specifically, I want to thank Dr. Jinggang Lu for his valuable discussions on various topics regarding electrical characterization of defects in crystalline silicon. I would also like to acknowledge my friend Jinwoo Kim for many joyful moments.

(8)

v

TABLE OF CONTENTS

LIST OF TABLES... viii

LIST OF FIGURES... ix

INTRODUCTION... 1

THESIS OUTLINE... 4

CHAPTER 1. LITERATURE REVIEW... 6

1.1 Electrical activity of grain boundaries... 6

1.2 Electrical activity of dislocations... 7

1.3 Hybrid orientation direct-silicon-bonded (DSB) silicon wafers as a model of grain boundaries structure... 8

1.4 Strained-Si/SiGe/Si wafers as a model of dislocations structure... 10

1.5 Interface recombination-generation statistics... 11

1.5.1 Generalized rate relationships... 11

1.5.2 Steady-state relationship... 13

1.5.3 Interface recombination-generation... 14

1.5.3.1 Single level under steady-state relationship……… 15

1.5.3.2 Multi-level under steady-state relationship……….. 16

References……… 18

CHAPTER 2. RESEARCH METHODOLOGY……….... 21

2.1 Introduction... 21

2.2 Current-Voltage (I-V) characteristics... 22

2.2.1 Thermionic field emission of metal-semiconductor Schottky contacts.... 22

2.2.2 Current transport across the interface of bonded wafers... 23

2.3 Capacitance-Voltage (C-V) characteristics... 24

2.3.1 Reverse-biased junction capacitance (CJ)... 24

2.3.2 Capacitance-Voltage (C-V) measurements... 25

2.4 Capacitance transient………...……… 27

2.5 DLTS (Deep Level Transient Spectroscopy)………. 29

2.5.1 The DLTS system……….. 30

2.5.2 Methods for data analysis……….……. 31

2.5.2.1 Dual-channel boxcar averager……….. 31

2.5.2.2 Lock-in amplifier (LIA)……… 32

(9)

vi

CHAPTER 3. IMPACT OF IRON CONTAMINATION AND HYDROGENATION FOLLOWING IRON CONTAMINATION ON THE ELECTRICAL PROPERTIES

OF GRAIN BOUNDARYIES IN CRYSTALLINE SILICON………...………… 39

3.1 Introduction………. 39

3.2 Experimental……….……….…… 40

3.3 Results and Discussion……….. 41

3.3.1 Electrical characterization of silicon grain boundaries by C-V & J-V methods………...… 41

3.3.2 Electrical characterization of silicon grain boundaries by capacitance transient: impact of iron contamination and hydrogenation following iron contamination………. 50

3.4 Conclusion……….………. 60

References………. 61

CHAPTER 4. HYDROGEN PASSIVATION OF DEEP ENERGY LEVELS OF (110)/(001) CLEAN GRAIN BOUNDARY IN CRYSTALLINE SILICON…….…… 63

4.1 Introduction……….……… 63

4.2 Experimental……….…….. 64

4.3 Results and Discussion………....…..……….. 65

4.4 Conclusion………... 76

References………. 77

CHAPTER 5. SEGREGATION AND THERMAL DISSOCIATION OF HYDROGEN AT (110)/(001) SILICON GRAIN BOUNDARY……… 78

5.1 Introduction……….……… 78

5.2 Experimental……….………….. 79

5.3 Results and Discussion………..……….. 81

5.4 Conclusion………..………. 88

References………. 89

CHAPTER 6. INVESTIGATION OF THE RETENTION OF IRON IMPURITIES AT DISLOCATIONS IN CRYSTALLINE SILICON……….……… 90

6.1 Introduction………...………...…... 90

6.2 Experimental……….……….. 92

6.3 Results and Discussion………..………….. 93

6.3.1 Dislocations and associated defects in as-grown sample……… 93

6.3.2 Decoration of iron impurity at dislocations………..……….. 96

6.3.2.1 TEM analyses………….…....………...….... 96

6.3.2.2 DLTS analyses………...………... 97

6.3.2.3 Trapping of iron impurities at room temperature………….….. 101

(10)

vii

(11)

viii

LIST OF TABLES

Table 3.1 Trap level position ET from the valence band edge and

hole capture cross-section σp for a GB charge density 2.6×1011 cm-2.…..…. 58 Table 3.2 GB charge neutral level (φ0) and electron capture cross-section (σn)

for a GB charge density 2.6×1011 cm-2.………. 59 Table 6.1 Fe–B pair concentrations in the 900°C, 1 min. annealed

(12)

ix

LIST OF FIGURES

Chapter 1

Fig. 1. Illustration of the wafer bonding and layer transfer process... 9 Fig. 2. TEM cross-section image of a (110)/(001) bonded (or 90° tilt) wafer showing the

general large angle grain boundary... 9 Fig. 3. Cross-sectional TEM image acquired near the <110> zone axis of the as-grown SiGe/Si heterostructure... 10 Fig. 4. Possible electronic transitions between a single-level R-G center and the energy bands……… 12

Chapter 2

Fig. 1. Energy band diagram under A: forward bias and B: reverse bias (Ref. [1]). (qVA is the applied bias, qΦb and qVi are the potential barrier in the metal and

in the semiconductor, respectively.)……… 22 Fig. 2. Band diagram of the interface between two bonded p-type silicon wafers with the applied bias voltage. (qVA is the applied bias, qVL is the electric potential

energy barrier on the left side of the interface, qVR is the energy barrier

on the right side of the interface, and ξ = EF - EV.)……….……… 24

Fig. 3. (a) Parallel equivalent circuit, and (b) series equivalent circuit of a device under test (DUT) for the measurement using capacitance meters……… 26 Fig. 4. Schematic circuit diagram of a capacitance-conductance meter (Ref. [4])……. 27 Fig. 5. A Schottky diode for (a) zero bias, (b) reverse bias at t=0, and

(c) reverse bias as t∞. The applied voltage and resultant capacitance transient are shown in (d)………...……….. 28 Fig. 6. Block diagram of the DLTS system, employing either a lock-in amplifier or

a dual-channel boxcar averager (Ref. [8])………... 30 Fig. 7. Illustration of how a double boxcar is used to define the rate window.

The left-hand side shows capacitance transients at various temperatures, while the right-hand side shows the corresponding DLTS signal resulting from using the double boxcar to display the difference between the capacitance at time

1

t and the capacitance at time t2 as a function of temperature (Ref. [5])…… 32 Fig. 8. Phase setting for the “bias-pulse phase reference” mode: (a) filling pulse of

width tp and frequency f =1 T/ 0; (b) normalized exponential capacitance transient before (broken curve) and after gate-off (solid curve); (c) lock-in amplifier weighting function set in phase with the falling edge of the filling

(13)

x Chapter 3

Fig. 1. (a) C-V curves of three samples after different treatments.….……… 42 Fig. 1. (b) The GB charge density per unit charge (NGB) obtained from the measured

capacitance data (1MHz)………. 43 Fig. 1. (c) The band bending for different reverse biases calculated from the 1 MHz

capacitance data………... 44 Fig. 1. (d) J-V curve at 300K………... 45 Fig. 2. Equilibrium (EF), intrinsic (Ei), electron quasi- (FN), and hole quasi- (FP) Fermi

levels at GB at (a) zero bias and (b) above 3 V reverse bias. GB states are divided into five groups according to their position relative to the two quasi-

Fermi levels………. 47 Fig. 3. (a) Hole emission rate (J/q) vs. NGB at 270~320 K at 10 K increment.

(b) Arrhenius plots of hole emission rates for traps at different positions in the bandgap, labeled by the corresponding GB charge density per unit charge…… 49 Fig. 4. Dependence of NGB and hole capture cross-section on the trap-level position… 49

Fig. 5. Illustration of the three processes contributing to the decay of non-equilibrium holes at GB during the capacitance transient………... 51 Fig. 6. Hole decay rate (dNGB/dt) vs. hole density (NGB) obtained from I-V/C-V method

and capacitance transient technique from 280 to 300 K……….. 51 Fig. 7. (a) Capacitance transient of a clean sample with VR = 2 V and VP = 18 V.

(b) The corresponding band-bending profile before and during the transient... 53 Fig. 8. Hole emission (or decay) rates calculated from the experimental capacitance transient data of the (a) clean sample, (b) Fe contaminated sample, and (c) hydrogenated sample following Fe contamination from 230 K to 270 K. In order to show all the decay rates in one plot with a linear scale, the decay rates at 230 K, 240 K, 250 K, and 260 K were multiplied by a factor of 60, 19, 7,

and 2.5, respectively………... 56 Fig. 9. Arrhenius plots of hole emission rates at NGB = 2.6×1011 cm-2 for the clean,

Fe contaminated, and Fe + H samples……… 58 Chapter 4

Fig. 1. Energy band diagram of gold/DSB junctions (a) at zero bias and

(b) at reverse bias, V……… 66 Fig. 2. (a) C-V and (b) J-V characteristic before and after hydrogenation……….. 70 Fig. 3. Comparison of the GB charge density as a function of trap energy level

for clean and hydrogenated GB………... 72 Fig. 4. Capacitance transient measured in thermal equilibrium and corresponding

charge decay of the GB after filling GB states using a pulse voltage 20V

for a brief period……….. 74 Fig. 5. Charge decay rate versus GB charge density at different temperatures

(14)

xi Chapter 5

Fig. 1. TEM cross-section image of a (110)/(001) bonded (or 90° tilt) wafer showing the large-angle general grain boundary………... 81 Fig. 2. (a) Secondary ion mass spectroscopy depth profile of D introduced in bonded Si wafers and Cz-Si wafers by boiling the sample in heavy water. No D was detected by SIMS for as-received (110)/(001) DSB Si wafers. The broken line

indicates the (110)/(001) Si interface. A and d represent the integration of the D concentration profile on the right side of GB and the distance between the position of the interface and the tail of the profile intersecting the bulk D concentration of 1016 cm-3, which was about 60 nm………... 83 Fig. 2. (b) C-V depth profile of electrically active B in the bulk of Czochralski-grown Si wafers before and after D treatment. D introduced in the bulk was evaluated by quantifying the amount of the neutralized B content………. 83 Fig. 3. SIMS depth profile showing the dissociation of D from grain boundary at 800°C as a function of annealing time……… 86 Fig. 4. Arrhenius plot of the measured dissociation frequencies of the trapped D at

grain boundary. The solid line is a linear fit of lnv=lnv0+(−EA/KT) yielding EA = ~1.62 eV. The inset shows the exponential decay of D at GB at several

annealing temperatures. The annealing times at 600°C are adjusted by a factor

α

=9 to accommodate for the large time differences. The broken line

represents the least-squares fit of D(t,T)=D0exp(−νt)to the data for obtaining the decay time constant or dissociation frequency……….. 87

Chapter 6

Fig. 1. Cross-sectional TEM image acquired near the <110> zone axis of the as-grown SiGe/Si heterostructure……….... 93 Fig. 2. (a) DLTS spectra of as-grown and annealed samples under same reverse and pulse capacitances. (b) C-V curves of the as-grown and annealed samples…… 94 Fig. 3. Cross-sectional TEM images acquired along the <110> zone axis of the 900°C, 30 min. Fe-contaminated (100) SiGe/Si heterostructure. (a) bright-field

diffraction contrast image and (b) Z-contrast STEM image………..…….. 96 Fig. 4. (a) DLTS spectra of the 900°C, 30 min. iron contaminated sample.

(b) Arrhenius plot of the DLTS trap at 210 K………. 98 Fig. 5. DLTS spectra of the 900 °C, 1 min. iron contaminated sample acquired

after 4 and 48 hrs. of room temperature storage after quenching. (a) VR=8 V and

Vp=4 V, (b) VR =4 V and Vp =2 V, (c) VR=2 V and Vp=1 V. Fei and

Fe-dislocation represent interstitial iron and Fe decoration/precipitation

at dislocations, respectively……… 102 Fig. 6. DLTS spectra of the sample after 900°C annealing for 1 min., iron

(15)

1

INTRODUCTION

World solar photovoltaic (PV) market installations reached a record high of 5.95 gigawatts (GW) in 2008, representing growth of 110% over the previous year [1]. Due to its relatively low cost, multi-crystalline silicon (mc-Si) solar cells [2] are occupying a large portion of Si cell production. The use of lower-quality Si feedstock leads to the incorporation of metal impurities into the Si melt [3-6]. The molten Si is slowly cooled down during solidification. Hence, introduced impurities are diffused and precipitated at GBs or dislocations in mc-Si [7-11]. The carrier recombination activity of metallic impurity decorated defects is enhanced compared to that of clean defects, thereby degrading the minority carrier recombination lifetime of the mc-Si substrate [12-21]. Phosphorous diffusion gettering (PDG) and hydrogenation are applied to the as-grown mc-Si substrate for lifetime enhancement [22,23]. Average carrier lifetime of processed wafers is increased, but high defect density regions in wafers still exhibit a low lifetime. Based on these backgrounds, the following research objectives are suggested.

1. Characterize how impurity contamination and hydrogenation following impurity contamination affect each component (DGB, σn, σp, and qVGB) of GB recombination activity,

where DGB is the density of GB states, σn and σp are the electron and hole capture

cross-sections, respectively, and qVGB is the GB electric potential energy barrier. Although the

(16)

2

behavior of each electrical parameter composed of GB recombination activity has not been fully understood.

2. Determine the effectiveness of hydrogen passivation of clean GB and thermal stability of H at GB. Whether H can passivate GBs or not has been confirmed mainly by EBIC method. Here, we approached H passivation of clean GB via the investigation of the density of GB states before and after hydrogenation, which will help to clarify the mechanism of H passivation of extended crystal defects. Besides the electrical properties, thermal stability of H at GB was studied as well.

3. Characterize the retention of metal impurities at dislocations after high-temperature thermal annealing. It has been reported that gettering of metal impurities is not effective in highly defective regions in mc-Si. The gettering process involves three steps [24]; the first step is the release of metallic impurities from defects, the second step is the diffusion of dissociated impurities to the gettering regions, and the third step is the capture of impurities at the gettering sites. The important question is: which is the rate-limiting step in gettering? If the impurities are not released, gettering will not take place at all. Hence, we focused on the issue of the retention of metal impurities at dislocations at high temperatures.

(17)

3

(18)

4

THESIS OUTLINE

The thesis is organized as following:

Chapter 1 of “Literature Review” discussed the electrical activities of GBs and dislocations in crystalline Si. A model of defects structure employed in this study, namely, hybrid orientation bonded Si wafers and strained-Si/SiGe/Si wafers were reviewed. The electrical properties of GBs were introduced.

Chapter 2 of “Research Methodology” briefly described the experimental techniques employed in this study.

Chapter 3 of “Impact of Iron Contamination and Hydrogenation Following Iron Contamination on the Electrical Properties of Grain Boundaries in Crystalline Silicon” described first how the electrical parameters of GB can be extracted by the electrical characterization methods such as C-V, I-V and capacitance transient using the clean sample. Afterwards, the influence of iron contamination and hydrogen treatment after iron contamination on the electrical properties of GB was investigated and compared with the obtained data of the clean sample by employing capacitance transient technique.

Chapter 4 of “Hydrogen Passivation of Deep Energy Levels of (110)/(001) Clean Grain Boundary in Crystalline Silicon” approached hydrogen passivation of silicon GB by examining the density of GB states before and after hydrogenation. The characterization of the density of GB states was performed via the concept of current transport across GB.

(19)

5

Grain Boundary” focused on the chemical characterization of deuterium (hydrogen) at GB. The segregation coefficient and thermal dissociation kinetics of hydrogen at a large-angle general GB in crystalline Si have been explored using deuterium as a readily identifiable isotope which duplicates hydrogen chemistry.

(20)

6 CHAPTER 1. LITERATURE REVIEW

1.1 Electrical activity of grain boundaries

The electrical activity of GBs can arise either from intrinsic structural disorder or from extrinsic impurity decoration, with the recombination activity of GBs noticeably increasing after metal decoration [25]. The deep gap states in silicon GBs are usually attributed to either dangling bonds (i.e., three-fold coordinated Si atoms) or to segregated impurities [26]. It has been reported that in the symmetric segment of the structure of GBs in silicon, a 5-fold coordinated atom was present, which elevated the structure energy of the boundary and produced a new state in the band gap. The defect states were originated in the localized electrons around the 5-fold-coordiated atoms [27].

It has been suggested that the recombination activity of clean GBs is weak and the GB character has no significant effect on it. The recombination activity of GBs becomes stronger as the impurity contamination level is increased. The variation in the recombination activity related to the GB character is also observed after contamination. The random or high ΣGBs shows the stronger EBIC contrast than the low ΣGBs [28]. The recombination activity of angle GBs has been investigated by EBIC study as well. The EBIC contrast of small-angle GBs is weak at 300 K. Deliberate impurity contamination enhances the recombination activity and the small-angle GBs shows the stronger EBIC contrast than the special and random GBs and acted as strong recombination centers at 300 K [29].

(21)

7

GBs in mc-Si has been studied by means of EBIC technique [30]. For GBs in the low contamination mc-Si, the effect of hydrogen passivation depends on GB character, namely the random and small-angle GBs are comparatively more difficult to be passivated than the special GBs. For GBs in the heavy contamination mc-Si, the effect of hydrogen passivation was less significant and was not affected by the GB character.

1.2 Electrical activity of dislocations

(22)

8

1.3 Hybrid orientation direct-silicon-bonded (DSB) silicon wafers as a model of grain boundaries structure

2-D near-surface grain boundaries can be created by direct silicon wafer bonding of wafers with different orientations and degrees of lattice tilt and twist. These samples will have a controlled defect density with known Burgers vectors, dictated by the DSB twist and tilt angles, located at a predetermined depth from the surface. Oxygen impurities inherent at the bonded interface can be left in place or readily removed by a high temperature annealing process to obtain clean dislocations. With an increase in the twist/tilting angles, the density of the square network of screw dislocations also increases, and eventually a general large angle grain boundary is obtained. This unique set of samples will provide a systematic progression of 1- and 2-D dislocation and grain boundary impurity and hydrogenation passivation interactions, allowing their similarities and differences to be conveniently examined and optimized for potential solar cell applications.

Figure 1 shows the wafer bonding and layer transfer process: (a) a pre-defined cleavage plane introduced into the donor wafer by light ion implantation, (b) hydrophilic bonding of the donor wafer to a handle (100) wafer, (c) layer transfer by cleavage and followed by a high temperature annealing to remove interfacial oxygen, (d) epi-thicken the transferred layer if necessary. An (100) donor wafer will be used to obtain a dislocation network, while an (110)

(23)

9

θ induced by the miscut of each wafer. With the increase of the twist/tilt angles, the density of the interfacial dislocations will increase, and eventually a large angle general grain boundary can be obtained. Figure 2 is a cross-sectional TEM image of a (110)/(001) DSB wafer, which is equivalent to a bonding with 90° tilt angle around one <011> direction.

(100) (100) or (110)

(100) (100) or (110)

(100) (100)

(a) Introducing cleavage plane

(b) hydrophobic bonding

(c) cleavage and remove oxygen

(d) epi-thicken ψ

θ

(b) hydrophilic

by high-T annealing

(100) (100) or (110)

(100) (100) or (110)

(100) (100)

(a) Introducing cleavage plane

(b) hydrophobic bonding

(c) cleavage and remove oxygen

(d) epi-thicken ψ

θ

(b) hydrophilic

(100) (100) or (110)

(100) (100) or (110)

(100) (100)

(a) Introducing cleavage plane

(b) hydrophobic bonding

(c) cleavage and remove oxygen

(d) epi-thicken ψ

θ

(b) hydrophilic

by high-T annealing

Fig. 1. Illustration of the wafer bonding and layer transfer process.

(24)

10

1.4 Strained-Si/SiGe/Si wafers as a model of dislocations structure

High mobility strained-Si grown on relaxed SiGe virtual substrates have been shown to enhance the performance of Si complementary metal-oxide semiconductor devices [36,37]. To accommodate the lattice parameter increase with increasing Ge content, misfit dislocations are generated in the SiGe graded layer, some of which terminate at the surface with two threading dislocations arms. The primary function of the relaxed SiGe layer is to serve as a “virtual substrate” for tensile-straining the top Si epilayer. In order to produce a relaxed SiGe epilayer with low threading dislocation densities on a Si substrate, the conventional method is to grow thick (a few µm) compositionally-graded buffer layers and a following layer of uniform SiGe. Mismatch strain is gradually relaxed by a modified Frank– Reed (MFR) mechanism [38,39], and the majority of 60° misfit dislocations (MDs) formed during the relaxation process are trapped within the SiGe graded layer as shown in Fig. 3. MDs generated in/near the SiGe graded layer were a model of dislocations structure in this study.

(25)

11 1.5 Interface recombination-generation statistics 1.5.1 Generalized rate relationships

Consider the possible R-G center to energy band transitions shown in Fig. 4. The possible transitions, four in all, are (a) electron capture at an R-G center, (b) electron emission from an R-G center, (c) hole capture at an R-G center, and (d) hole emission from an R-G center. The

net electron and hole recombination rates, rN and rP, are positive if recombination is

dominant and negative if generation is dominant.

T p T p G R P T n T n G R N p e p n c t p r n e n p c t n r − = ∂ ∂ − = − = ∂ ∂ − = − − (1)

Principle of detailed balance: Under equilibrium conditions each fundamental process and its

inverse must self-balance independent of any other process that may be occurring inside the material.    = = 0 0 P N r r

under equilibrium conditions

(26)

12

E

electron

hole

E

T

(trap)

E

C

E

V

(a)

(b)

(c)

(d)

T n n p c ⋅ ⋅

T p p n c ⋅ ⋅

T n n eT p p e

E

electron hole

E

T

(trap)

E

C

E

V

E

T

(trap)

E

C

E

V

(a)

(b)

(c)

(d)

T n n p c ⋅ ⋅

T p p n c ⋅ ⋅

T n n eT p p e

Fig. 4. Possible electronic transitions between a single-level R-G center and the energy bands.

1 0 0 0 0 0

0 c n

n n p c e n T T n

n = =

and 1 0 0 0 0 0

0 c p

p p n c e p T T p

p = =

where        = = 0 0 0 1 0 0 0 1 T T T T p p n p n n p n computable constants

It is next assumed that the emission and capture coefficients all remain approximately equal to their equilibrium values under non-equilibrium conditions, i.e.,

   ≈ = ≈ ≈ = ≈ 1 1 0 0 1 1 0 0 p c p c e e n c n c e e p p p p n n n n (2)

(27)

13

(

)

(

1

)

1 p p p n c t p r n n n p c t n r T T p G R P T T n G R N − = ∂ ∂ − = − = ∂ ∂ − = − − (3)

1.5.2 Steady-state relationship

     ∂ ∂ − = ∂ ∂ − ≠ = −

G R G

R P N t p t n r r 0

under steady-state conditions

The equal creation or annihilation of holes and electrons under steady-state conditions in turn fixes nT for a given n and p. Specifically, equating the right-hand sides of Eq. (3),

remembering pT =NTnT , and solving for nT, one obtains

) (

)

( 1 1

1 p p c n n c p N c n N c n p n T p T n

T + + +

+

= (steady-state) (4)

The Eq. (4) nT expression can be used to eliminate nT (and pT) in Eq. (3). After a bit off

manipulation which makes use of the fact that n1p1 =ni2, we arrive at the result

) ( ) ( 1 1 1 2 p p N c n n N c n np r r R T n T p i P N + + + − = =

= (5)

where the symbol R has been introduced to identify the net recombination rate. Finally,

T nN c /

1 and 1/cpNT have units of time (seconds) and it is therefore reasonable to

(28)

14 T

n n

N c

1

=

τ …the electron minority carrier lifetime and

T p p

N c

1

=

τ

…the hole minority carrier lifetime

which when substituted into Eq. (5) yields

) (

)

( 1 1

2

p p n

n

n np R

n p

i + +

+ − =

τ

τ

1.5.3 Interface recombination-generation

(29)

15

(1) Because interface states are arranged along a plane in space rather than spread out over a volume, the net recombination rates are logically expressed in terms of carriers removed from a given band per UNIT AREA per second (electrons or holes/cm2/sec).

(2) Whereas a single level usually dominates bulk recombination-generation, the interface-center interaction routinely involves centers distributed in energy throughout the band gap. Hence, it is necessary to add up or integrate the single-level interface rates over the energy band gap. To begin the analysis we assume the band gap contains a single energy level, EIT. Adding the subscript s to the previous corresponding bulk results, the expressions

for the interface are obtained.

1.5.3.1 Single level under steady-state relationship Under steady-state conditions, as in the bulk,

s Ps Ns r R r = =

if the filled-state population of interfacial traps at EIT is assumed to change exclusively via

thermal band-to-trap interactions.

) (

)

( 1 1

1 s s ps s s ns s Ts ps s Ts ns Ts p p c n n c p N c n N c n + + + +

= (steady-state) (6)

Likewise as in the bulk above,

) ( 1 ) ( 1 1 1 2 s s Ts ns s s Ts ps i s s s p p N c n n N c n p n R + + + −

(30)

16

Note that 1/cnsNTs and 1/cpsNTs are NOT time constants. In fact, cnsNTs =sn and

p Ts psN s

c = have units of a velocity, cm/sec, and are the (single level) interface

recombination velocities for electrons and holes.

1.5.3.2 Multi-level under steady-state relationship

As already noted, interface centers are typically found to be continuously distributed in energy throughout the band gap. The net recombination rates associated with the individual centers in the distribution must be added together to obtain the overall net recombination rate. A simple addition is possible assuming that the centers at different energies are non-interacting. Let DIT(E) be the density of interfacial traps (traps per cm2 per eV) at an

arbitrarily chosen energy E

(

EvEEc

)

. DIT(E)dE will then be the number of

interfacial traps per cm2 with energies between E and E+dE. Associating DIT(E)dE with NTS in the single-level relationship [NTSDIT(E)dE] in Eq. (7) and recognizing that these states provide an incremental contribution (dRs) to the overall net recombination rate

when there is a distribution of states, one deduces

dE E D c p p c

n n

n p n

dR IT

ns s s ps s s

i s s

s ( )

/ ) (

/ )

( 1 1

2

+ + +

= (8)

(31)

17 Integrating over all band gap energies then yields

+ ++

= c v E

E s s ps s s ns IT

i s s

s D E dE

c p p c

n n

n p n

R ( )

/ ) (

/ )

( 1 1

2

(9)

In utilizing the above relationship it must be remembered that all of the trap parameters can vary with energy. The anticipated variation of DIT(E) with energies is of course noted explicitly. n1s and p1s are exponential functions of energy. Like DIT(E), cns(E) and

) (E

(32)

18

REFERENCES

1. “Marketbuzz 2009: Annual World Solar PV Market Report”, http://www.solarbuzz.com. 2. H. J. Möller, C. Funke, M. Rinio, and S. Scholz, Thin Solid Films 487, 179 (2005). 3. J. R. Davis, Jr., A. Rohatgi, R. H. Hopkins, P. D. Blais, P. Rai-Choudhury, J. R. Mccormick, and H. C. Mollenkopf, IEEE Trans. Electron Devices ED-27, 677 (1980). 4. D. Macdonald, A. Cuevas, A. Kinomura, Y. Nakano, and L. J. Geerligs, J. Appl. Phys. 97, 033523 (2005).

5. A. A. Istratov, T. Buonassisi, R. J. Mcdonald, A. R. Smith, R. Schindler, J. A. Rand, J. P. Kalejs, and E. R. Weber, J. Appl. Phys. 94, 6552 (2003).

6. E. R. Weber, Appl. Phys. A 30, 1 (1983).

7. T. Buonassisi, A. A. Istratov, M. A. Marcus, M. Heuer, M. D. Pickett, B. Lai, Z. Cai, S. M. Heald, and E. R. Weber, Solid State Phenomena 108-109, 577 (2005).

8. T. Buonassisi, A. A. Istratov, M. D. Pickett, M. A. Marcus, T. F. Ciszek, and E. R. Weber, Appl. Phys. Lett. 89, 042102 (2006).

9. H. Hieslmair, A. A. Istratov, T. Heiser, and E. R. Weber, J. Appl. Phys. 84, 713 (1998).

10. A. A. Istratov, H. Hedemann, M. Seibt, O. F. Vyvenko, W. Schröter, T. Heiser, C. Flink, H. Hieslmair, and E. R. Weber, J. Electrochem. Soc. 145, 3889 (1998).

(33)

19

12. Z. J. Radzimski, T. Q. Zhou, A. B. Buczkowski, and G. A. Rozgonyi, Appl. Phys. A 53, 189 (1991).

13. M. Kittler and C. Ulhaq-Bouillet, Mater. Sci. Eng. B24, 52 (1994).

14. M. Kittler, C. Ulhaq-Bouillet, and V. Higgs, Mater. Sci. Forum 196-201, 383 (1995). 15. M. Kittler, W. Seifert, M. Stemmer, and J. Palm, J. Appl. Phys. 77, 3725 (1995). 16. M. Kittler, C. Ulhaq-Bouillet, and V. Higgs, J. Appl. Phys. 78, 4573 (1995). 17. V. Kveder, M. Kittler, and W. Schröter, Phys. Rev. B 63, 115208 (2001).

18. V. Kveder, W. Schröter, M. Seibt and A. Sattler, Solid State Phenom. 82-84, 361 (2002).

19. K. Knobloch, M. Kittler, and W. Seifert, J. Appl. Phys. 93, 1069 (2003). 20. M. Kittler, W. Seifert, and K. Knobloch, Microelectronic Eng. 66, 281 (2003). 21. O. F. Vyvenko, M. Kittler, W. Seifert, and M. V. Trushin, Phys. Stat. Sol. (c) 2, 1852 (2005).

22. S. M. Myers, M. Seibt, and W. Schröter, J. Appl. Phys. 88, 3795 (2000).

23. W. Schröter, A. Döller, A. Zozime, V. Kveder, M. Seibt, and E. Spiecker, Solid State Phenom. 95-96, 527 (2004).

24. H. R. Huff, Solid-State Technol. 26, 211 (1983).

25. J. Chen, D. Yang, Z. Xi, and T. Sekiguchi, J. Appl. Phys. 97, 033701 (2005). 26. F. Cleri, P. Keblinski, L. Colombo, S. R. Phillpot, and D. Wolf, Phys. Rev. B 57,

6247 (1998).

(34)

20

28. J. Chen, T. Sekiguchi, D. Yang, F. Yin, K. Kido and S. Tsurekawa, J. Appl. Phys. 96, 5490 (2004).

29. J. Chen, T. Sekiguchi, R. Xie, P. Ahmet, T. Chikyo, D. Yang, S. Ito, and F. Yin, Scripta Materialia 52, 1211 (2005).

30. J. Chen, D. Yang, Z. Xi, and T. Sekiguchi, Physica B 364, 162 (2005). 31. V. Kveder, M. Kittler, and W. Schröter, Phys. Rev. B 63, 115208 (2003). 32. M. Kittler, C. Ulhaq-Bouillet, and V. Higgs, J. Appl. Phys. 78, 4573 (1995). 33. O. V. Feklisova, E. B. Yakimov, and N. Yarykin, Phys. B 340–342, 1005 (2003). 34. O. V. Feklisova, E. B. Yakimov, N. Yarykin, and B. Pichaud, J. Phys.: Condens.

Matter 16, S201 (2004).

35. H. Alexander and H. Teichler, Dislocations in: Handbook of Semiconductor Technology, edited by K. A. Jackson and W. Schröter (Wiley-VCH, New York, 2000), Vol. 1, p. 291.

36. K. Rim, J. L. Hoyt, and J. F. Gibbons, IEEE Trans. Electron Devices 47, 1406 (2000).

37. K. Ismail, B. S. Meyerson, and P. J. Wang, Appl. Phys. Lett. 58, 2117 (1991).

38. E. A. Fitzgerald, Y. H. Xie, D. Monroe, P. J. Silverman, J. M. Kuo, A. R. Kortan, F. A. Thiel, and B. E. Weir, J. Vac. Sci. Technol. B 10, 1807 (1992).

(35)

21 CHAPTER 2. RESEARCH METHODOLOGY

2.1 Introduction

(36)

22 2.2 Current-Voltage (I-V) characteristics

2.2.1 Thermionic field emission of metal-semiconductor Schottky contacts

Electrons overcome the potential barrier between the metal and the semiconductor through a quantum-mechanical process called “thermionic emission”. This process is activated by the thermal energy of the electrons. When the bias voltage (VA) is applied to the

device, the potential barrier that the electrons have to overcome to transit from the semiconductor into the metal is equal to ΦbVA (VA > 0 for the forward bias, VA < 0 for

the reverse bias), see Fig. 1. The resulting thermionic emission current density is given by

   

=

KT V

Φ

q T

R

Jm s * 2exp ( b A) (1)

where R* is called the Richardson constant and is equal to

3 0 * 2

) / ( 4 *

h m m qK

R = π n .

Fig. 1. Energy band diagram under A: forward bias and B: reverse bias (Ref. [1]). (qVA is the

applied bias, qΦb and qVi are the potential barrier in the metal and in the semiconductor,

(37)

23

2.2.2 Current transport across the interface of bonded wafers

We start with the assumption that the only important mechanism for current flow across the interface is thermionic emission. Tunneling directly into the trap states at the interface is specifically neglected as well as generation-recombination currents [2]. It has been shown that the majority carrier transport across GB can be described by the simple double-depletion-layer/thermionic field emission model [3]. The total current density (J) across the interface is the current density from the left to the right (JLR) in Fig. 2, reduced by the

current density in the opposite direction (JRL).

            + −       + = − = KT qV KT qV T R J J

J L R R L * 2 exp ξ L exp ξ R

            − −       + = KT qV KT qV T

R* 2exp ξ L 1 exp ,

) ( ) / ( 120 ) / ( 4

* * 0 2 2

3 0 * 2 K Acm m m h m m qK

R = π p = p − (2)

where R* is the Richardson constant, K is the Boltzmann constant, h is the Planck’s constant,

*

p

m is the hole effective mass, and m0 = 9.11×10-31 kg is the free electron rest mass.

The potential barrier qVL depending on the applied bias can be calculated from the measured

current density using Eq. (2) as follow.

(38)

24 2.3 Capacitance-Voltage (C-V) characteristics 2.3.1 Reverse-biased junction capacitance (CJ)

The depletion region width in the p-type semiconductor (xp) changes with the applied

bias (VA). If in addition to the dc bias, a small-signal sine wave of ac bias is

EC

EV qVA

qVR qVL

ξ ξξ ξ EF

J

LR

J

RL

EC

EV qVA

qVR qVL

ξ ξξ ξ EF

J

LR

J

RL

Fig. 2. Band diagram of the interface between two bonded p-type silicon wafers with the applied bias voltage. (qVA is the applied bias, qVL is the electric potential energy barrier on

the left side of the interface, qVR is the energy barrier on the right side of the interface, and ξ

= EF - EV.)

applied to the Schottky diode,

υ

a =Vmsin

ω

t , the total applied junction voltage is

a A A V υ

υ = + . The charge increment at the depletion region edge must change to

(39)

25

) (

2 0

0 0

A bi SCR

s s s

J

V V qN

K

A K W

A K C

− =

=

ε

ε

ε

(Farad) (4)

where A is the cross-sectional area (cm2) and NSCR is the ionized impurity density in the

space-charge region.

2.3.2 Capacitance-Voltage (C-V) measurements

Capacitance can be defined as the change in the charge amount, dQ, due to a change in the voltage, dV:

dV dQ

C= (5)

This method is known as differential or small signal capacitance. Most capacitance measurements are made with capacitance meters or capacitance bridges, by superimposing a small-amplitude ac voltage v on the dc voltage V, as a change of voltage. Capacitance meters assume the device under test (DUT) to be represented by either the parallel equivalent circuit in Fig. 3(a) or the series equivalent circuit in Fig. 3(b).

For the DUT represented by a parallel equivalent circuit (see Fig. 4), an ac signal vi is

applied to the DUT and the device impedance Z is calculated from the ratio of vi to the

sample current ii. In the vector voltage-current method, the ac voltage typically varies at

frequencies of 10 KHz to 1MHz with amplitude of 10 to 20 mV. Since the high input impedance of a high-gain operational amplifier allows no current through (ii io), the

(40)

26

Fig. 3. (a) Parallel equivalent circuit, and (b) series equivalent circuit of a device under test (DUT) for the measurement using capacitance meters.

Since ii= vi/Z, the device impedance can be derived from voand vias

.

o i F

v v R

Z =− (6)

For the parallel equivalent circuit in Fig. 4, the device impedance of the is given by

2 2

2

2 ( ) G ( c)

C j

c G

G Z

ω

ω

ω

− +

+

= (7)

where C is the equivalent parallel capacitance, G is the equivalent parallel conductance, and the testing angular frequency ω= 2πf. The device impedance consists of a conductance and a susceptance, respectively. Furthermore, the voltages vo and viare fed to a phase detector and

the conductance and susceptance of the sample are obtained by using the 0º and 90º phase angles of vo referenced to vi. The 0º phase angle gives the conductance G while the 90º phase

(41)

27

Fig. 4. Schematic circuit diagram of a capacitance-conductance meter (Ref. [4]).

2.4 Capacitance transient

When the diode is pulsed from zero to reverse bias as shown in Fig. 5 with most R-G centers initially occupied by holes, holes are emitted from the R-G centers for t > 0. Emission dominates over capture during this reverse-bias phase because the emitted holes are swept out of the reverse-biased space-charge region (SCR) very quickly, thereby reducing the chance of being recaptured. The hole sweep-out time is tW /

υ

p. For

υ

p ≈107 cm/sec at

room temperature and W consisting of a few microns, t is a few tens of picoseconds. This time is significantly shorter than typical capture times. Following hole emission from traps, electrons remain and are subsequently emitted followed by hole emission, and so on. The steady-state electron-filled trap density (nT) in the reverse-biased SCR is

1

≈ + =

p n

p

T T

e e

e

N n

(42)

28 (a)

EC

EV Ei

ET(deep level)

EF

ET(shallow level) p-type Si

Al

Depletion width (W)

ET

EC

EV Ei

ET

W EC

EV Ei ET ET filled empty W (b) (c) V t t=0 VR 0 (a)

(b) (c) (Steady-state)

C t t=0 C (V=0) 0 (d) (a) EC EV Ei

ET(deep level)

EF

ET(shallow level) p-type Si

Al

Depletion width (W) EC

EV Ei

ET(deep level)

EF

ET(shallow level) p-type Si

Al

EC

EV Ei

ET(deep level)

EF

ET(shallow level) p-type Si

Al

EC

EV Ei

ET(deep level)

EF

ET(shallow level)

EC

EV Ei

ET(deep level)

EF

ET(shallow level) p-type Si

Al

Depletion width (W) Depletion width (W)

ET EC EV Ei ET W ET EC EV Ei ET ET EC EV Ei ET W

W EC

EV Ei ET ET filled empty

W EC

EV Ei ET ET EC EV Ei ET ET filled empty W W (b) (c) V t t=0 VR 0 V t t=0 VR 0 (a)

(b) (c) (Steady-state)

C t t=0 C (V=0) 0 (a)

(b) (c) (Steady-state)

C t t=0 C (V=0) 0 (d)

Fig. 5. A Schottky diode for (a) zero bias, (b) reverse bias at t=0, and (c) reverse bias as t∞. The applied voltage and resultant capacitance transient are shown in (d).

Figure 5(b) and 5(c) show the space-charge region width W to change when holes are emitted from traps. In transient measurements, it is this time-varying W that is detected as a time-varying capacitance. From Eq. (4), we find

− + − + − − = − − = A T A T A bi A s J N t p C N t p V V N qK A

C 1 ( ) 1 ( )

) ( 2 0 0

ε

(9)

where C0 is the capacitance of a device with no deep-level impurities at reverse bias, +

= A T

SCR N p

N for deep-level donors occupied by holes.The time-dependent capacitance reflects the time dependence of nT(t) or pT(t). The capacitance increases with time for

(43)

29

are donors or acceptors. The resulting junction capacitance can then be expressed by an exponential time-varyingfunction as

) exp( ) 0 ( exp

) 0 ( )

(t C t C tep

C = −

     − =

τ (10)

where τ is the emission time constant and is equal to the inverse of the emission coefficient (ep), and C(0) is the capacitance at t = 0. The capacitance transient can be used to extract the

number of trap states, the position of the energy level and the carrier capture cross-section.

2.5 DLTS (Deep Level Transient Spectroscopy)

(44)

30 2.5.1 The DLTS system

The DLTS system is shown in the block diagram of Fig. 6. A Boonton 72B capacitance meter is used to measure the transient capacitance, and either the dual-channel boxcar averager or the lock-in amplifier is used for setting the rate window. It is necessary to gate off the first 1-2 msec of the capacitance signal because of the 1 msec response time of the capacitance meter and the consequent overloading problems which occur when a bias pulse is applied. By using the gating-off-period control circuit and the sample-and-hold circuit, we can gate off the signal for a chosen period and thus avoid baseline restoration problems. Two calibrated platinum thermal sensors next to the diode in the sample holder and a temperature controller are used for accurate temperature control.

(45)

31 2.5.2 Methods for data analysis

2.5.2.1 Dual-channel boxcar averager

A series of capacitance transients for a typical trap at various temperatures is shown schematically on the left-hand side of Fig. 7. According to the carrier emission time Eq.,

) / exp( )

( hNV th −1 ET KT =

σ

υ

τ

(11)

the emission rate is very small for low temperatures and becomes more rapid as temperature is increased. These transient signals are fed into a double boxcar with gates set at t1 and t2 as shown in Fig. 7. The signal from the differential output of the boxcar is applied to the y-axis of an X-Y recorder. This is simply C(t1)−C(t2). It is clear from Fig. 7 that this quantity,

) ( ) (t1 C t2

C − goes through a maximum when the emission time constant (τ) is on the order of t2t1.

τ

maxis the value of

τ

at the maximum of C(t1)−C(t2) versus T for a

particular trap. The relationship between

τ

maxand t1 and t2 is simply determined by the following formula [5].

) / ln(2 1

1 2 max

t t

t t

=

(46)

32

Fig. 7. Illustration of how a double boxcar is used to define the rate window. The left-hand side shows capacitance transients at various temperatures, while the right-hand side shows the corresponding DLTS signal resulting from using the double boxcar to display the difference between the capacitance at time t1 and the capacitance at time t2 as a function of temperature (Ref. [5]).

2.5.2.2 Lock-in amplifier (LIA)

The signal response, tuning procedure, and calculation of trap concentrations from peak heights of the LIA output have been discussed previously for the ideal case in which the filling pulse width tp and the system response time (also referred to as delay time) td

(47)

33

max

τ at a DLTS peak and the LIA frequency f was determined as

τ

max =0.42f ,

independent of the gate-off time. The shortcomings of this analysis were pointed out by Day et al. [8] who presented a more detailed analysis in which the system response time t was d taken into consideration when calculating the LIA output, phase settings, and decay time constants.

The LIA response Sexp to this partially exponential waveform, is the integral of the

product of the LIA square-wave weighting function in Fig. 8(c) and the first Fourier component of the waveform. This output is proportional to ∆C by a factor that can be

calculated through a detailed mathematical and numerical analysis as follows:

To calculate the first Fourier component of the waveform in Fig. 8(b), the input signal to the LIA is written as

( )

       < ≤ −       − −       − < ≤ −       + −       − = 2 2 exp exp 2 2 2 / exp exp 0 0 0 0 0 0 T t t T for t T t t T t T for T t t t f g g d g d

τ

τ

τ

τ

(13)

The Fourier expansion of this function over the interval

(

T0/2≤t<T0/2

)

is

( )

∞ =             +       + =

1 0 0

0 cos 2 sin 2

2 n n n T

nt b T nt a a t

(48)

34

In Eq. (14), an and bn are the Fourier coefficients given by

( )

dt

T nt t f T a T T n             =

− 0 2 / 2 / 0 2 cos 2 0 0

π

(15)

( )

dt

T nt t f T b T T n             =

− 0 2 / 2 / 0 2 sin 2 0 0

π

(16)

For the signal in Fig. 8(b), defined by Eq. (13), the first Fourier coefficients are obtained from Eq. (15) and (16) with n=1

×               +       − −       = −1 2 0 2 0 0 1 2 exp

2

τ

τ

π

τ

T t T T a p               − −             −       τ π πτ

π g g T tg

T t T T t 0 0 0 0 exp 2 sin 2 2

cos (17)

×               +       − − = −

2 1

0 2 1 0 1 2 exp τ π τ

π T t T

b p               −               −       +             − τ π πτ π πτ g g

g T t

T t T T t T 0 0 2 0 0

0 1 cos 2 exp

2 2

sin 2

(49)

35

The first Fourier component of the signal analyzed by the LIA is thus

( )

      +       = 0 1 0 1 1 2 sin 2 cos T t b T t a t

f π π (19)

with a1 and b1 given by Eqs. (17) and (18). The LIA response to the incoming signal is

obtained from

( ) ( )

t wt dt f

S T

T

= /2

2 / 1 exp 0 0 (20)

where w(t) is the LIA weighting function shown in Fig. 8(c). By taking into account the boundary conditions for the different sections of the waveform in Fig. 8(b), the LIA output becomes

( )( )

t dt f

( )( )

t dt f

( )( )

t dt

f S T t T t T t t T d d d d 1 1

1 /2

2 / 1 2 / 1 2 / 1 exp 0 0 0 0 + + − + +

=

(21)

Equations (19) and (21) result in

            +             = 0 1 0 1 0 exp 2 cos 2 sin 2 T t b T t a T

S πd πd

π (22)

with a1 and b1 given by Eqs. (17) and (18). In order to obtain the maximum value of the

decay time constant τmax, the condition for a maximum of the DLTS peak is used

0 /

exp dτ =

dS (23)

(50)

36 The conversion of the LIA output to ∆C is as follow.

R output sq

scale

R C

LIA S

S V

C C

C

× × =

exp max

(24)

where Cscale is the scale setting on the capacitance meter during DLTS measurements, Vmax is

the maximum voltage output from the capacitance meter at that setting, and CR is the reverse

bias capacitance. The LIA response due to its own weighting function Ssq is

( )

0

2 /

2 /

2

2 1

0

0

T dt t w

S T

T

(51)

37

(52)

38

REFERENCES

1. S. M. Sze, Physics of Semiconductor Devices, Wiley, New York (1969), pp. 145–156. 2. R. K. Mueller, J. Appl. Phys. 32, 635 (1961).

3. G. E. Pike and C. H. Seager, J. Appl. Phys. 50, 3414, (1979).

4. D. K. Schroder, Semiconductor Material and Device Characterization (John Wiley & Sons, New York, 1998).

5. D. V. Lang, J. Appl. Phys. 45, 3023 (1974).

6. G. L. Miller, J. V. Ramirez, and D. A. H. Robinson, J. Appl. Phys. 46, 2638 (1975). 7. L. C. Kimerling, IEEE Trans. Nucl. Sci. NS-23, 1497 (1976).

8. D. S. Day, M. Y. Tsai, B. G. Streetman, and D. V. Lang, J. Appl. Phys. 50, 5093 (1979).

9. J. T. Schott, H. M. DeAngelis, and W. R. White, Airforce Cambridge Laboratories Report No. AFCRL-TR-76-0024, (1976).

(53)

39

CHAPTER 3. IMPACT OF IRON CONTAMINATION AND HYDROGENATION FOLLOWING IRON CONTAMINATION ON THE ELECTRICAL PROPERTIES OF GRAIN BOUNDARYIES IN CRYSTALLINE SILICON

3.1 Introduction

The electrical behavior of GBs in crystalline silicon is of great technological importance to multi-crystalline silicon solar cells, polycrystalline silicon thin-film transistor (TFT), and micro/nano-crystalline silicon thin-film solar cells [1]. GBs in crystalline silicon can act as minority carrier recombination sites, which degrade solar cell efficiency. The potential barrier and the charges at GBs also reduce the collection of minority carriers. The carrier generation, recombination, and transportation processes are controlled by the GB trap levels in the silicon bandgap. For instance, majority carrier transport across a GB can be modeled as a thermionic emission process over the GB barrier, which is controlled by the charge neutral level (trap filling position before charge transfer from the grains) and the GB density of states [2,3]. The minority carrier recombination/generation properties of GBs are also mediated by the electron (σn) and hole (σp) capture cross-sections of individual gap states [4]. The

(54)

40

contaminated regions, the impact of hydrogenation was less significant and was not affected by GB character [7].

In this chapter, we report the influence of Fe contamination and hydrogenation following Fe contamination on the electrical properties of (110)/(001) silicon GB, namely, how impurity contamination and hydrogenation following impurity contamination affect each component (DGB, σn, σp, and qVGB) of GB recombination activity was characterized.

3.2 Experimental

The samples consisted initially of a 200 nm thick, p-type (110) Si layer on a p-type (100) Si substrate produced by hydrophilic wafer bonding and subsequent cleavage along the defective plane introduced by hydrogen implantation [8-10]. The oxygen at the bonded interface was removed by a high temperature annealing process. The (110) top layer was epitaxially thickened to 2.3 µm for the electrical characterization. C-V shows that the substrate and the top layer doping are 1.05×1015 and 0.95×1015 cm-3, respectively. Cross-sectional HR-TEM reveals no interfacial oxide precipitates, and depth profiling by Secondary Ion Mass Spectroscopy also did not detect any oxygen at the bonding interface.

(55)

41

order to dissociate the H-B pairs. All samples were cleaned with diluted HF at room temperature and in a Piranha solution (1 part sulfuric acid and 1 part peroxide) at 80°C, before preparing Al Schottky diodes by thermal evaporation. Ohmic contacts were made by rubbing an eutectic Ga-In alloy on the back surface. C-V and capacitance transients were measured on a BioRad DL8000 DLTS system at 1 MHz frequency at temperatures from 230 K to 270 K.

3.3 Results and Discussion

3.3.1 Electrical characterization of silicon grain boundaries by C-V & J-V methods Figure 1(a) plots the C-V curves of the clean sample, the Fe contaminated sample, and the hydrogenated sample after Fe contamination. The sum of the Al Schottky depletion depth and the GB depletion width at zero bias can be obtained from the 1 MHz capacitance. For the clean sample, it was (εSiA /) CR= 2.05 µm, where εSi is the dielectric constant of Si and A is the diode area. The depletion depth of the Al/Si junction can be obtained from the 10 KHz capacitance. That was (εSiA /) CR= 1.02 µm for the clean sample. Thus, the total depletion width of the GB at zero bias is determined as 1.03 µm for the clean sample that gives a band bending (or the GB electric potential energy barrier at zero bias) of 0.21 eV and a Fermi level at 0.47 eV above the valance band.

Figure

Fig. 3. Cross-sectional TEM image acquired near the <110> zone axis of the as-grown SiGe/Si heterostructure
Fig. 4. Possible electronic transitions between a single-level R-G center and the energy bands
Fig. 1. Energy band diagram under A: forward bias and B: reverse bias (Ref. [1]). (applied bias, qVA is the qΦ  and bqVi are the potential barrier in the metal and in the semiconductor, respectively.)
Fig. 2. Band diagram of the interface between two bonded p-type silicon wafers with the = applied bias voltage
+7

References

Related documents

These variables and parameters include the profiles of snow temperature, density, grain size, stickiness, and liquid water content, the characteristics of the substratum (e.g.

Throughput, delay, jitter and packet loss performances of various e-learning applications have been analyzed over WiLD networks1. The simulation results suggest that the

Einkristalle für die Röntenstrukturanalyse wurden durch Diffussion von Pentan in eine Lösung dieses Pulvers in CH 2 Cl 2 erhalten; im Kristall befindet sich je ein Molekül CH 2

Theoretical Stark profiles of the H-β line calculated for hydrogen atoms in a helium plasma 137.. with an electron density of 10 16 cm -3 and a temperature of 0.1 eV for both

using neural networks and optimization techniques. Journal of the Franklin Institute. Multilayer perceptrons and radial basis function neural network methods for the solution

Measuring and Predicting Orthographic Associations Modelling the Similarity of Japanese Kanji Proceedings of the 22nd International Conference on Computational Linguistics (Coling

Construction of an English Dependency Corpus incorporating Compound Function Words Akihiko Kato, Hiroyuki Shindo, Yuji Matsumoto Nara Institute Science of Technology 8916 5 Takayama,