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Novel Power on Reset Design for Full-Proof Enablement of Threshold Supply in SoCs

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459,ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013)

423

Novel Power on Reset Design for Full-Proof Enablement of

Threshold Supply in SoCs

Karabi Kalita

1

, Sudha Nair

2

1M.Tech Student, RKDF Institute of Science & Technology, Bhopal, M.P., INDIA.

2Sudha Nair, Asst. Prof., Deptt. of Electronics & Comm. Engg., RKDF Institute of Science & Technology Bhopal, M.P.,INDIA Abstract— A Novel on-chip Power On Reset (POR) circuit

with long reset duration & low leakage current for System on Chip (SoC) applications is presented in this paper. This prototype design is simulated in a 0.18-μm CMOS process which provides a reset signal with duration of hundreds of milliseconds. Three cascaded current mirrors are used to scale down the current in nano-ampere range to achieve sufficient time for all the blocks on SoC to attain state of stable operation. The circuit is capable of detecting brown-out events in the range of milliseconds. The chip consumes less than half of a micro ampere current under a 1.8-V supply.

KeywordsBrown out detection, Brown out reset, Cascaded Current Mirror, Power on detection, Power on reset, Schmitt trigger.

I. INTRODUCTION

Electronics systems typically employ a number of integrated circuits operating from a common voltage power supply and each such integrated circuit chip itself is typically made up of various logical and functional circuit modules that operate together to provide desired functionality. When such a system is initially turned on, a supply voltage can reach from a null up to its full voltage value over a period of time which can vary from less than a microsecond to over a hundred milliseconds. Due to this delay in the supply voltage ramp the state of a system at start-up is an important consideration in designing integrated circuits based electronic systems as the system may initially operate in an unpredictable fashion because components like flip-flops are not designed to power-on in any particular state. Therefore it is usually desirable to provide an input signal at start-up to reset synchronous circuitry as in many applications, upon power on, an integrated chip requires initialization for the of the proper operation of the circuits.

Fig1: Power on reset (POR) circuit

Fig2: Brown out Reset (BOR) circuit

Fig3: Circuit diagram for Power on Reset (POR) and Brown out Reset (BOR)

The initialization is performed by a command signal known as power on reset (POR), once the power supply voltage has ramped up to a voltage exceeding a pre-defined threshold value referred to as the assertion voltage. In particular, the POR circuit provides a reliable reset state on power-up. Such functionality prevents the malfunctioning of the chip due to being initialized in an unknown state.

A.Power on Reset Circuit

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013)

424

Depending on the specific RC values involved, the voltage across the capacitor can increase exponentially, which in turn provides the delay.

Figure 1 presents an advanced power-on reset circuit. The diode is used to rapidly discharge the capacitor C on power-down. This is very important as a power-up reset pulse is needed after a short power-down (less than the time constant of RC) or after a power spike. The two capacitors C1 &C2 allow the reset pin level to follow voltage variations that appear on either Vdd or ground.

B.Brown Out Reset Circuit

Due to excessive supply noise or heavy current drawn by the load the supply voltage can abruptly drop below the minimum value of VDD and the circuits at this voltage can give garbage values. This phenomenon is known as a brown-out event. So a reset signal is provided to the circuit for certain interval of time so that instead of giving garbage value it returns to the initial state. In many applications, it is necessary to guarantee a reset pulse whenever Vdd is less than Vdd (min). This can be achieved using a brown-out protection circuit described in Figure 2. This simple circuit causes a reset whenever Vdd drops below the zener diode voltage plus the VBE.

Fig3 shows the timing diagram of Power on Reset (POR) and Brown out Reset (BOR) event. The terms described in the figure are as follows, Vdd (max) is the steady state value of the supply voltage Vlow is the lowest value of supply voltage below which the circuit cannot operate correctly, Vdd (min) is the minimum supply voltage at which reset switch turns on and Tint is the time duration for which the supply voltage remains at Vlow. If the supply voltage falls below this level a brown out reset signal is generated and resets the circuit. Tpor is the power on reset time and Tbor is the brown out reset time.

In this paper we present a unique Power on Reset circuit with long duration and Brown out detection capability. It consumes current less than half of a micro-ampere range i.e. leakage current decreases and hence power dissipation decreases. Moreover the circuit consumes approximately less active area because resistance is not used in the circuit.

II. PROPOSED CIRCUIT DESCRIPTION

The fig-4 shows the proposed circuit for POR circuit with long reset time and brown out detection function. The proposed Power On Reset circuit consists of five functional blocks namely a bias circuit, cascaded current mirror, circuit for providing delay, Brown out detector circuit and Schmitt trigger circuit.

A. Bias circuit

Bias circuit consists of three diode connected transistors M1 to M3 and is used to reduce the overdrive voltage of M4. Overdrive voltage, usually abbreviated as VOV, defined as the voltage between transistor gate and source (Vgs) in excess of the threshold voltage (Vth) where Vth is defined as the minimum voltage required between gate and source to turn the transistor on (allow it to conduct electricity). Due to this definition, overdrive voltage is also known as excess gate voltage or effective voltage. Overdrive voltage can be found by using the simple equation

Vov = Vgs - Vth

B. Cascaded Current Mirror

These current mirrors are used to scale down the reference current I1 by a factor of 1000.

C.Delay Circuit

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013)

425

Fig4: Proposed POR Circuit with long duration & BOR detection function

D.Brown out detection circuit

The brown out detection circuit composed of the transistor circuit M11, M12, M13, M14and the capacitor M01

E.Schmitt trigger

The output Va from the current mirror is applied as input to the Schmitt trigger. The Schmitt trigger generates a reset pulse at its output

.

III. OPERATING PRINCIPLE

When power is switched on, Vdd supply voltage gradually increases and the transistor ie. current generator (M1–M4) remains off until the supply voltage reaches the turn-on voltage of the current generator. The turn on voltage of current generator is given by the equation V turn-on = Vgs1 + Vgs2 +Vgs3+Vgs4

When Va exceeds the high switching point of the Schmitt trigger VSPH, the resetsignal switches back to low and finishes the reset phase. The complete circuit connected to this reset signal then starts to operate at normal operation. The duration of the reset signal depends on current through M1, the size capacitance of M0, and the value of VSPH.

Due to sudden failure of power supply sometimes the supply voltage level falls below a certain level Vlow and is not sufficient for all the circuits to work properly, so a reset pulse should be generated to prevent circuit malfunction. A Brown out detection circuit is added in order to provide the reset signal. The two diode connected transistor M13 and M14 provides the gate bias voltage for the transistorM12.

The gate voltage forM12 can be expressed as Vg=Vdd-Vgs13-Vgs14

Thus Va, the drain voltage of current source M9, remains low. During this transition period, the output of the Schmitt trigger Reset continues to rise following the supply voltage and turns on the reset switches connected to it when it reaches minimum value of Vdd. When the supply voltage exceeds Vturn_on, the current generator and cascaded mirrors turn on and M9 starts to charge M0 with a sub nano-ampere order current, and thus, Vastarts to rise.

The capacitor M01is used to hold that gate voltage. When the supply voltage goes below Vlow the source voltage of pMOS transistor M12 decreases turning off the transistor which pulls Vctrl node down to ground level. As a consequence pMOS transistor M10 turns on and voltage (Va) across the capacitor M0 is discharged through this transistor. When voltage Va decreases below the lower switching point of Schmitt trigger VSPL, it turns on and generates a reset pulse.

V

low

voltage is given as

V

low

= V

gg

+V

th12

The upper and lower switching point of Schmitt trigger are set at 1.45V and 0.8V respectively. Vdd & V th are at 1.8V & 0.6V respectively. The equations for calculating (W/L) ratio for the transistors used in the design of Schmitt trigger are:

= = )2

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013)

426

= =( 2

In the proposed circuit design, static currents I1, I2, I3 are reduced to decrease power consumption. The values of currents are found to be I1=140.25nAmp, I2=13.93 nAmp, I3=1.7nAmp I4=0.175nAmp. So, all currents are in nano-ampere range.

The current through M11is expressed as I3=ΔV. Cp/Δt

Here, ΔV is the required dropout voltage of Vctrl from Vdd to turn M4 on, CP is the parasitic capacitance at the

gate of M10, and Δt is the minimum time that the supply voltage stays below Vlow from the moment the brown-out event is detected.

The current flowing through transistor M10 is Id= - µp cox ( ) (Vgs10 - Vth) 2

= - β10 (Va - Vth) 2

Vth is the threshold voltage of transistor M10 and capacitor Mo is discharged by Id

Id=C

Where C is the equivalent capacitance of M0. The minimum time of Tint, i.e., Tint_min, for M0 to discharge its voltage Va from Vdd(max) to VSPL and to change the output of the Schmitt trigger can be calculated as

Tint-min= = .dVa

Hence, the interval of a brown-out event Tint should be larger than Tint_min so that the brown-out circuit can detect the situation and generate a reset signal. The value of

Tint_min can be designed with the size of M10, equivalent capacitance of M0, and the high-to-low switching point of the Schmitt trigger VSPL.

IV. SIMULATION RESULTS

The waveforms show the power on reset event with reset time of 255ms and a brown out event of 5ms is present at time 0.6s which again activates the reset signal and provides a brown-out reset pulse of 165 ms duration, the duration can be increased by increasing the discharge current through M10. The average power consumed by the POR circuit during the simulation cycle of 1s is 1.807e-4 watts. The maximum power recorded was 9.093e-004 at the time of charging of the capacitor M0.

Average static power consumed by the circuit in duration of 100ms is 1.87 e-6 watts Max power 2.235457e-006 at time 0.4.

The simulated results are shown in the fig5.

Fig5: Simulated transient response during power on and brown out event

The plot in Fig6 shows the variation of the POR and brown-out reset time with temperature. The plots have been plotted for the range 273 to 473K at the difference of 25K each. At Vdd rise time of 100ms we found the longest reset time 285ms at 273K and shortest 122ms at 473K.

Fig6: Variation of POR and BOR with temperature

V. CONCLUSION

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013)

427

The circuit requires less area as compared to [7] because the resistance has been removed and it is ideal for SoC’s and large chips where long reset time is required and power is a crucial factor.

REFERENCES

[1] S. Mitra, “Power-up considerations,” Application Notes.

[2] T. Yasuda, M. Yamamoto, and T. Nishi, “A power-on reset pulse generator for low voltage applications,” in Proc. IEEE Int. Symp. Circuits Syst., May 2001, vol. 4, pp. 599–601.

[3] S. K.Wadhwa, G. K. Siddhartha, and A. Gaurav, “Zero steady state current power on reset circuit with Brown-out detector,” in Proc. 19th Int. Conf.VLSID, 2006, pp. 631–636.

[4] Katyal A ST Microelectronics, a Jolla, CA Bansal “A self biased current source based on power on reset circuit for on chip applications” in VLSI design, Automation and Test, 2006 international symposium.

[5] S. U. Ay, “A nanowatt cascadable delay element for compact power-on reset (POR) circuits,” in Proc. 52nd IEEE Int. Midwest Symp. Circuits Syst., 2009, pp. 62–65.

[6] Burd Lazar,A Lazar,L.C”Power on reset circuit for SoC with multiple I/O power supplies “Circuits and Systems(ISSCS),2011,10th

international Symposium.

[7] Huy-Binh Le, Xuan-Dien Do, Sang-Gug Lee, and Seung-Tak Ryu “A Long Reset-Time Power-On Reset Circuit with Brown-Out Detection capability” in IEEEE TRANS A IEEE Transaction on Circuits and Systems refess brief “RESS BRIEFS, VOL. 58, NO. 11, NOVEMBER 2011

References

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