Comparision and Implementation of Cryptography Algorithm By Using VHDL

International Journal of Emerging Technology and Advanced Engineering

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Comparision and Implementation of Cryptography Algorithm

By Using VHDL

Priya Jain

,

Dr. Rita Jain

,

Tarun Verma

Abstract - This paper presents the comparison and

optimization of Galois field algorithm and

IDEA(International data encrypted algorithm) using

VHDL(xc2v40-6cs144)with the help of Xilinx-Ise (9.2) .In terms of security IDEA algorithm is very much superior where as in terms of timings Galois field is much better and is already patented of Ascom. These are cryptographic algorithm used for security purpose.

The Galois field property of multiplication is XORing based process along with the use of irreducible polynomial selected by National Institute of Standard Technology that retains the multiplication result to the same number of bits as that of the multiplier & multiplicand bit. The encrypted result can thus be used for secure data transmission and is hatched at the decoder end using the FPGA lookup table which uses the symmetric key.

We have investigated different encoded result using encoding algorithm. Simulation result of Galois field algorithm shows that using Galois multiplication property a 4 x 4 bit multiplication yields an output of 4 bit result .Thus it reduces the number of bits in results and encodes the data too. This can be implemented in cryptographic applications where as in IDEA Algorithm the whole algorithm is divided into modules and among all of them the most time consuming one is the modulo multiplication module .The IDEA algorithm that is used computes the product in a recursive fashion and it uses divide and conquer approach during multiplication which ultimately consumes less time and increases the through put in the algorithm. The block size considered here is the same as of traditional IDEA encryption algorithm. In IDEA for synthesis we have used Xylinx 9.2i and for simulation we have used modelsim 10.2.

Keywords - Encryption, Cryptographic Algorithm, IDEA, Galois Field, VHDL.

I. INTRODUCTION

Cryptography is the study of Secret (crypto-)-Writing (-graphy). It is the science or art of encompassing the principles and methods of transforming an intelligible. Message into one that is intelligible and then transforming the message back to its original form.

As the field of cryptography has advanced; cryptography today is assumed as the study of techniques and applications of securing the integrity and authenticity of transfer of information under difficult circumstances. In the field of networking, role of network Prevention/Detection is immense.[1][10] It is a very vital tool which provides the security against various external and internal threats in any network. To maintain network intrusion detection in a network involves the fulfillment of the security goals in the network which are Data Confidentiality, Integrity, Authentication and Non-Repudiation. Cryptology is the science concerned with providing secure communications.[1][2] The goal of cryptology is to construct schemes which allow only authorized access to information. All malicious attempts to access information is prevented. An authorized access is identified by a cryptographic key. A user having the right key will be able to access the hidden information, while all other users will not have access to the information. Cryptology consists of cryptography and cryptanalysis. The former involves the study and application of various techniques through which information may be rendered unintelligible to all but the intended receiver[10]

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II. IDEA ENCRYPTION ALGORITHM

This section must contain specific details about the materials studied, instruments used, specialized tools, source and research experimental details, algorithms, and application which allows other research work to reproduce the result. In this paper the cipher used in IDEA is a symmetric block cipher[3][4]. The size of the key is fixed to be 128 bits and the size of the data block which can be handled in one encryption/decryption process is fixed to 64 bits. All data operations in the IDEA cipher are in 16-bit unsigned integers. When processing data which is not an integer multiple of 64-bit block, padding is required. The security of IDEA algorithm is based on the mixing of three different kinds of algebraic operations: EX-OR, addition and modular multiplication. IDEA is based upon a basic function, which is iterated eight times. The first iteration operates on the input 64-bit plain text block and the successive iterations operate on the 64-bit block from the previous iteration. After the last iteration, a final transform step produces the 64-bit cipher block.[10]

P1 P2 P3 P4

ROUND 1

SEVEN MORE

SIMILAR ROUND

OUTPUT

TRANSFORMATION

PROCESS

OUTPUT CIPHER TEXT (64 bits)

16 Bit INTEGER ADDITION MODULO 216

BITWISE XOR

Figure 1 International Data Encryption Algorithm (IDEA)

The algorithm structure has been chosen such that, with the exception that different key sub-blocks are used, the encryption process is identical to the decryption process. IDEA uses both confusion and diffusion to encrypt the data. Three algebraic groups, EX-OR, addition modulo 216, and multiplication modulo (216 + 1), are mixed, and they are all easily implemented in both hardware and software. All these operations operate on 16-bit sub-blocks.[4][5]

III. GALOIS FIELD ALGORITHM

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No

Figure2 Algorithm for GF (2m_{) Multiplication}

IV. EXPERIMENTAL RESULT &DISCUSSION

Figure 4.1 Simulation result of Galios Field

 Algorithm used based on Galois field property of multiplication

 N X N bit multiplication yields N bit Result

 National Institute of Standards & Technology (NIST) based irreducible polynomial secret key.

 Here in Galois Field for simulation we used Model sim PE Student Ediion 10.1c.Here the reset is forced to 0,done is forced to 1 and multiplier is forced to 1000,multiplicand to 1000,then the cipher text obtained is 1100.which is equivalent to 256.

In simulation results of IDEA the first four are the input results and the next four are the output results

Figure 4.2 Simulation result of IDEA(Encoder)

START

Result =0 Loop=3

Result = Result XOR (Ai AND B)

Left shift Result (append with 0)

Loop=Loop -1

Loop=0?

MS bit=1?

Multiplication Done

STOP Subtr

act Polyn omial

Cipher text is 1100 Input(Multipli er1000

Multiplicand (1000)

201A

5DFE

DA01

ABCD 221E

6002

DC05

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V. TABLE

Comparision of different parameters between IDEA and Galois Field Algorithm.

Table 1

Synthesis result of IDEA & Galois Field

S no Parameters IDEA Galois

1 No of Slices 28 out of 256 35 out of 256

2 Number of 4

input LUTs

56 out of 512 56 out of 512

3 No of bonded

IOBs 128 128

4 Maximum

Combi national path delay

7.296ns 4.575ns

VI. RESULT

 We observed that GALOIS FIELD MULTIPLICATION property can be used to design encoder & decoder.

 Similarly we have observed that 4 BIT MULTIPLICATION results 4 bit of encrypted data.  The Decrease in Hardware is required in Galois Field.  The number of step calculating Galois Field

Algorithm taken by device Spartan 2v40cs144-6 is: 6 steps.

 Galois Save more time and area a and cost is low  IDEA Algorithm can also be used to design encoder

and decoder.

 The hardware is increased

 The time taken by the IDEA algorithm as per simulation is 7.296ns where as in Galios Field Algorithm time taken is 3.33 ns

VII. CONCLUSION

In the results we see that the time taken by IDEA Algorithm is 7.29ns where as in Galois Field Algorithm time taken is 4.575 ns which is lesser than IDEA .So we can say that due to the increased no of rounds and complexity the time taken by the Galois Field Algorithm is less as compared to IDEA Algorithm. But for the security purpose the IDEA Algorithm is more secure.

REFERENCES

[1] Jana Görs, Graham Horton, Nadine Kempe‖ A Collaborative

Algorithm for Computer-Supported Idea Selection in the Front End of Innovation2012 45th Hawaii International Conference on System Sciences

[2] N. Kempe, R. Buchholz, J. Goers, G. Horton, "AnOptimal

Algorithm for Raw Idea Selection underUncertainty", Accepted to the Hawaii InternationalConference on System Sciences, Maui, HI, January2012.

[3] Pravinkumartiwari1 ,Momd.abdullah2, Rajesh nema3, ―A Hardware

implementation of IDEA cryptosystem using a recursive multiplication approach.‖, International Journal of Advanced Research in Computer Engineering & TechnologyVolume 1, Issue 4, June 2012.

[4] Sourav Mukherjee and Bibhudatta Sahoo, ―A Hardware

implementation of IDEA cryptosystem using a recursive multiplication approach.‖, International Conference on Electronic Systems (ICES-2011), pp 383 - 389, 2011,

[5] Antti H¨am¨al¨ainen, Matti Tommiska, and Jorma Skytt¨, ―6.78

Gigabits per Second Implementation of the IDEA Cryptographic Algorithm‖, 2002 Springer-Verlag, pages 760-769.

[6] Chiranth E, Chakravarthy H.V.A, Naga mohanareddy P,Umesh

T.H, Chethan Kumar M., ―Implementation of RSACryptosystem Using Verilog‖ International Journal ofScientific & Engineering Research Volume 2, Issue 5,May-2011.

221E

201A 6002

DC05

201A

5DFE

DA01

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[7] Rajashekhar Modugu, Yong-Bin Kim and Minsu Choi, ―A Fast

Low-Power Modulo 2n + 1 Multiplier‖, Journal of IET Computers & Digital Techniques Jan-2011.

[8] Dr.Ravi Shankar Mishra, Prof Puran Gour, Mohd AbdullahDesign &

Implementation of 8 Bit Galois Encoder for on FPGA Secure Data TransmissionInternational Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 1, Issue 3, pp.820-823

[9] Thomas Conway, ―Galois Field Arithmetic Over GF For High-Speed

―IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 4, APRIL 2004.

[10] P. Kitsos*, G. Theodoridis, O. Koufopavlou,―An efficient

reconfigurable multiplier architecture for Galois field GF(2m)‖, Microelectronics Journal 34 (2003) 975–980

[11] A Book on Cryptography and Network Security by Atul Kahate.Tata

McGraw-Hill Education, 07-Sep-2008.

[12] Ahmed O. El-Rayis, Xin Zhao, Tughrul Arslan, Ahmet T. Erdogan

―Dynamically Programmable Reed Solomon Processor with Embedded Galois Field‖ , 978-1-4244-2796-3/08/$25.00 © 2008 IEEE

AUTHORS PROFILE

1 Dr Rita Jain is award Ph.D from MANIT., & currently working as Head., Electronics & Comm. Dept in LNCT Bhopal. MP(INDIA).

2 Prof Tarun Verma is recieved M.Tech from R.G.P.V. & currently working as an Asst. Prof in Electronics & Comm. Dept , LNCT Bhopal. MP(INDIA).

3