Design for Test by Alfred L Crouch

(1)

Figures to Accompany

Design-for-Test

for Digital IC’s and

Embedded Core Systems

Alfred L. Crouch

(2)

Contents ii

Chapter 1 Test and Design-for-Test Fundamentals

Figure 1-1

Cost of Product

Figure 1-2

Concurrent Test Engineering

Figure 1-3

Why Test?

Figure 1-4

Definition of Testing

Figure 1-5

Measurement Criteria

Figure 1-6

Fault Modeling

Figure 1-7

Types of Testing

Figure 1-8

Manufacturing Test Load Board

Figure 1-9

Using ATE

Figure 1-10

Pin Timing

Figure 1-11

Test Program Components

Chapter 2 Automatic Test Pattern Generation Fundamentals

Figure 2-1

The Overall Pattern Generation Process

Figure 2-2

Why ATPG?

Figure 2-3

The ATPG Process

Figure 2-4

Combinational Stuck-At Fault

Figure 2-5

The Delay Fault

Figure 2-6

The Current Fault

Figure 2-7

Stuck-At Fault Effective Circuit

Figure 2-8

Fault Masking

Figure 2-9

Fault Equivalence Example

Figure 2-10

Stuck-At Fault ATPG

Figure 2-11

Transition Delay Fault ATPG

Figure 2-12

Path Delay Fault ATPG

Figure 2-13

Current Fault ATPG

Figure 2-14

Two-Time-Frame ATPG

Figure 2-15

Fault Simulation example

Figure 2-16

Vector Compression and Compaction

Figure 2-17

Some Example Design Rules for ATPG Support

Figure 2-18

ATPG Measurables

Chapter 3

Scan Architectures and Techniques

(3)

Contents iii

Figure 3-3

Scan Effective Circuit

Figure 3-4

Flip-Flop versus Scan Flip-Flop

Figure 3-5

Example Set-Scan Flip-Flops

Figure 3-6

An Example Scan Circuit with a Scan Chain

Figure 3-7

Scan Element Operations

Figure 3-8

Example Scan Test Sequencing

Figure 3-9

Example Scan Testing Timing

Figure 3-10

Safe Scan Shifting

Figure 3-11

Safe Scan Vectors

Figure 3-12

Partial Scan

Figure 3-13

Multiple Scan Chains

Figure 3-14

The Borrowed Scan Interface

Figure 3-15

Clocking and Scan

Figure 3-16

Scan-Based Design Rules

Figure 3-17

DC Scan Insertion

Figure 3-18

Stuck-At Scan Diagnostics

Figure 3-19

At-Speed Scan Goals

Figure 3-20

At-Speed Scan Testing

Figure 3-21

At-Speed Scan Architecture

Figure 3-22

At-Speed Scan Interface

Figure 3-23

Multiple Scan and Timing Domains

Figure 3-24

Clock Skew and Scan Insertion

Figure 3-25

Scan Insertion for At-Speed Scan

Figure 3-26

Critical Paths for At-Speed Testing

Figure 3-27

Logic BIST

Figure 3-28

Scan Test Fundamentals Summary

Chapter 4 Memory Test Architectures and Techniques

Figure 4-1

Introduction to Memory Testing

Figure 4-2

Memory Types

Figure 4-3

Simple Memory Organization

Figure 4-4

Memory Design Concerns

Figure 4-5

Memory Integration Concerns

Figure 4-6

Embedded Memory Test Methods

Figure 4-7

Simple Memory Model

(4)

Contents iv

Figure 4-9

Array Bridging Faults

Figure 4-10

Decode Faults

Figure 4-11

Data Retention Faults

Figure 4-12

Memory Bit Mapping

Figure 4-13

Algorithmic Test Generation

Figure 4-14

Scan Boundaries

Figure 4-15

Memory Modeling

Figure 4-16

Black Box Boundaries

Figure 4-17

Memory Transparency

Figure 4-18

The Fake Word Technique

Figure 4-19

Memory Test Needs

Figure 4-20

Memory BIST Requirements

Figure 4-21

An Example Memory BIST

Figure 4-22

MBIST Integration Issues

Figure 4-23

MBIST Default Values

Figure 4-24

Banked Operation

Figure 4-25

LFSR-Based Memory BIST

Figure 4-26

Shift-Based Memory BIST

Figure 4-27

ROM BIST

Figure 4-28

Memory Test Summary

Chapter 5 Embedded Core Test Fundamentals

Figure 5-1

Introduction to Embedded Core Test and Test Integration

Figure 5-2

What is a CORE?

Figure 5-3

Chip Designed with Core

Figure 5-4

Reuse Core Deliverables

Figure 5-5

Core DFT Issues

Figure 5-6

Core Development DFT Considerations

Figure 5-7

DFT Core Interface Considerations

Figure 5-8

DFT Core Interface Concerns

Figure 5-9

DFT Core Interface Considerations

Figure 5-10

Registered Isolation Test Wrapper

Figure 5-11

Slice Isolation Test Wrapper

Figure 5-12

Slice Isolation Test Wrapper Cell

(5)

Contents v

Figure 5-15

Other Core Interface Signal Concerns

Figure 5-16

DFT Core Interface Frequency Considerations

Figure 5-17

A Reuse Embedded Core’s DFT Features

Figure 5-18

Core Test Economics

Figure 5-19

Chip with Core Test Architecture

Figure 5-20

Isolated Scan-Based Core-Testing

Figure 5-21

Scan Testing the Non-Core Logic

Figure 5-22

Scan Testing the Non-Core Logic

Figure 5-23

Memory Testing the Device

Figure 5-24

DFT Integration Architecture

Figure 5-25

Test Program Components

Figure 5-26

Selecting or Receiving a Core

Figure 5-27

Embedded Core DFT Summary

(6)

Chapter 1 Test and Design-for-Test Fundamentals 1

Chapter 1 Test and Design-for-Test Fundamentals

Figure 1-1 Cost of Product

Silicon

Cost

Packaging

Cost

Testing

Cost

Initial

Product

Final

Increasing

Time

The goal over time is to reduce the cost of manufacturing

the product by reducing the per-part recurring costs:

- reduction of silicon cost by increasing volume and yield,

and by die size reduction (process shrinks or more

- reduction of packaging cost by increasing volume,

shifting to lower cost packages if possible (e.g., from

- reduction in cost of test by:

- reducing the vector data size

- reducing the tester sequencing complexity

- reducing the cost of the tester

- reducing test time

- simplifying the test program

ceramic to plastic), or reduction in package pin count

efficient layout)

Total

Cost

(7)

Figure 1-2 Concurrent Test Engineering

Gate-Level Library Mapping

Behavioral Specification and Model

Test Control

Test Interface

BIST HDL

Hardware Description Language

Register Transfer Level

Timing Constraints

Test Architecture

Development

Functional Architecture

Development

Scan Insertion

Gate-Level Synthesis

Insert

Scan Cells

Scan Signals

Gate-Level Netlist

Static Timing Assessment

Physical Process Mapping

Scan Optimization

FloorPlanning and

Algorithmic

Scan Signal

ReOrdering

Macrocell FloorPlanning

Timing Driven Cell Placement

Timing Driven Routing

Clock Tree Synthesis

Place&Route

Scan Ports

JTAG HDL

(8)

Figure 1-3 Why Test?

WHY TEST?

Measurement

of Defects &

Quality Level

Adds Complexity

to Design

Methodology

Adds to

Silicon

Area

Incoming

Inspection

Contractual

Perceived

Product Quality

by Customer

Reliability

Requirement

Contractual

Reasons

Pro & Con Perceptions of DFT

Impacts

Design Speed or

Performance

Impacts

Design Power

& Package Pins

Eases

Diagnosis

& Debugging

Eases

Generation of

Vectors

Provides a

Deterministic

Quality Metric

Reduces

the Cost

of Test

(9)

Figure 1-4 Definition of Testing

DEFINITION of TESTING

EXAMPLE

D Q CLK D Q CLK IN_A IN_D IN_B IN_C OUT_1 OUT_2

1

1 ^

1 X

1 ?

?

with an unknown state

Broadside Parallel Vector A KNOWN EXPECTED RESPONSE A KNOWN STIMULUS DEVICE IN A KNOWN STATE Device or Circuit under test

1 ^

^

X

0 1 S a b a b

(10)

Transistor and Gate Representation of Defects, Faults, and Failures

gate

faults

a

b

c

@

0

0 a

b

c

@

1

Figure 1-5 Measurement Criteria

+

A

B

C

physical

defects

opens

shorts

metal bridges

process errors

transistor

faults

S

2

2 D

G

SB

G

D

2

2 D

SB

observed truth table

A

B

C

failures

0

1

0

1

0

1

0

1

0

1

0

Vdd Vss G S D S D G source-to-drain short D is always at a logic 1

(11)

stuck faults

a

b

c

6 gate faults

@

0

0 a

b

c

@

1

Figure 1-6 Fault Modeling

defects

open/short

bridge

mask

process

delay faults

a

b

c

6 transitions

1-0

0

0 a

b

c

0-1

1

1 transistor faults

s

2

2 d

g

sb

g

d

2

2 d

sb

+

c

ab

00

01

10

11 c

1

0 nand

0

1

0

1

0

1

0

0 ab

a b

c

delay faults

A

B

path

2S

2C

2S

R

A

B

2S

2C

2S

F

B2CR B2CF

1 BIT ADDER with CARRY

A B S C e f a b r t s c

a

b

s

g

d

R=Slow-to-Rise

F=Slow-to-Fall

transition

Truth Table

with fail modes

(12)

faultlist

a

b

e

f

r

t

s

c

16 faults

@

0

0 a

b

e

f

r

t

s

c

@

1

Figure 1-7 Types of Testing A D D E R

3

5

8

0 a

b

s

c

Functional

Structural

3 + 5 = 8

/

4

A B S C e f a b r t s c

(13)

Figure 1-8 Manufacturing Test Load Board

Chip under

Test

The chip will be accessed by the tester at its pins only A custom (load) board will be made for this purpose Each pin has a limited number of bits available (e.g., 2 MB) The test program (set of vectors and tester control) will be applied at tester speed (may be less than actual chip speed) The primary goal of manufacturing test is structural verification

(14)

Figure 1-9 Using ATE

Chip

Loadboard

Power Supply 1

Power Supply 2

Power Supply 3

Clock Gen 1

Clock Gen 2

Clock Gen 3

2 Meg

Memory

Depth

192 Channels

Soc

ke

t

(15)

Figure 1-10 Pin Timing

1. Input Setup Time:

2. Input Hold Time:

time the signal must arrive and be stable before the clock edge to ensure capture

time the signal must remain stable after the clock edge to ensure that capture is stable

1 2 3

3. Output Valid Time:

4. Output Hold Time:

time the signal takes to be valid (or tristated) and stable on the output after the clock edge time that the signal remains available after output valid so that it can be used

NRZ RZ SBC CLK 4 DV

Tester Point of View Chip Point of View

1 1 1 0 0 0 0 0 0

(16)

Figure 1-11 Test Program Components

DC Pin Parametrics

DC Logic Stuck-At

DC Logic Retention

AC Frequency Assessment

Memory Testing

AC Logic Delay

Memory Retention

AC Pin Specification

Idd and Iddq

Test Logic Verification

Specialty Vectors

Analog Functions

Test Escapes

Scan Stuck-At Scan Sequential Scan Path Delay Scan Transition The Venn circles are

examples of DC fault coverages of some of the vector classifications in the test program Some of the fault coverages overlap Vector reduction can be accomplished by removing overlap or by combining vector sets Delay Parametric Functional Test Escapes

(17)

Chapter 2 Automatic Test Pattern Generation Fundamentals 1

Chapter 2 Automatic Test Pattern Generation Fundamentals

Figure 2-1 The Overall Pattern Generation Process

Library Support

Netlist Conditioning

Observe Point Assessment

Vector Generation/Simulation

Vector Compression

(18)

Figure 2-2 Why ATPG?

WHY ATPG?

Greater

Measurement

Ability

Adds Complexity

to Design

Methodology

Eases

Diagnosis

& Debugging

Requires

Tool

Support

Eases

Generation of

Vectors

Reduction

in Cycle

Time

Perceived

Competitive

Methodology

More

Efficient

Vectors

Reasons

Pro & Con Perceptions of ATPG

Requires

Library

Support

Provides a

Deterministic

Quality Metric

Reduces

the Cost

of Test

Requires

Design-for-Test

Analysis

Good

Bad

(19)

Figure 2-3 The ATPG Process

Fault Selection

Fault Observe Point Assessment

Fault Excitation

Vector Generation

Fault Simulation

(20)

GOOD CIRCUIT

X

stuck-at-0 1 0 0 0 0 0 1 force to a 1

a

b

c

d

e

Figure 2-4 Combinational Stuck-At Fault

detected good = faulty 1 1 0 0

FAULTY CIRCUIT

1 0 0 0 1 0 0 1 0 0 0 D I F F E R E N T

(21)

Figure 2-5 The Delay Fault

A

B

C

Z

D

E

F

Delay Model Element Insufficient Transistor Doping

Capacitive or Resistive Wire Delay from Opens Slow Gate Output

Slow Gate Input Delay from Strong Driver

Delay from Extra Load

and Metal Defects Resistive Bridge

Effect of Delay Fault Delay of Transition Occurrence

Changing of Edge-Rate

0

1 “Ideal” Signal

0

Added Rise Delay Added Fall Delay Edge-Rate Layover

The Delay Fault Model is an added delay to net, nodes, wires, gates and other circuit elements

(22)

Figure 2-6 The Current Fault

A

B

C

Z

D

E

F

Leakage Fault Model Leakage from Metastability

Capacitive or Resistive Delay Extends Current Internal Gate Leakage

Leakage from Bridge

Flow Time Resistive Bridge

Effect of a Current Fault is to add extra current flow or to extend flow time The Current Fault Model

is an added Leakage to net, nodes, wires, gates and other circuit elements

I(t)

(23)

e

Figure 2-7 Stuck-At Fault Effective Circuit

1 e

0 X

stuck-at-0 force to a 1

a

b

c

d

e

Detectable

ab

00

01

10

11 z

1

0 nand

c

d

ab

00

01

10

11 z

1

0

0 nor

R E M A P

evaluate fault against the gate’s truth table

evaluate change against the gate’s truth table

evaluate final result against the circuit’s whole truth table

R E M

A P

(24)

Figure 2-8 Fault Masking

GOOD CIRCUIT

X

stuck-at-0 1 0 X 0 1 0 force to a 1

a

b

c

e

not detected good = faulty 1 1 0 X

FAULTY CIRCUIT

1 0 X 1 1 0 0 1 1 X S A M E

(25)

faultlist

a

b

e

f

r

t

s

c

16 faults

@

0

0 a

b

e

f

r

t

s

c

@

1

Figure 2-9 Fault Equivalence Example GOOD - 1 BIT ADDER with CARRY

A

B

S

C

e

f

a

b

r

t

s

c

Fault Equivalence Table

b

a

z

AND

INV

OR

a@0 = b@0 = z@0

a@1 = z@0 : a@0 = z@1

a@1 = b@1 = z@1

r

t

e

a’

a

b

1. Any fault that

requires a logic 1 on the output of an AND-gate will also place 1’s on inputs 2. Similar analysis

exists for all other gate-level elements 3. If one fault is

detected, all

equivalent faults are detected

4. Fault selection only needs to target one of the equivalent faults

(26)

faultlist

A

B

S

C

e

f

a

b

r

t

s

c

a

b

e

f

r

t

s

c

16 faults

@

0

0 a

b

e

f

r

t

s

c

@

1

Figure 2-10 Stuck-At Fault ATPG 1 BIT ADDER with CARRY

A

B

S

C

e

f

a

b

r

t

s

c

1 0

Exercise the Fault

Set Up the Detect and Propagation Path

1 1 0 ₀ 0 1 1 1 1

X

1. Set up the path to pass the opposite of e S @ 0, which is e = 1 2. Exercise by setting

e equal to1

3. Detect by observing S for wrong value during fault simulation

(27)

faultlist

S@Time 1

a

b

e

f

r

t

s

c

16 faults

@

0

0 a

b

e

f

r

t

s

c

@

1

Figure 2-11 Transition Delay Fault

S@Time 2

A

B

S=1

C

e

f

a

b

r

t

s

c

A

B

S

C

e

f

a

b

r

t

s

c

1 0

Exercise the Fault to Pass a 1 Set Up the Detect Path to Pass a 1

1 1 0 ₀ 0 1 1 1 1

A

B

S=0

C

e

f

a

b

r

t

s

c

0 1

Pre-Fail the Fault by Passing a 0

The Transition Delay Faultlist is identical to the Stuck-At Faultlist but

the goal is to detect a Logic Transition within

a given time period

X

0 0 1 1 0 1

1. Set up the path to pass the opposite of e S @ 0, which is e = 1 2. Pre-fail by setting

e equal to 0

3. Exercise by setting e equal to 1 some time period later 4. Detect by observing

S for wrong value during timing simulation

(28)

faultlist

A

B

S@Time1 -> S@Time2

C

e

f

a

b

r

t

s

c

a

b

e

f

t

c

16 faults

@

0

0 a

b

e

f

r

t

s

c

@

1

Figure 2-12 Path Delay Fault 1 BIT ADDER with CARRY

A

B

S

C

e

f

a

r

t

s

c

0->1 1->0

Exercise the Fault (Path)

Set Up the Off-Path

1->1 1->1 0 0 0->0

b

x->x

r @ 0

s @ 0

X

0->1 0->1 1->0

X

x

16.0 pt

1. Set up the path to pass a transition on B-to-S through e, r, and s by setting the off-path values to be stable for 2 time periods

2. Exercise by first setting B equal to 1 and then to 0. This is known as a vector-pair

1. Detect by observing S for wrong value during fault simulation with respect to a time standard

(29)

Figure 2-13 Current Fault

faultlist

A

B

S

C

e

f

a

b

r

t

s

c

a

b

e

f

r

t

s

c

16 faults

@

0

0 a

b

e

f

r

t

s

c

@

1

1 0

Exercise the Fault

1. Exercise by first setting e equal to1

2. Detect by measuring current and accept vector by quietness

(30)

Figure 2-14 Two-Time-Frame ATPG

second-order cone of logic establishes transition and off-path values first-order combinational contains path and off-path logic Defined Critical Path establishes the legal next-state cone of logic Q _D Gate Elements 1->0 1->1 0->0 1->1 Expect Value Transition

bit End of Pathbit

establish

first state next-statelegal next-next-statelegal preset

next-state

1. Launch 1st Value: 2. Launch Transition:

establish path fail value at clock edge provide pass value at next clock edge

3. Capture Transition: observe transition value at this clock edge

1 2 3

Propagation Delay Time

Register Setup Time Slack Time

Solve This Combinational Cone of Logic As the First Step Solve This Combinational

Cone of Logic As Second Step

to Combinational Multiple after Middle Register Values

Are Established by First Cone _{Time Frame Analysis} 1

0

(31)

faultlist

16 faults

Figure 2-15 Fault Simulation example GOOD - 1 BIT ADDER with CARRY

A

B

S

C

e

f

a

b

r

t

s

c

“t” S@1 - 1 BIT ADDER with CARRY

A

B

S

C

e

f

a

b

r

t

s

c

“t” S@0 - 1 BIT ADDER with CARRY

A

B

S

C

e

f

a

b

r

t

s

c

GND + VDD

a

b

e

f

r

t

s

c

@

0

0 a

b

e

f

r

t

s

c

@

1

1. Create multiple copies of the netlist for each fault. 2. Apply same vectors to each copy. 3. Compare each copy to good simulation (expected response). 4. Fault is detected if bad circuit and good circuit differ at a detect point. 5. Measurement is faults detected divided by total number of faults (8/16 = 50%).

(32)

Figure 2-16 Vector Compression and Compaction

Pattern Set 01101110001010 01101110101110 00101110111010 11111110001010 01100000001011 01001011001010 01010101010101 11101100101010 11001110001010 01111000001010 00000000001010 Fault Re-Simulation with Redundant Vector Dropping This Usually Drops

Early Vectors That Are Fully Covered

by Later Vectors and Eliminates Less

Efficient Vectors Simulation Post Processing Compression

1 0 1 0 X X X X X X

Dynamic ATPG Compression

During ATPG a Vector Is Not Submitted to Fault Simulation

until Multiple Faults have been Targeted — “X”s Mapped

This can Greatly Increase Vector Generation Time X

one targeted fault

But Usually Results in the Most Efficient Vectors

(33)

Figure 2-17 Some Example Design Rules for ATPG Transistor

D

Q

CLK

SET

D

Q

CLK

CLR

General Combinational Logic

Propagation Timing Distance Must Be Less Than One Test Clock Cycle

Structure

Equivalent Gate Structure

Combinational Feedback Results in Latches, Oscillators, or Endless Loops

ATPG May Only Operate on Gate-level Elements

(34)

Figure 2-18 ATPG Measurables

ATPG

TOOL

Design

Description

ATPG

Library

Faultlist

Management

_Runscripts

Detected

Faults

Vectors

Sizing

Complexity

Runtime

Features

Support

Files

Vector

Compression

Vector

Translation

algorithms

rule checks

(35)

Chapter 3 Scan Architectures and Techniques 1

Chapter 3 Scan Architectures and Techniques

Figure 3-1 Introduction to Scan-based Testing

Chip under Test with Full-Scan - >1,000,000 gates - >5,000,000 faults - >10,000 flip-flops - < 500 chip pins * > 2,000 gates/pin - > 1,000 sequential depth * > 2M = 21000 - >1,000,000 gates - >5,000,000 faults - > no effective flip-flops - < 500 + 10,000 chip pins * > 95.23 gates/pin - > no sequential depth * > 2M = 20 = 1

A deep sequential circuit

A combinational circuit Chip under Test without Scan

(36)

Chapter 3 Scan Architectures and Techniques 2 Q D Q D Q D input1 input2 input3 clk input5 output2 output1 Combinational &

Figure 3-2 An Example Non-Scan Circuit

Sequential Logic QN input4 input6 Q D 1 2 3 4 Sequential Depth of 4 Combinational Width of 6 26+4 = 1024 Vectors

(37)

Chapter 3 Scan Architectures and Techniques 3 input1 input2 input3 input5 output2 output1 Combinational-Only Logic

Figure 3-3 Scan Effective Circuit

input4 input6 TPO2 TPI4 TPI3 TPI2 TPI1 TPO4 TPO3 TPO1 TPI5

A no-clock, combinational-only circuit with: 6 inputs plus 5 pseudo-inputs and

2 outputs plus 4 pseudo-outputs

D D D D Q Q Q Q QN

(38)

Figure 3-4 Flip-Flop versus Scan Flip-Flop Regular D Flip-Flop

D

_Q

CLK

QN

D Q clk

D

Q

SDI

SE

CLK

QN

D Q clk

SDO

Scannable D Flip-Flop

SDO

(39)

Figure 3-5 Example Set-Scan Flip-Flops

Set-Scan D Flip-Flop

D

Q

CLK

QN

D Q clk

SDI

SE

SET

D

Q

SE

SDI

CLK

QN

D Q clk

SDO

Set-Scan D Flip-Flop

SET

SDO

with Set at Higher Priority

(40)

Chapter 3 Scan Architectures and Techniques 6 Q D Q D Q D input1 input2 input3 clk input5 output2 output1 Combinational and

Figure 3-6 An Example Scan Circuit with a Scan Chain

Sequential Logic QN input4 input6 Q D SDI SE SE SDI SE SDI SE SDI SE scanin SDO SDO SDO SDO scanout 1 0 1 1

(41)

Figure 3-7 Scan Element Operations

The scan cell provides observability and controllability of the signal path by conducting the four transfer functions of a scan element.

Operate: D to Q through port a of the input multiplexer: allows normal transparent operation of the element.

Scan Sample: D to SDO through port a of the input multiplexer: gives observability of logic that fans into the scan element.

Scan Load/Shift: SDI to SDO through the b port of the multiplexer: used to serially load/shift data into the scan chain while simultaneously unloading the last sample.

Scan Data Apply: SDI to Q through the b port of the multiplexer: allows the scan element to control the value of the output, thereby controlling the logic driven by Q.

Scannable D Flip-Flop

D

Q

SDI

SE

CLK

QN

SDO

D Q clk a b

(42)

Figure 3-8 Example Scan Test Sequencing

D Q SDI SE=1 CLK QN SDO D Q clk

Scan Apply Mode (Last Shift)

D Q SDI CLK QN SDO D Q clk

Functional Operation Mode

Scan Shift Load/Unload Mode

Scan Sample Mode

While the clock is low,

apply test data to SDI and Place SE = 1

From normal operation:

At the rising edge of the clock, test data will be loaded

Apply clocks for scan length

When chain is loaded, the last shift clock will apply scan data

While the clock is low, place SE = 0

Normal circuit response will be applied to D

The next rising edge of the clock

Return to Load/Shift mode to unload circuit response sample NOTE: unloading is simultaneous with loading the next test

Repeat operations until all vectors have been applied

NOTE: the chip’s primary inputs must be applied during the scan apply mode (after the last shift)

will sample D

(43)

Figure 3-9 Example Scan Testing Timing

The First Shift Out The Scan Sample

The Last Shift In

CLK SE

The Output Pin Strobe

Faults Exercised Interval SHIFT DATA SHIFT DATA FAULT EXERCISE SHIFT DATA SHIFT DATA SAMPLE DATA

(44)

Figure 3-10 Safe Scan Shifting

Driven Contention

During Scan Shifting

D Q

CLK

Q D

CLK

Q D

CLK

Asynchronous or Synchronous

Signals with Higher Priority

than Scan—or Non-Scan Elements

D

Q

CLK

CLR

HOLD

SET

Gated Clock Nets

t_seB

D Q

CLK

D

Q

CLK

CLR

HOLD

SET

f_seB f_seB

Provide a Forced Mutual Exclusivity Provide a Blocking Signal Provide an Enable Signal

clock tree

distribution

(45)

t_seB de-asserted

Figure 3-11 Safe Scan Vectors

The First Shift Out The Scan Sample

CLK SE

Faults Exercised Interval

t_seB

Driven Contention

during the Capture Cycle

D Q

CLK

D Q

CLK

Q D

CLK

Q D

CLK

a tristate scan enable may be a separate signal that has slightly different timing than

(46)

Figure 3-12 Partial Scan

input1 input2 input3 input5 output2 output1 Combinational-Only Logic input4 input6 TPI3 TPI2 TPI1 TPO4 TPO3 TPO1 TPI5

A clocked, sequential circuit with depth=1: 6 inputs plus 4 pseudo-inputs and

2 outputs plus 3 pseudo-outputs

D D D D Q Q Q Q QN

(47)

Chapter 3 Scan Architectures and Techniques 13 One Long Scan Chain Many Variable Length Scan Chains Many Balanced Scan Chains One Channel Each Vector is 1000 Bits Long

So 5 Vectors Are 5000 Bits of Tester Memory

10 Non-Balanced

Vector Data

An Example Using a Chip with 1000 Scan Bits and 5 Scan Vectors

Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data 10 Balanced Channels 100 Channels 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100

Each Vector Is 100 Bits Long—So 500 Bits of Tester Memory

Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data

Each Vector Is 180 Bits Long—So 900 Bits of Tester Memory Differences from Longest Chain (180) Are Full of X’s—Wasted Memory

No Wasted Memory Space

X XXX XX XX XXX XXXX XX X 120 80 100 110 90 180 20 100 X XXX XX XX XXX XXXX XX X X XXX XX XX XXX XXXX XX X X XXX XX XX XXX XXXX XX X 120 80 100 110 90 180 20 100 120 80 100 110 90 180 20 100 120 80 100 110 90 180 20 100

X’s on all Other Channels not actively used for parallel pin data

1000 1000 1000 Vector Data 1000 XX XX XX XX XX XX XX XX 100 100 100 100 Vector Data Vector Data 100 100 100 100 100 100 100 100 100 100 100 100 Vector Data Vector Data

Red Space Is Wasted Tester Memory

(48)

Figure 3-14 The Borrowed Scan Interface Pad

Any Bidir

Functional Normal Input

Parallel Scan SE

Input Q

Borrowed DC Scan Input on Bidirectional Pin

Combinational

Logic D S

Input to Chip to Logic

Input Scan Interface—May Resolve to Functional during Sample Interval

Output Data Path Output Enable

Pad

SE

Output Q

Borrowed DC Scan Output on Bidirectional Pin

D S

Output Scan Interface—May Resolve to Functional during Sample Interval

Input Data Path Is a Combinational

Logic Blocked during Scan Shift with bus_se Scan

Data Input

Pin

Captures Directly from the Input Pin During

the Shift Operation Captures through the

Combinational Logic during the Sample Operation

Any Bidir Pin s a b Added Scan Output Mux with bus_se or scan_mode

Combinational Logic

Functional Output Enable with bus_se or scan_mode added

Scan Data Output Combinational Logic Don’t Care during Scan Shift Last Scan Shift Bit

from Scan Chain Normal Output from Logic SE Input Q D S SE on Input Blocks Data or scan_mode SE

(49)

Figure 3-15 Clocking and Scan

Analog

Digital 1

Digital 2

Raw VCO

Clock

VCO

Counters &

Dividers

On-Chip Clock Generation Logic

• Scan Bypass Clocks

• Scan Testing an On-Chip Clock Source

(50)

Figure 3-16 Scan-Based Design Rules

Driven Contention

during Scan Shifting

D Q

CLK

Q D

CLK

Q D

CLK

Asynchronous or Synchronous

Signals with Higher Priority

than Scan—or Non-Scan Elements

D

Q

CLK

CLR

HOLD

SET

Gated Clock Nets

t_seB

D Q

CLK

D

Q

CLK

CLR

HOLD

SET

f_seB f_seB

Provide a Forced Mutual Exclusivity

Provide a Blocking Signal

(51)

Figure 3-17 DC Scan Insertion

Basic Netlist Scan Insertion

Element Substitution

Ports, Routing & Connection of SE

Ports, Routing & Connection of SDI-SDO

Extras

Tristate “Safe Shift” Logic

Asynchronous “Safe Shift” Logic

Gated-Clock “Safe Shift” Logic

Multiple Scan Chains

Scan-Bit Re-Ordering

All Scan Chains (Clocks) Shift Last Shift

Only One Clock Domain Conducts a Sample Clock

All Non-Sampling Clock Domains

Inhibit Sample Clock Pulse

Clock Considerations

(52)

Figure 3-18 Stuck-At Scan Diagnostics

1 0 1 1 0 0 0 1 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0 1 1 0 0 0 1 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 0 0 1 1 1

0

1

0

1

0

Scan Fail Data Presented at Chip Interface Automatically

Implicates the Cone of Logic at One Flip-Flop

Multiple Fails under the Single Fault Assumption

Implicate Gates Common to Both

(53)

Figure 3-19 At-Speed Scan Goals

Basic Purpose

• Frequency Assessment

• Pin Specifications

• Delay Fault Content

Cost Drivers

• No Functional Vectors

• Fewer Overall Vectors

• Deterministic Grade

(54)

Figure 3-20 At-Speed Scan Testing

The Transition Capture The Transition Launch

CLK

Transition Generation Interval

The First Shift Out

Faults Exercised Interval SE

T_SE

Bus_SE F_SE

Separate Scan Enables for Tristate Drivers, Clock Forcing Functions, Logic Forcing Functions, Scan Interface Forcing Functions,

and the Scan Multiplexor Control Because the Different Elements Have

(55)

Figure 3-21 At-Speed Scan Architecture Pad Any Bidir Pin Normal Input Parallel Scan SE Input Q

Borrowed Scan Input with Scan Head Register

Combinational Logic D S D Input Q Driven Contention During Scan Shifting

D Q CLK Q D CLK Q D CLK

Asynchronous or Synchronous Signals with Higher Priority than Scan or Non-Scan Sequential Elements

D Q CLK CLR HOLD SET t_seB D Q CLK D Q CLK CLR HOLD SET f_seB Input to Chip to Logic

At-Speed Assert and De-Assert

At-Speed Scan Interface—Resolves to Functional During Sample Interval

Output Data Path Blocked during Scan Shift Output Enable with bus_se

(56)

Figure 3-22 At-Speed Scan Interface Pad

Any Bidir

Functional Normal Input

Parallel Scan SE

Input Q

Borrowed AC Scan Input on Bidirectional Pin

Combinational

Logic D S

Input to Chip to Logic

Input Scan Interface—Resolves to Functional during Sample Interval

Output Data Path

Output Enable Combinational

Logic Blocked during Scan Shift

with at-speed bus_se Scan

Data Input

Pin

Captures Directly from the Input Pin During

the Shift Operation Captures through the

Combinational Logic during the Sample Operation

D Input Q Head Pad SE Output Q

Borrowed AC Scan Output on Bidirectional Pin

D S

Output Scan Interface—Resolves to Functional During Sample Interval

Input Data Path Is a

Any Bidir

Pin a

b Added Scan Output Mux with bus_se

Combinational Logic

Functional Output Enable with bus_se Added

Scan Data Output Combinational Logic Don’t Care during Scan Shift Last Scan Shift Bit

from Scan Chain Normal Output from Logic SE Input Q D S SE on Input Blocks Data D Output Q Tail s

(57)

Figure 3-23 Multiple Scan and Timing Domains

Fast

Logic LogicSlow

Legal ATPG

Transfer Illegal ATPGTransfer

Only Fast-to-Slow Legal ATPG Transfer Applied Slow Clock Applied Fast Clock Last Scan Shift Edge Fast to Slow Transfers Fast to Slow Transfers Slow to Fast Transfers Fast Scannable

System Registers System RegistersSlow Scannable

The Clock Domains and Logic Timing should be crafted so that the very next rising edge after the launch or last shift

is the legal capture edge Clock A

Scan Enable A

Clock B Scan Enable B

(58)

Figure 3-24 Clock Skew and Scan Insertion

D SDI Q scanned flip-flop D SDI Q D SDI Q Combinational Logic Combinational Logic

Cross Domain Clock Skew must be managed to less than the fastest 120 ps 165 ps Combinational Logic 150 ps D SDI Q scanned flip-flop D SDI Q D SDI Q Combinational Logic Combinational Logic

Second Clock Domain—All Elements on Same Clock Tree

120 ps 165 ps Combinational Logic 150 ps 300ps+

First Clock Domain — All Elements on Same Clock Tree

CLK SE

Cross Domain

Clock Skew

CLK SE

flip-flop update time in the launching clock domain

If it is not, then the receiving flip-flop may receive new-new scan data before the capture clock arrives

To prevent this outcome, constrain the ATPG tool to only sample one clock domain at a time during the sample interval

(59)

Figure 3-25 Scan Insertion for At-Speed Scan

Design Flow Chart

Model Simulation Synthesis Timing Place Mask Verification Analysis and Route and Fab Silicon Test Scan Mode Bus_SE Tristate_SE Scan Shift SE Clock Force_SE Scan Data Specification Determination Logic Force_SE Architecture Development Specification Development Connection Insertion Bus_SE: Tristate_SE: Scan Mode: Force_SE:

Scan Enable (SE): Scan Shift Force_SE: Clock Force States

Scan Interface Control Fixed “Safe” Logic

Logic Forced States Internal Tristates Scan Chain Bit

Re-Ordering

Behavior

Gates

Mask

(60)

Figure 3-26 Critical Paths for At-Speed Testing

In3

Static Timing Analysis Provides Path Description

Isolated Combinational Logic All Fan-in to Endpoint Is

U35

U36

U37

U39

In4

In2

In1

D Q

R1

D Q

R2

Out1

A

B

A

B

A

B

of Identified Critical Path from the Q-Output of R1 to the Device Output Pin—Out1

1>0 1>0 0>1 0>1 X 0 0 0 1 0

Accounted at this Endpoint Fanout to other Endpoints is Evaluated atThose Endpoints

U38

A

B

1

Period = 20ns : Output Strobe @ 15ns

Incremental

Delay

Cumulative

Delay

Clk

2.2ns

Skew Amb.

R1.Q

0.0ns

U35.A

U35.Z

U37.A

U37.Z

U38.A

U38.Z

Out1

0.1ns

3.2ns

0.2ns

2.2ns

0.1ns

2.1ns

2.2ns

5.4ns

5.6ns

7.8ns

7.9ns

Dly=10.1 Slk=4.9ns

2.1ns

Path Element

Description

(61)

Figure 3-27 Logic BIST

Chip with Full-Scan

LFSR - PRPG: pseudo-random pattern generation

D Q D Q D Q

CLK

LFSR - MISR: multiple input signature register

D Q CLK and X-Management D Q D Q 1 1 1 Seed X3 X2 X1 X0 Polynomial: X3 + X +1 = X3 + X1 + X0 = 23 + 21 + 20 = 11 111 011 001 100 010 101 110 111

(62)

Figure 3-28 Scan Test Fundamentals Summary

Direct Observability of Internal Nodes

Direct Controllability of Internal Nodes

Enables Combinational ATPG

Scan Testing Methodology

More Efficient Vectors

Higher Potential Fault Coverage

Deterministic Quality Metric

Efficient Diagnostic Capability

Advantages

Concerns

Safe Shifting

Safe Sampling

Power Consumption

Clock Skew

Design Rule Impact on Budgets

(63)

Chapter 4 Memory Test Architectures and Techniques 1

Chapter 4 Memory Test Architectures and Techniques

Figure 4-1 Introduction to Memory Testing

Logic Embedded

JTAG Boundary Scan

PLL TAP

Chip-Level

Memory

(64)

Figure 4-2 Memory Types

6 Transistor SRAM Cell

Column/Bit-Data Column/Bit-Data

Row/Word-Address

Column/Bit-Data Row/Word-Address

1 Transistor DRAM Cell

Column/Bit-Data

Row/Word-Address

2 Transistor EEPROM Cell Storage Select

Select Storage

Select Select

(65)

Figure 4-3 Simple Memory Organization

Memory: Data Width by Address Depth 32 x 512 Data In Address In Read/WriteBar Output Enable Data Out

Data Bus: To Multiple Memory Arrays

Address Bus: To Multiple Memory Arrays

Memory Array

Address Decode to Row Drivers Data Decode to Column Drivers Control Circuitry to Read, Write,

and Data Output Enable

Control Signals: Individual Signals to This Memory Array

Bus Enable

(66)

Figure 4-4 Memory Design Concerns

Chip FloorPlan

Memory 1

Memory

2 M

e

m

o

r

y

3 Memory 4

- Aspect Ratio

- Access Time

- Power Dissipation

(67)

Figure 4-5 Memory Integration Concerns

Chip FloorPlan

Memory 1

Memory

2 M

e

m

o

r

y

3 Memory 4

- Routing

- Placement & Distribution

- Overall Power Dissipation

Processor

Local

(68)

Figure 4-6 Embedded Memory Test Methods

Embedded Microprocessor Core Embedded Memory Array Embedded Memory Array BIST Controller Embedded Memory Array 32 24 3 32 24 3

Functional Memory Test

Direct Access Memory Test

BIST Memory Test Data Control Address Data Address Control Invoke Reset Hold Done Fail

(69)

Chapter 4 Memory Test Architectures and Techniques 7 row # —> 0 column # —> row # —> 1 row # —> 2 0 1 2 3

data bit cell

Figure 4-7 Simple Memory Model

0 1 0 0 0 0 1 1 1 1 1 1

(70)

0 1 1

1 0 1 0

single bit stuck-at 1 word stuck-at

single bit stuck-at 0

data value 1110

address A031—>

Figure 4-8 Bit-Cell and Array Stuck-At Faults

1 1 1 0

1

Data in Bit Cells May Be Stuck-At Logic 1 or Logic 0